229 results about "Synchronous circuit" patented technology

A synchronization circuit for an interconnection protocol, a controller and a storage device are provided. The synchronization circuit includes a first synchronization circuit module and a second synchronization circuit module. The first synchronization circuit module converts first control information of a first clock domain output by a data link layer receiver of the first device into second control information of a second clock domain, and outputs the second control information of the second clock domain. The second synchronization circuit module is coupled to the first synchronization circuit module, and converts the second control information of the second clock domain output by the first synchronization circuit module into third control information of a third clock domain to be output to a data link layer transmitter of the first device. Any two among the first, second and third clock domains are asynchronous.

The invention discloses a synchronous circuit and method of an energy storage inverter parallel operation system, and belongs to the field of photovoltaic technology. The circuit comprises a CAN bus; the plurality of synchronous communication components are respectively arranged in each energy storage inverter of the energy storage inverter parallel operation system; the synchronous communication component comprises an ePWM module, and the ePWM module comprises corresponding time base counter registers; one of the energy storage inverters is a host, and the rest of the energy storage inverters are slaves; a main synchronous communication component in the host is used for sending a kth-phase carrier synchronization signal to the CAN bus when a count value of a time base counter register corresponding to the kth phase in the main synchronous communication component is 0; the slave synchronization communication component in each slave is used for setting the count value of the time base counter register corresponding to the kth phase in the slave to be 0 when receiving the kth phase carrier synchronization signal, and k is a positive integer. According to the embodiment of the invention, synchronous operation among the energy storage inverters can be realized, and the operation reliability and safety of the parallel operation system are ensured.

The invention relates to the technical field of communication and anti-interference, in particular to an ultra-wideband frequency hopping circuit and a fast synchronization method, which adopt an image frequency rejection receiving framework to dehop wideband microwave frequency hopping signals to obtain intermediate frequency signals, and adopt a mode of combining dual-channel AD differential sampling and rising edge detection with threshold detection to realize fast synchronization of the ultra-wideband frequency hopping signals. Precise identification and tracking of the phase of the envelope detection signal are realized, rapid following hopping of the local oscillation frequency hopping signal of the receiver is further realized, and the problems of complex synchronization circuit, poor acquisition precision, long synchronization process establishment time and the like in the traditional frequency hopping synchronization process are solved. According to the invention, while high-precision frequency hopping synchronization is realized, hardware resources are saved, and synchronization establishment time is shortened.

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

A receive clock generated at a receiver coupled to a single wire bus is synchronized in each clock cycle, allowing for receiving infinite length data frames without clock overflow or underload. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in the output of the clock gating circuit. The clock gating circuit is disabled when the output of the counter indicates a pre-configured maximum count value. An edge synchronization circuit that synchronizes an edge in the basic clock signal with an edge in a data signal received through the single wire bus ignores the edge in the data signal when the counter output has a value less than the maximum count value, and resetting the counter in response to an edge detected in the data signal received through the single wire bus.

The invention discloses a variable-sampling-rate current waveform and electromagnetic response acquisition system and a control method. The variable-sampling-rate current waveform and electromagnetic response acquisition system comprises nine parts, namely a sensor circuit, a signal conditioning circuit, an analog-to-digital conversion circuit, an analog-to-digital isolation circuit, a main control circuit, a synchronous circuit, a storage circuit, a man-machine interaction circuit and a power management module. The voltage signal is firstly processed by the signal conditioning circuit to meet the sampling requirement of the 24-bit ADC module, and then the ADC module converts an analog voltage signal into a binary digital signal based on a reference voltage; and under the action of a clock signal of the synchronization module, the converted digital signal is firstly transmitted to an external SRAM (Static Random Access Memory) through DMA (Direct Memory Access) to be cached and stored. Interference of digital circuits such as a single-chip microcomputer and crosstalk of analog signals among different channels are effectively reduced, and the problems that an acquisition system is single in sampling rate, high in short-circuit noise level, large in shallow detection blind area and low in urban underground space complex target electromagnetic detection precision are solved.

The invention provides an SRAM (Static Random Access Memory) setup and hold time test circuit structure and system. The structure comprises a synchronous circuit, a first delay circuit, a second delay circuit, a third delay circuit and a test control circuit, the synchronous circuit comprises a clock signal input end, a test signal switching input end, a clock signal output end, an address signal output end and a data signal output end; the first delay circuit comprises a first control end, a clock signal delay input end and a clock signal delay output end; the second delay circuit comprises an address signal delay input end, a first selection input end and an address signal delay output end; the third delay circuit comprises a data signal delay input end, a second selection input end and a data signal delay output end. And the synchronous clock signal, the synchronous address signal and the synchronous data signal are homologous, so that the problem that errors exist in the acquired SRAM setup and hold time due to delayed synchronous processing can be obviously reduced.

The invention discloses a real-time time service industrial personal computer, and relates to the technical field of industrial personal computers, the real-time time service industrial personal computer comprises a main control board and a PCIe time code card, the PCIe time code card is connected with the main control board through a PCIe bus, and a GNSS time service module, a temperature compensation crystal oscillator and a PPS synchronous circuit are integrated on the PCIe time code card; the GNSS time service module is used for receiving a satellite signal and outputting a UTC timestamp and a 1PPS pulse signal; the temperature compensation crystal oscillator is used as a local clock source, and the PPS synchronous circuit is used for directly outputting 1PPS signals when satellite signals are available and switching to compensated crystal oscillator PPS signals when the satellite signals are lost; when the industrial personal computer is powered on, the PPS pulse triggers the clock of the main control board to be reset, the PCIe time code card transmits calibrated time-varying data to the main control board in real time, and the main control board distributes a synchronous clock signal with the precision of + / -1 microsecond to external equipment through an industrial bus protocol according to the time-varying data provided by the PCIe time code card. According to the invention, the problem of insufficient time service precision of a traditional industrial personal computer is solved.

A phase adjustment circuit (11) of a received signal quality monitor is capable of performing phase scanning of a sampling clock signal (phi e) of a reference sampler in a phase range that is several times the unit interval (UI) of a serial data signal. A first synchronization circuit (13A) receives a first output signal of one sampler included in the plurality of data receiving samplers and a second output signal of the reference sampler (SMe). A first output signal and a second output signal synchronously output from the first synchronization circuit (13A) are input to a comparison logic circuit (15), and the comparison logic circuit (15) outputs a comparison result relating to the quality of the received signal.

A system for the automated collection of test results and conformity reporting in IT service management environments. The system includes: a structural enclosure configured to enclose a variety of electronic components, wherein the structural enclosure is equipped with power supply circuits, thermal control units and electromagnetic shielding; at least one processor located within the structural housing and electrically connected to a communication controller, wherein the processor is configured to execute instructions for interface with distributed data sources for information technology service management; The communications controller includes a variety of encrypted data transmission circuits configured to securely extract evidentiary data from service management logs, access control records, configuration baselines, and monitoring databases; a compliance controller electrically connected to the processor, wherein the compliance controller comprises a rule-based processing unit configured to identify evidence artifacts required by a compliance framework, and a verification processing unit configured to validate the integrity, completeness, and format of the extracted artifacts; a time synchronization circuit electrically coupled to the compliance controller, wherein the time synchronization circuit is configured to assign tamper-proof cryptographic timestamps to each evidence artifact at the capture location; a memory management circuit electrically connected to the non-volatile memory, wherein the memory management circuit is configured to organize the validated evidence artifacts in a hierarchical and indexed data structure, with indexing being performed according to service identifiers and conformance categories; a hardware security controller located within the structural enclosure, wherein the hardware security controller includes a secure enclave configured to store cryptographic keys and to digitally sign evidence artifacts and compliance reports prior to their transmission; and an output interface that is electrically connected to the compliance controller and the hardware security controller, wherein the output interface is configured to generate compliance reports in both machine-readable structured formats and human-readable formatted documents and to transmit these reports to authorized audit systems.

The invention provides a clock signal synchronization circuit and system, which can be applied to the technical field of signal transmission. The circuit comprises: a first node, the first node comprising: a phase-locked loop unit configured to perform frequency multiplication on a system clock signal according to a predetermined frequency multiplication coefficient to obtain a reference clock signal; the first asynchronous storage unit is configured to write in to-be-transmitted data based on the system clock signal, read out the to-be-transmitted data based on the reference clock signal and transmit the to-be-transmitted data to a second node, and the to-be-transmitted data comprises an identification code located at an initial position; and the second node is configured to align the recovery clock signal with the to-be-transmitted data according to the identification code in the to-be-transmitted data, generate a clock reset signal, perform frequency division on the recovery clock signal according to the clock reset signal and a predetermined frequency multiplication coefficient to obtain a frequency division clock signal, and output the to-be-transmitted data based on the frequency division clock signal.

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

The invention relates to a cross-clock-domain data synchronization method, an FIFO control circuit and a synchronization circuit, and the method comprises the steps: obtaining a first clock cycle number passed by a source clock domain in target time if the write clock frequency of the source clock domain is different from the read clock frequency of a target clock domain, the first clock period number and the second clock period number passed by the target clock domain within the target time are both integers; under the condition that the first clock cycle number is larger than the second clock cycle number, multiple first effective clock signals are generated every time a target time passes, the multiple first effective clock signals are generated within the target time, the number of the first effective clock signals is the second clock cycle number, and data writing control is carried out based on the first effective clock signals, the cross-clock domain data synchronization is completed; according to the method, the cross-clock-domain data synchronous transmission between clocks with different frequencies is well realized, the implementation is relatively high, and the cost is relatively low.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and a jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine that converts this data into frequency-domain data. The spectrum hardware engine has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to a computing device to estimate phase noise.

The invention discloses a phase synchronization circuit, an expanded phase-locked loop circuit and a delay phase-locked loop circuit. The phase synchronization circuit comprises a clock comparison unit, a biasing circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter and a clock output unit. The clock comparison unit is connected with the clock output unit, the charge pump circuit and the time / analog conversion circuit; the biasing circuit is connected with the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected with the compensation charge pump circuit; the loop filter is connected with the charge pump circuit, the compensation charge pump circuit and the clock output unit. According to the phase synchronization circuit and the expansion structure thereof, time information can be directly converted into voltage for leakage current compensation, so that comparison action based on the voltage is not needed, and analog circuits such as an integrated operational amplifier and a voltage comparator are not needed. Therefore, it is possible to suppress an increase in the chip area of the compensation circuit and to reduce the phase error of the output clock.

The invention relates to the technical field of circuit layout optimization, in particular to a low-EMI synchronous circuit layout optimization system which comprises a signal analysis module, a layout adjustment module, a resource matching module, a task execution module and a process optimization module. According to the invention, through difference analysis of high-frequency and low-frequency signal paths and extraction of an interference intersection dense area, accurate positioning and quantitative management of an electromagnetic interference source are realized, a potential interference risk area in a circuit is effectively identified, determination is carried out in combination with coupling characteristics of component arrangement spacing and signal line trend, the identification efficiency is improved, and the identification accuracy is improved. The positions of components are accurately adjusted through an overlapping matching mode of resource positions and adjustable areas, the signal crosstalk and radiation risks are reduced, the task load proportion and the scheduling time interval trend are combined, the design process node configuration sequence is optimized, the response capability of layout adjustment and the execution priority matching precision are improved, and the layout adjustment efficiency is improved. Therefore, the cooperative improvement of the interference suppression effect and the design efficiency is realized.

The invention provides a software operation synchronization method and system based on a dual-chip architecture, and abandons a traditional mode depending on a UART / SPI / CAN communication protocol or an additional synchronization circuit. Firstly, a unique PWM duty ratio mapping relation with any difference not smaller than 5% is preset for the initial state, the system self-checking state, the OTA upgrading state, the running state, the fault state, the dormancy preparation state and other running states of the double-chip system, and then a chip A and a chip B continuously output PWM signals matched with the current states of the chip A and the chip B through common GPIO pins in a push-pull output mode. Meanwhile, PWM signals of GPIO pins of the opposite side are collected in real time in a bidirectional mode through respective hardware capture units, the duty ratio is analyzed to obtain the state of the opposite side, response operation is executed according to preset logic, synchronization failures caused by communication delay and data frame error codes of a traditional software protocol are effectively avoided, the system stability is guaranteed, meanwhile, a complex protocol stack does not need to be designed, and the cost is reduced. The CPU load rate is reduced, an additional synchronous circuit is omitted, the chip area and power consumption are reduced, and the hardware cost is reduced.

The invention discloses a frequency division synchronous circuit applied to a multi-channel analog-to-digital converter. The frequency division synchronous circuit is composed of three main modules including a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit. A multi-channel analog-to-digital converter needs a reasonably designed clock system to provide a time sequence basis for cooperative work of all modules, however, an existing clock system has the problems of large jitter, fuzzy state, low efficiency and the like, and the multi-channel analog-to-digital converter based on the problems is difficult to meet the requirements of rapidly developed communication and detection array systems. According to the improved clock system, the sampling clock jitter is reduced through the edge reconstruction technology, so that the sampling noise is improved, and the conversion precision is improved; the phase ambiguity of frequency division is eliminated through a synchronization strategy, data processing and correction are facilitated, the device can be controlled to be reset to a specific initial state, and array application is facilitated; through a bus type clock distribution strategy, the number of clock transmission lines is reduced, and the circuit operation efficiency is improved.

The invention provides a synchronization circuit, and relates to the technical field of communication, the synchronization circuit comprises N integration unit circuits, and the target integration unit circuit is used for comparing whether a target symbol value in a received current synchronization sequence is consistent with a preset symbol value of a corresponding bit in a preset weight sequence specified by a protocol; charging or discharging the positive output end of the target integration unit circuit and the negative output end of the target integration unit circuit according to a preset symbol value; and the N integration unit circuits are used for integrating the bias current and comparing the voltage difference between the target positive output end and the target negative output end after the integration is finished so as to determine whether the synchronization succeeds or not. By implementing the technical scheme provided by the invention, the effect of reducing the power consumption of the synchronous circuit is achieved.

The utility model relates to the technical field of synchronous rectification, in particular to a novel synchronous rectification module integrated with an output capacitor, which comprises a transformer body, a main circuit board, an output filter capacitor, a first synchronous circuit board, a second synchronous circuit board, a filter circuit board and a golden finger circuit board assembly. The transformer has the advantages that the filter circuit board is arranged at the top of the transformer body, on one hand, the filter circuit board is provided with a plurality of electronic components, and the arrangement pressure of the electronic components and copper laying wires of the first synchronous circuit board, the second synchronous circuit board and the main circuit board can be reduced; and on the other hand, a plurality of output filter capacitors are arranged on the transformer body close to the output side of the switching power supply and are electrically connected with the filter circuit board through jacks, so that the space between the side surface of the transformer body close to the output and a switching power supply shell is effectively utilized, and the output ripple and dynamic characteristics of the switching power supply can be effectively improved.

This application relates to the field of automatic feeding technology, and provides a distributed control method and system for feeding motor rotor laminations. The method includes: setting up programmable logic controllers (PLCs) at multiple feeding nodes, each controller connected to a synchronous Buck topology circuit; reading and parsing the feeding task script, identifying the collaborative feeding nodes and their task control precision from multiple feeding nodes; sending a precision synchronization command to a coordination terminal based on the task control precision to obtain a corresponding fluctuation limiting signal; and the coordination terminal performing distributed collaborative control on the output of the synchronous Buck circuit connected to the collaborative feeding nodes based on the fluctuation limiting signal to complete the execution of the feeding task script. This application solves the technical problems of inconsistent actions and large precision fluctuations caused by independent control of each feeding node in the traditional motor rotor lamination feeding process, achieving the technical effect of highly consistent actions of each feeding node and controllable feeding precision through distributed synchronous control and high-precision DC bus clamping.

The invention provides a multi-frequency TDD (Time Division Duplex) analog synchronization circuit and method, which can solve the problems of high cost, poor precision and low sensitivity of a TDD synchronization scheme in the prior art, and comprises a radio frequency selection path used for selecting and outputting a single-frequency-band radio frequency signal from input radio frequency signals according to a control signal; the detector is connected with the radio frequency selection path and used for performing envelope detection on the target radio frequency signal, and the detector is provided with an inverted output end VDN; the processor comprises an ADC input end, and the ADC input end is connected with the inverted output end VDN of the detector and used for collecting the detected voltage signals; the processor is also connected with the radio frequency selection path and is used for sending a control signal to control the radio frequency selection path to gate a corresponding frequency band channel; the processor identifies the frame header position of the radio frequency signal according to the voltage signal collected by the ADC input end, and outputs an uplink switching signal and a downlink switching signal.

A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

A device includes: a receiver path; and a demodulator having an input coupled to an output of the receiver path; a first STF synchronization circuit coupled to the output of the receiver path and configure to: detect a first synchronization sequence of a first packet in a first subcarrier, and in response to detecting the first synchronization sequence, cause the demodulator to process a rest of the first packet, where the first packet is received by the receiver path using a single subcarrier at a time; and a second STF synchronization circuit coupled to the output of the receiver path and configure to: detect a second synchronization sequence of a second packet in a second subcarrier, and in response to detecting the second synchronization sequence, cause the demodulator to process a rest of the second packet, where the second packet is received using a single subcarrier at a time.

The application discloses a circuit for preventing upper and lower pipes of a dcdc from conducting simultaneously, and relates to the technical field of synchronous Buck circuits, which comprises a control and regulation unit, wherein the control and regulation unit outputs a driving signal to a power switch unit; the driving signal of the control and regulation unit comprises a high-side driving signal (Hdrv), a low-side driving signal (Ldrv), a substrate selection control module, a substrate selection module and a VDD2 generation module; the control and regulation unit outputs a PG signal to the substrate selection control module; the output end of the substrate selection module is electrically connected with the input end of the substrate selection module; the output end of the VDD2 generation module is electrically connected with the input end of the substrate selection module; and the output end of the substrate selection module is electrically connected with the substrate (Psub) of the power switch tube (PM1). The substrate potential of the power switch tube (PM1) is dynamically switched through the substrate selection module, the upper and lower pipes are prevented from conducting simultaneously from the physical layer, the power device is effectively protected, and the circuit stability is improved.

The invention provides a TDD synchronization circuit, a chip and a radio frequency coverage unit, the TDD synchronization circuit comprises a detection circuit and a comparison circuit, the input end of the detection circuit receives a TDD coupling signal, and the detection circuit carries out detection processing on the TDD coupling signal and outputs a TDD modulation signal without carrier waves. The comparison circuit receives the first reference voltage signal and the TDD modulation signal and performs logic processing on the first reference voltage signal and the TDD modulation signal to enlarge the voltage range of the TDD modulation signal and obtain a TDD driving signal, and the TDD driving signal is more beneficial to driving a next-stage circuit, realizing recovery of a TDD time slot signal and participating in switching control of radio frequency uplink and downlink; and the TDD time slot control is accurately carried out. A complex processor and the like are not arranged in the TDD synchronous circuit, the device type selection range is wide, implementation is easy, the response speed is high, TDD synchronization does not need to be conducted through a modem, cost is saved, interference is avoided, and practicability is high.

In an example, a system includes one or more clock channels on a clock chip, each clock channel configured to provide a clock signal. The system also includes a signal line coupled to the one or more clock channels, the signal line configured to send clock signals to and receive clock signals from each clock channel. The system includes a controller configured to select a first clock signal from a first clock channel to drive the signal line. The system also includes divider timing synchronization circuitry in a second clock channel configured to align a second clock signal from the second clock channel with the first clock signal.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The invention provides a clock synchronization circuit and system which can be applied to the technical field of signal transmission. The clock synchronization circuit comprises: a first node comprising: a first port unit configured to send downlink data to a second node via a downlink according to a first sending reference clock obtained based on an input reference clock, and obtain a first recovery clock according to uplink data returned by the second node via an uplink, performing phase adjustment on the first sending reference clock according to the first phase adjustment step length number; a second port unit configured to output a first measurement reference clock according to an input reference clock; the first phase measurement unit is configured to sample an input reference clock and a first recovery clock according to a first measurement reference clock and output a first phase adjustment step length number; and the second node is configured to obtain the second recovery clock according to the downlink data received by the downlink, and send the uplink data through the uplink according to the second sending reference clock.

A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.