152 results about "Synchronous circuit" patented technology

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

The invention discloses a real-time time service industrial personal computer, and relates to the technical field of industrial personal computers, the real-time time service industrial personal computer comprises a main control board and a PCIe time code card, the PCIe time code card is connected with the main control board through a PCIe bus, and a GNSS time service module, a temperature compensation crystal oscillator and a PPS synchronous circuit are integrated on the PCIe time code card; the GNSS time service module is used for receiving a satellite signal and outputting a UTC timestamp and a 1PPS pulse signal; the temperature compensation crystal oscillator is used as a local clock source, and the PPS synchronous circuit is used for directly outputting 1PPS signals when satellite signals are available and switching to compensated crystal oscillator PPS signals when the satellite signals are lost; when the industrial personal computer is powered on, the PPS pulse triggers the clock of the main control board to be reset, the PCIe time code card transmits calibrated time-varying data to the main control board in real time, and the main control board distributes a synchronous clock signal with the precision of + / -1 microsecond to external equipment through an industrial bus protocol according to the time-varying data provided by the PCIe time code card. According to the invention, the problem of insufficient time service precision of a traditional industrial personal computer is solved.

A system for the automated collection of test results and conformity reporting in IT service management environments. The system includes: a structural enclosure configured to enclose a variety of electronic components, wherein the structural enclosure is equipped with power supply circuits, thermal control units and electromagnetic shielding; at least one processor located within the structural housing and electrically connected to a communication controller, wherein the processor is configured to execute instructions for interface with distributed data sources for information technology service management; The communications controller includes a variety of encrypted data transmission circuits configured to securely extract evidentiary data from service management logs, access control records, configuration baselines, and monitoring databases; a compliance controller electrically connected to the processor, wherein the compliance controller comprises a rule-based processing unit configured to identify evidence artifacts required by a compliance framework, and a verification processing unit configured to validate the integrity, completeness, and format of the extracted artifacts; a time synchronization circuit electrically coupled to the compliance controller, wherein the time synchronization circuit is configured to assign tamper-proof cryptographic timestamps to each evidence artifact at the capture location; a memory management circuit electrically connected to the non-volatile memory, wherein the memory management circuit is configured to organize the validated evidence artifacts in a hierarchical and indexed data structure, with indexing being performed according to service identifiers and conformance categories; a hardware security controller located within the structural enclosure, wherein the hardware security controller includes a secure enclave configured to store cryptographic keys and to digitally sign evidence artifacts and compliance reports prior to their transmission; and an output interface that is electrically connected to the compliance controller and the hardware security controller, wherein the output interface is configured to generate compliance reports in both machine-readable structured formats and human-readable formatted documents and to transmit these reports to authorized audit systems.

The invention provides a clock signal synchronization circuit and system, which can be applied to the technical field of signal transmission. The circuit comprises: a first node, the first node comprising: a phase-locked loop unit configured to perform frequency multiplication on a system clock signal according to a predetermined frequency multiplication coefficient to obtain a reference clock signal; the first asynchronous storage unit is configured to write in to-be-transmitted data based on the system clock signal, read out the to-be-transmitted data based on the reference clock signal and transmit the to-be-transmitted data to a second node, and the to-be-transmitted data comprises an identification code located at an initial position; and the second node is configured to align the recovery clock signal with the to-be-transmitted data according to the identification code in the to-be-transmitted data, generate a clock reset signal, perform frequency division on the recovery clock signal according to the clock reset signal and a predetermined frequency multiplication coefficient to obtain a frequency division clock signal, and output the to-be-transmitted data based on the frequency division clock signal.

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

The invention relates to a cross-clock-domain data synchronization method, an FIFO control circuit and a synchronization circuit, and the method comprises the steps: obtaining a first clock cycle number passed by a source clock domain in target time if the write clock frequency of the source clock domain is different from the read clock frequency of a target clock domain, the first clock period number and the second clock period number passed by the target clock domain within the target time are both integers; under the condition that the first clock cycle number is larger than the second clock cycle number, multiple first effective clock signals are generated every time a target time passes, the multiple first effective clock signals are generated within the target time, the number of the first effective clock signals is the second clock cycle number, and data writing control is carried out based on the first effective clock signals, the cross-clock domain data synchronization is completed; according to the method, the cross-clock-domain data synchronous transmission between clocks with different frequencies is well realized, the implementation is relatively high, and the cost is relatively low.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and a jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine that converts this data into frequency-domain data. The spectrum hardware engine has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to a computing device to estimate phase noise.

The invention discloses a phase synchronization circuit, an expanded phase-locked loop circuit and a delay phase-locked loop circuit. The phase synchronization circuit comprises a clock comparison unit, a biasing circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter and a clock output unit. The clock comparison unit is connected with the clock output unit, the charge pump circuit and the time / analog conversion circuit; the biasing circuit is connected with the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected with the compensation charge pump circuit; the loop filter is connected with the charge pump circuit, the compensation charge pump circuit and the clock output unit. According to the phase synchronization circuit and the expansion structure thereof, time information can be directly converted into voltage for leakage current compensation, so that comparison action based on the voltage is not needed, and analog circuits such as an integrated operational amplifier and a voltage comparator are not needed. Therefore, it is possible to suppress an increase in the chip area of the compensation circuit and to reduce the phase error of the output clock.

The invention relates to the technical field of circuit layout optimization, in particular to a low-EMI synchronous circuit layout optimization system which comprises a signal analysis module, a layout adjustment module, a resource matching module, a task execution module and a process optimization module. According to the invention, through difference analysis of high-frequency and low-frequency signal paths and extraction of an interference intersection dense area, accurate positioning and quantitative management of an electromagnetic interference source are realized, a potential interference risk area in a circuit is effectively identified, determination is carried out in combination with coupling characteristics of component arrangement spacing and signal line trend, the identification efficiency is improved, and the identification accuracy is improved. The positions of components are accurately adjusted through an overlapping matching mode of resource positions and adjustable areas, the signal crosstalk and radiation risks are reduced, the task load proportion and the scheduling time interval trend are combined, the design process node configuration sequence is optimized, the response capability of layout adjustment and the execution priority matching precision are improved, and the layout adjustment efficiency is improved. Therefore, the cooperative improvement of the interference suppression effect and the design efficiency is realized.

The invention provides a software operation synchronization method and system based on a dual-chip architecture, and abandons a traditional mode depending on a UART / SPI / CAN communication protocol or an additional synchronization circuit. Firstly, a unique PWM duty ratio mapping relation with any difference not smaller than 5% is preset for the initial state, the system self-checking state, the OTA upgrading state, the running state, the fault state, the dormancy preparation state and other running states of the double-chip system, and then a chip A and a chip B continuously output PWM signals matched with the current states of the chip A and the chip B through common GPIO pins in a push-pull output mode. Meanwhile, PWM signals of GPIO pins of the opposite side are collected in real time in a bidirectional mode through respective hardware capture units, the duty ratio is analyzed to obtain the state of the opposite side, response operation is executed according to preset logic, synchronization failures caused by communication delay and data frame error codes of a traditional software protocol are effectively avoided, the system stability is guaranteed, meanwhile, a complex protocol stack does not need to be designed, and the cost is reduced. The CPU load rate is reduced, an additional synchronous circuit is omitted, the chip area and power consumption are reduced, and the hardware cost is reduced.

This application relates to the field of automatic feeding technology, and provides a distributed control method and system for feeding motor rotor laminations. The method includes: setting up programmable logic controllers (PLCs) at multiple feeding nodes, each controller connected to a synchronous Buck topology circuit; reading and parsing the feeding task script, identifying the collaborative feeding nodes and their task control precision from multiple feeding nodes; sending a precision synchronization command to a coordination terminal based on the task control precision to obtain a corresponding fluctuation limiting signal; and the coordination terminal performing distributed collaborative control on the output of the synchronous Buck circuit connected to the collaborative feeding nodes based on the fluctuation limiting signal to complete the execution of the feeding task script. This application solves the technical problems of inconsistent actions and large precision fluctuations caused by independent control of each feeding node in the traditional motor rotor lamination feeding process, achieving the technical effect of highly consistent actions of each feeding node and controllable feeding precision through distributed synchronous control and high-precision DC bus clamping.

The invention provides a multi-frequency TDD (Time Division Duplex) analog synchronization circuit and method, which can solve the problems of high cost, poor precision and low sensitivity of a TDD synchronization scheme in the prior art, and comprises a radio frequency selection path used for selecting and outputting a single-frequency-band radio frequency signal from input radio frequency signals according to a control signal; the detector is connected with the radio frequency selection path and used for performing envelope detection on the target radio frequency signal, and the detector is provided with an inverted output end VDN; the processor comprises an ADC input end, and the ADC input end is connected with the inverted output end VDN of the detector and used for collecting the detected voltage signals; the processor is also connected with the radio frequency selection path and is used for sending a control signal to control the radio frequency selection path to gate a corresponding frequency band channel; the processor identifies the frame header position of the radio frequency signal according to the voltage signal collected by the ADC input end, and outputs an uplink switching signal and a downlink switching signal.

A device includes: a receiver path; and a demodulator having an input coupled to an output of the receiver path; a first STF synchronization circuit coupled to the output of the receiver path and configure to: detect a first synchronization sequence of a first packet in a first subcarrier, and in response to detecting the first synchronization sequence, cause the demodulator to process a rest of the first packet, where the first packet is received by the receiver path using a single subcarrier at a time; and a second STF synchronization circuit coupled to the output of the receiver path and configure to: detect a second synchronization sequence of a second packet in a second subcarrier, and in response to detecting the second synchronization sequence, cause the demodulator to process a rest of the second packet, where the second packet is received using a single subcarrier at a time.

The application discloses a circuit for preventing upper and lower pipes of a dcdc from conducting simultaneously, and relates to the technical field of synchronous Buck circuits, which comprises a control and regulation unit, wherein the control and regulation unit outputs a driving signal to a power switch unit; the driving signal of the control and regulation unit comprises a high-side driving signal (Hdrv), a low-side driving signal (Ldrv), a substrate selection control module, a substrate selection module and a VDD2 generation module; the control and regulation unit outputs a PG signal to the substrate selection control module; the output end of the substrate selection module is electrically connected with the input end of the substrate selection module; the output end of the VDD2 generation module is electrically connected with the input end of the substrate selection module; and the output end of the substrate selection module is electrically connected with the substrate (Psub) of the power switch tube (PM1). The substrate potential of the power switch tube (PM1) is dynamically switched through the substrate selection module, the upper and lower pipes are prevented from conducting simultaneously from the physical layer, the power device is effectively protected, and the circuit stability is improved.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The invention provides a clock synchronization circuit and system which can be applied to the technical field of signal transmission. The clock synchronization circuit comprises: a first node comprising: a first port unit configured to send downlink data to a second node via a downlink according to a first sending reference clock obtained based on an input reference clock, and obtain a first recovery clock according to uplink data returned by the second node via an uplink, performing phase adjustment on the first sending reference clock according to the first phase adjustment step length number; a second port unit configured to output a first measurement reference clock according to an input reference clock; the first phase measurement unit is configured to sample an input reference clock and a first recovery clock according to a first measurement reference clock and output a first phase adjustment step length number; and the second node is configured to obtain the second recovery clock according to the downlink data received by the downlink, and send the uplink data through the uplink according to the second sending reference clock.

A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.

The present invention relates to the technical field of power equipment, and more specifically, to a code generator for substation identification, comprising a code generator module and a power supply. The code generator module comprises an RC step-down voltage stabilization circuit, a sinusoidal wave phase synchronization circuit, a reactive pulse drive circuit, and an MCU unit, which are electrically associated with each other. The MCU unit performs bit expansion encoding on data to be coded based on a code generator instruction received through a serial port, and then outputs the result to the reactive pulse drive circuit via a resistor, so that the reactive pulse drive circuit sends the data to a power supply line and transmits the data information to the power grid via an instantaneous current. The circuit structure of the present invention is simple, safe, and compact.

This invention relates to the field of motor control technology, specifically to a control method and apparatus for preventing backflow of pump-generated voltage based on a synchronous BUCK circuit. The method includes: executing switching control of the synchronous BUCK circuit according to a set frequency and duty cycle of the switching transistors, and recording the values ​​of Vo and Vin once per switching control cycle; upon reaching a predetermined judgment period, reading the Vo and Vin values ​​recorded in each switching control cycle within the judgment period; determining whether a pump-generated voltage has occurred based on the changes in the Vo and Vin values ​​recorded in each switching control cycle within the judgment period; and if so, turning off both switching transistors Q1 and Q2. By acquiring the values ​​of Vin and Vo, the state of the synchronous BUCK circuit is determined using these two voltage values. When it is determined that a pump-generated voltage has occurred, both switching transistors Q1 and Q2 are turned off. That is, by controlling the switching state and duty cycle of Q1 and Q2, backflow of pump-generated voltage energy is prevented.

The application discloses a FPGA global reset synchronization circuit, a chip, a verification simulation system and a method. The FPGA global reset synchronization circuit comprises a clock signal channel and a reset signal channel. The clock signal channel comprises a filter and a frequency multiplier. The filter is used for filtering an input first clock signal, the frequency multiplier is used for frequency multiplication after the filtering, a second clock signal is generated, the frequency of the second clock signal is an integer multiple of the first clock signal, and the second clock signal is output to provide a clock signal for user logic in the FPGA chip. The reset signal channel comprises a cross-clock-domain transmission circuit. The cross-clock-domain transmission circuit is used for outputting an input reset signal after the cross-clock-domain transmission to provide a global reset signal for the user logic in the FPGA chip. The application does not depend on the distance of the FPGA and the length of the signal line, and is especially suitable for clock reset synchronization of a large number of FPGAs when the FPGAs are used for chip verification and simulation.

The present invention provides a synchronization circuit device and a method for generating a synchronization signal. The synchronization circuit device includes: a carrier frequency offset blind estimation circuit, which is configured to receive a multi-bit frequency domain data stream and a synchronization signal fed back from an address synchronization circuit, and output a first carrier frequency offset estimation value; a carrier frequency offset compensation circuit, which is configured to perform carrier frequency offset compensation on the received multi-bit frequency domain data stream according to the first carrier frequency offset estimation value, and output a frequency domain data stream without carrier frequency offset as a single bit; and an address synchronization circuit, which is configured to receive the frequency domain data stream without carrier frequency offset as a single bit, and output a synchronization signal.

The application discloses a Lamoeba chip architecture and a runtime reconstruction mechanism method based on an asynchronous mechanism, which combines an asynchronous reconfigurable Lamoeba chip and a reconstruction algorithm mechanism with time as a cost. The asynchronous mechanism provides a hardware basis for reconfigurable computing. The Lamoeba chip adopts a communication architecture of an on-chip mesh NoC to perform data transmission and communication on a network. The network adopts a 2D-mesh topology structure. Different types of computing modules are mounted in the network. In combination with a microprocessor in a single-chip microcomputer, software programming and routing address configuration are performed to complete the calculation of corresponding algorithms. The reconstruction algorithm calculates the data operation time, routing time and arbitration time of different paths in the network to find the shortest time allocation mode for algorithm mapping and change the deployment of the computing modules in the algorithm to the hardware resources. The application has the advantages of flexible general computing, high special computing, low power consumption without a clock and the ability to avoid various problems caused by the clock in the synchronous circuit.

The present application provides a wake-up circuit and a processing circuit. The wake-up circuit is used to generate a wake-up signal and an interrupt signal, and includes a detection circuit, a first logic circuit, a synchronization circuit, a flip-flop and a second logic circuit. When a wake-up event occurs and a first set signal is enabled, the detection circuit enables a detection signal. When the detection signal and a low power signal are enabled, the first logic circuit enables the wake-up signal. The synchronization circuit generates a synchronization signal according to the detection signal. An edge of the synchronization signal is aligned with an edge of an operation clock. When the synchronization signal is enabled, the flip-flop enables an output signal. When the output signal and a second set signal are enabled, the second logic circuit enables the interrupt signal.

This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastable states cannot be simulated in EMU simulation verification environments before chip design. This application adds a metastable state simulation circuit after the trigger synchronization circuit constructed based on a multi-level trigger cascade mode. The metastable state simulation circuit simulates cross-clock domain metastable data output scenarios. The technical solution provided in this application complements the CDC simulation method in the DV design verification environment, effectively identifying potential problems in the design under test under CDC scenarios in the early stages of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the chip development process.

The invention relates to the technical field of integrated circuits, and discloses a high-speed clock delay controller, system and control method.The controller is characterized in that a low-frequency pulse generation circuit receives a high-speed main clock signal and converts the high-speed main clock signal into low-frequency pulse signals with the number corresponding to the preset delay period number; the clock synchronization circuit is used for synchronizing the low-frequency pulse signal with a high-speed main clock signal and outputting a synchronization pulse signal; the clock pause control circuit is used for shortening the pulse width of the synchronous pulse signal to a high-speed main clock period and then negating to generate a clock pause control signal; the high-speed clock driving circuit is used for controlling pause or output of the high-speed main clock signal according to the clock pause control signal, integer period delay of the high-speed main clock signal is achieved, and a high-speed main clock delay signal is obtained. According to the invention, accurate and additional noise-free adjustable delay can be provided for a high-speed clock signal.

A heterogeneous computing system performs data synchronization. The heterogeneous computing system includes a system memory, a cluster, and a processing unit outside the cluster. The cluster includes a sync circuit, inner processors, and a snoop filter. The sync circuit is operative to receive a sync command indicating a sync address range. The sync command is issued by one of the processing unit and the inner processors. The sync circuit further determines whether addresses recorded in the snoop filter fall within the sync address range. In response to a determination that a recorded address falls within the sync address range, the sync circuit notifies a target one of the inner processors that owns a cache line having the recorded address to take a sync action on the cache line.

The application provides a clock synchronization circuit, a chip and an electronic device, the clock synchronization circuit comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider; a first end of the first phase-locked loop circuit is connected with an input end; second ends of the first phase-locked loop circuit are respectively connected with a first end of the second phase-locked loop circuit and a first output end; a second end of the second phase-locked loop circuit is connected with a first end of the first frequency divider; and a second end of the first frequency divider is connected with a second output end. The clock synchronization circuit provided by the application comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider, can realize simultaneous output of standard Ethernet and wireless communication system homologous clock, and simplifies a clock scheme and reduces device cost.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

A circuit includes a switching signal generator and synchronization circuitry configured to determine a first time of a switching period based on a switching signal. The circuit further includes a comparison signal generator configured to generate a comparison signal with a first constant rate of change after the first time. The synchronization circuitry is further configured to determine a second time of the switching period based on when current at the inductive element changes from a positive current to a negative current. The comparison signal generator is further configured to generate the comparison signal with a second constant rate of change after the second time. The circuit further includes a threshold detector configured to compare a value of the comparison signal at the end of a target switching period with a threshold value.

The invention discloses a synchronous circuit applied to high-speed DAC (Digital-to-Analog Converter) data reception, which simultaneously uses a D trigger array formed by D triggers for sampling a rising edge and a falling edge, so that the external data rate is twice of that of a data input clock, and data at the rising edge and the falling edge of the data input clock are changed. The digital control / locking detection module is used for fixing the delay generated by the digital control delay module according to the corresponding trigger signal so as to complete the locking of the digital control loop; the elastic FIFO array is used for outputting the DAC data signal synchronized with the work clock FDAC, synchronization of the phase of the DAC data signal and the work clock FDAC is achieved, the problem that the phase relation between the work clock and input data is uncertain when a chip is powered on each time is solved, and therefore it is guaranteed that the input data and the work clock of a DAC core module are the same in phase, and the performance of the high-speed DAC is improved.