111 results about "Synchronous circuit" patented technology

A system for the automated collection of test results and conformity reporting in IT service management environments. The system includes: a structural enclosure configured to enclose a variety of electronic components, wherein the structural enclosure is equipped with power supply circuits, thermal control units and electromagnetic shielding; at least one processor located within the structural housing and electrically connected to a communication controller, wherein the processor is configured to execute instructions for interface with distributed data sources for information technology service management; The communications controller includes a variety of encrypted data transmission circuits configured to securely extract evidentiary data from service management logs, access control records, configuration baselines, and monitoring databases; a compliance controller electrically connected to the processor, wherein the compliance controller comprises a rule-based processing unit configured to identify evidence artifacts required by a compliance framework, and a verification processing unit configured to validate the integrity, completeness, and format of the extracted artifacts; a time synchronization circuit electrically coupled to the compliance controller, wherein the time synchronization circuit is configured to assign tamper-proof cryptographic timestamps to each evidence artifact at the capture location; a memory management circuit electrically connected to the non-volatile memory, wherein the memory management circuit is configured to organize the validated evidence artifacts in a hierarchical and indexed data structure, with indexing being performed according to service identifiers and conformance categories; a hardware security controller located within the structural enclosure, wherein the hardware security controller includes a secure enclave configured to store cryptographic keys and to digitally sign evidence artifacts and compliance reports prior to their transmission; and an output interface that is electrically connected to the compliance controller and the hardware security controller, wherein the output interface is configured to generate compliance reports in both machine-readable structured formats and human-readable formatted documents and to transmit these reports to authorized audit systems.

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and a jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine that converts this data into frequency-domain data. The spectrum hardware engine has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to a computing device to estimate phase noise.

The invention provides a software operation synchronization method and system based on a dual-chip architecture, and abandons a traditional mode depending on a UART / SPI / CAN communication protocol or an additional synchronization circuit. Firstly, a unique PWM duty ratio mapping relation with any difference not smaller than 5% is preset for the initial state, the system self-checking state, the OTA upgrading state, the running state, the fault state, the dormancy preparation state and other running states of the double-chip system, and then a chip A and a chip B continuously output PWM signals matched with the current states of the chip A and the chip B through common GPIO pins in a push-pull output mode. Meanwhile, PWM signals of GPIO pins of the opposite side are collected in real time in a bidirectional mode through respective hardware capture units, the duty ratio is analyzed to obtain the state of the opposite side, response operation is executed according to preset logic, synchronization failures caused by communication delay and data frame error codes of a traditional software protocol are effectively avoided, the system stability is guaranteed, meanwhile, a complex protocol stack does not need to be designed, and the cost is reduced. The CPU load rate is reduced, an additional synchronous circuit is omitted, the chip area and power consumption are reduced, and the hardware cost is reduced.

This application relates to the field of automatic feeding technology, and provides a distributed control method and system for feeding motor rotor laminations. The method includes: setting up programmable logic controllers (PLCs) at multiple feeding nodes, each controller connected to a synchronous Buck topology circuit; reading and parsing the feeding task script, identifying the collaborative feeding nodes and their task control precision from multiple feeding nodes; sending a precision synchronization command to a coordination terminal based on the task control precision to obtain a corresponding fluctuation limiting signal; and the coordination terminal performing distributed collaborative control on the output of the synchronous Buck circuit connected to the collaborative feeding nodes based on the fluctuation limiting signal to complete the execution of the feeding task script. This application solves the technical problems of inconsistent actions and large precision fluctuations caused by independent control of each feeding node in the traditional motor rotor lamination feeding process, achieving the technical effect of highly consistent actions of each feeding node and controllable feeding precision through distributed synchronous control and high-precision DC bus clamping.

The invention provides a multi-frequency TDD (Time Division Duplex) analog synchronization circuit and method, which can solve the problems of high cost, poor precision and low sensitivity of a TDD synchronization scheme in the prior art, and comprises a radio frequency selection path used for selecting and outputting a single-frequency-band radio frequency signal from input radio frequency signals according to a control signal; the detector is connected with the radio frequency selection path and used for performing envelope detection on the target radio frequency signal, and the detector is provided with an inverted output end VDN; the processor comprises an ADC input end, and the ADC input end is connected with the inverted output end VDN of the detector and used for collecting the detected voltage signals; the processor is also connected with the radio frequency selection path and is used for sending a control signal to control the radio frequency selection path to gate a corresponding frequency band channel; the processor identifies the frame header position of the radio frequency signal according to the voltage signal collected by the ADC input end, and outputs an uplink switching signal and a downlink switching signal.

A device includes: a receiver path; and a demodulator having an input coupled to an output of the receiver path; a first STF synchronization circuit coupled to the output of the receiver path and configure to: detect a first synchronization sequence of a first packet in a first subcarrier, and in response to detecting the first synchronization sequence, cause the demodulator to process a rest of the first packet, where the first packet is received by the receiver path using a single subcarrier at a time; and a second STF synchronization circuit coupled to the output of the receiver path and configure to: detect a second synchronization sequence of a second packet in a second subcarrier, and in response to detecting the second synchronization sequence, cause the demodulator to process a rest of the second packet, where the second packet is received using a single subcarrier at a time.

The application discloses a circuit for preventing upper and lower pipes of a dcdc from conducting simultaneously, and relates to the technical field of synchronous Buck circuits, which comprises a control and regulation unit, wherein the control and regulation unit outputs a driving signal to a power switch unit; the driving signal of the control and regulation unit comprises a high-side driving signal (Hdrv), a low-side driving signal (Ldrv), a substrate selection control module, a substrate selection module and a VDD2 generation module; the control and regulation unit outputs a PG signal to the substrate selection control module; the output end of the substrate selection module is electrically connected with the input end of the substrate selection module; the output end of the VDD2 generation module is electrically connected with the input end of the substrate selection module; and the output end of the substrate selection module is electrically connected with the substrate (Psub) of the power switch tube (PM1). The substrate potential of the power switch tube (PM1) is dynamically switched through the substrate selection module, the upper and lower pipes are prevented from conducting simultaneously from the physical layer, the power device is effectively protected, and the circuit stability is improved.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The invention provides a clock synchronization circuit and system which can be applied to the technical field of signal transmission. The clock synchronization circuit comprises: a first node comprising: a first port unit configured to send downlink data to a second node via a downlink according to a first sending reference clock obtained based on an input reference clock, and obtain a first recovery clock according to uplink data returned by the second node via an uplink, performing phase adjustment on the first sending reference clock according to the first phase adjustment step length number; a second port unit configured to output a first measurement reference clock according to an input reference clock; the first phase measurement unit is configured to sample an input reference clock and a first recovery clock according to a first measurement reference clock and output a first phase adjustment step length number; and the second node is configured to obtain the second recovery clock according to the downlink data received by the downlink, and send the uplink data through the uplink according to the second sending reference clock.

A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.

This invention relates to the field of motor control technology, specifically to a control method and apparatus for preventing backflow of pump-generated voltage based on a synchronous BUCK circuit. The method includes: executing switching control of the synchronous BUCK circuit according to a set frequency and duty cycle of the switching transistors, and recording the values ​​of Vo and Vin once per switching control cycle; upon reaching a predetermined judgment period, reading the Vo and Vin values ​​recorded in each switching control cycle within the judgment period; determining whether a pump-generated voltage has occurred based on the changes in the Vo and Vin values ​​recorded in each switching control cycle within the judgment period; and if so, turning off both switching transistors Q1 and Q2. By acquiring the values ​​of Vin and Vo, the state of the synchronous BUCK circuit is determined using these two voltage values. When it is determined that a pump-generated voltage has occurred, both switching transistors Q1 and Q2 are turned off. That is, by controlling the switching state and duty cycle of Q1 and Q2, backflow of pump-generated voltage energy is prevented.

The application discloses a FPGA global reset synchronization circuit, a chip, a verification simulation system and a method. The FPGA global reset synchronization circuit comprises a clock signal channel and a reset signal channel. The clock signal channel comprises a filter and a frequency multiplier. The filter is used for filtering an input first clock signal, the frequency multiplier is used for frequency multiplication after the filtering, a second clock signal is generated, the frequency of the second clock signal is an integer multiple of the first clock signal, and the second clock signal is output to provide a clock signal for user logic in the FPGA chip. The reset signal channel comprises a cross-clock-domain transmission circuit. The cross-clock-domain transmission circuit is used for outputting an input reset signal after the cross-clock-domain transmission to provide a global reset signal for the user logic in the FPGA chip. The application does not depend on the distance of the FPGA and the length of the signal line, and is especially suitable for clock reset synchronization of a large number of FPGAs when the FPGAs are used for chip verification and simulation.

The present application provides a wake-up circuit and a processing circuit. The wake-up circuit is used to generate a wake-up signal and an interrupt signal, and includes a detection circuit, a first logic circuit, a synchronization circuit, a flip-flop and a second logic circuit. When a wake-up event occurs and a first set signal is enabled, the detection circuit enables a detection signal. When the detection signal and a low power signal are enabled, the first logic circuit enables the wake-up signal. The synchronization circuit generates a synchronization signal according to the detection signal. An edge of the synchronization signal is aligned with an edge of an operation clock. When the synchronization signal is enabled, the flip-flop enables an output signal. When the output signal and a second set signal are enabled, the second logic circuit enables the interrupt signal.

This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastable states cannot be simulated in EMU simulation verification environments before chip design. This application adds a metastable state simulation circuit after the trigger synchronization circuit constructed based on a multi-level trigger cascade mode. The metastable state simulation circuit simulates cross-clock domain metastable data output scenarios. The technical solution provided in this application complements the CDC simulation method in the DV design verification environment, effectively identifying potential problems in the design under test under CDC scenarios in the early stages of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the chip development process.

The invention relates to the technical field of integrated circuits, and discloses a high-speed clock delay controller, system and control method.The controller is characterized in that a low-frequency pulse generation circuit receives a high-speed main clock signal and converts the high-speed main clock signal into low-frequency pulse signals with the number corresponding to the preset delay period number; the clock synchronization circuit is used for synchronizing the low-frequency pulse signal with a high-speed main clock signal and outputting a synchronization pulse signal; the clock pause control circuit is used for shortening the pulse width of the synchronous pulse signal to a high-speed main clock period and then negating to generate a clock pause control signal; the high-speed clock driving circuit is used for controlling pause or output of the high-speed main clock signal according to the clock pause control signal, integer period delay of the high-speed main clock signal is achieved, and a high-speed main clock delay signal is obtained. According to the invention, accurate and additional noise-free adjustable delay can be provided for a high-speed clock signal.

The application provides a clock synchronization circuit, a chip and an electronic device, the clock synchronization circuit comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider; a first end of the first phase-locked loop circuit is connected with an input end; second ends of the first phase-locked loop circuit are respectively connected with a first end of the second phase-locked loop circuit and a first output end; a second end of the second phase-locked loop circuit is connected with a first end of the first frequency divider; and a second end of the first frequency divider is connected with a second output end. The clock synchronization circuit provided by the application comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider, can realize simultaneous output of standard Ethernet and wireless communication system homologous clock, and simplifies a clock scheme and reduces device cost.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

The invention discloses a synchronous circuit applied to high-speed DAC (Digital-to-Analog Converter) data reception, which simultaneously uses a D trigger array formed by D triggers for sampling a rising edge and a falling edge, so that the external data rate is twice of that of a data input clock, and data at the rising edge and the falling edge of the data input clock are changed. The digital control / locking detection module is used for fixing the delay generated by the digital control delay module according to the corresponding trigger signal so as to complete the locking of the digital control loop; the elastic FIFO array is used for outputting the DAC data signal synchronized with the work clock FDAC, synchronization of the phase of the DAC data signal and the work clock FDAC is achieved, the problem that the phase relation between the work clock and input data is uncertain when a chip is powered on each time is solved, and therefore it is guaranteed that the input data and the work clock of a DAC core module are the same in phase, and the performance of the high-speed DAC is improved.

This invention discloses a multi-oscillator true random number generator based on independent auxiliary TRNG control. It is characterized by comprising a main TRNG module and an auxiliary TRNG module. The main TRNG module provides a true random number sequence TR via an internal bus. The main TRNG module includes a random signal generation module, an asynchronous sampling circuit, and a post-processing circuit. The random signal generation module includes N ring oscillators RO_i, each RO_i having an independent enable terminal EN_i, i=0~N-1. The auxiliary TRNG module is a complete TRNG, outputting an M-bit auxiliary random number sequence F[M-1:0], where M>N≥2. The lower N bits of the auxiliary TRNG module's output F[N-1:0] are directly connected one-to-one to the enable terminal EN_i of the corresponding RO_i in the main TRNG module without any synchronization circuit, achieving EN_i=F[i], where F[i] corresponds to the i-th bit in F[N-1:0]. This invention can improve the entropy quality and attack resistance of the overall system.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain, a test data in (TDI) line, a test data out (TDO) line connected to the output terminal, a test access port (TAP) controller to control an operation of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal and a test mode select (TMS) signal, a power management unit to control power gating for the blocks, and a clock management unit to control a clock signal provided to the blocks. The TAP controller includes a first register that stores a first data for generating a first control signal controlling the power and clock management units, which control the operation of the blocks based on the first control signal.

This invention discloses an asynchronous sparse matrix outer product multiplier based on an event-driven circuit design. The multiplier employs a merging strategy that explicitly associates data with storage unit addresses, mapping matrix data address indices to corresponding addresses in the storage modules. Identical indices indicate identical storage locations, necessitating a merging operation. This strategy ensures the determinism of the data merging process and avoids complex sorting operations. Furthermore, the event-driven, clockless circuit used in this multiplier effectively mitigates some problems associated with synchronous circuits due to the absence of a clock and the use of an asynchronous controller to control data transmission. It also features low power consumption, high adaptability, and a certain degree of electromagnetic interference resistance, making it suitable for processing scenarios requiring ultra-low power consumption.

The application provides a clock synchronization circuit, a control method, a printed circuit board and communication equipment. The clock synchronization circuit comprises a first frequency divider and an external reference signal processing module, a phase detector, a voltage control conversion module and a clock generator connected in sequence. The voltage control conversion module comprises a digital-to-analog converter, a loop filter module and a first switch module. The phase detection output end of the phase detector is connected to the loop filter module. The digital-to-analog converter and the loop filter module are both connected to the first switch module. The output end of the first switch module is connected to the clock generator. The clock generator is connected to the phase detection feedback end of the phase detector through the first frequency divider. The signal from the digital-to-analog converter or the signal from the external reference signal processing module can be used as a reference clock signal by switching the first switch module. The internal and external reference clock can be switched by using fewer clock generator devices, thereby reducing the area of the printed circuit board and saving costs.

The application discloses an eye diagram data synchronization circuit and method and a serial-parallel converter receiving end, and belongs to the technical field of high-speed serial data communication; the circuit comprises: a calibration signal generation module for generating a phase calibration signal according to a phase difference between a data sampling signal and an offset sampling signal; two registers for respectively outputting the offset sampling signal and pre / post offset sampling signals; wherein the pre / post offset sampling signals are obtained by outputting the offset sampling signal in advance / delaying half a bit period; and a selection output module for selecting the offset sampling signal or the pre / post offset sampling signals as a synchronized offset sampling signal output according to the phase calibration signal, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period. The application has wide application range, high synchronization precision and good dynamic performance.

The application discloses a frequency division synchronous circuit applied to a multi-channel analog-digital converter, which is composed of three main modules of a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit. The multi-channel analog-digital converter needs a reasonably designed clock system to provide a timing basis for the cooperative work of each module, but the existing clock system has problems of large jitter, fuzzy state and low efficiency, and the multi-channel analog-digital converter based on the clock system is difficult to meet the needs of the fast developing communication and detection array system. The application is an improved clock system, which reduces the sampling clock jitter through an edge reconstruction technology, thereby improving the sampling noise and improving the conversion precision; the phase ambiguity of the frequency division is eliminated through a synchronous strategy, which is beneficial to data processing and correction, and the clock system can be reset to a specific initial state under control, which is beneficial to array application; through a bus type clock distribution strategy, the number of clock transmission lines is reduced, and the circuit operation efficiency is improved.

Embodiments of this disclosure provide an asynchronous signal transmission circuit, method, chip, and electronic device. The asynchronous signal transmission circuit includes a synchronization circuit, a comparison circuit, and a storage circuit. The synchronization circuit is configured to sample asynchronous input data using at least two synchronizers based on a target clock signal and output first sampled data. The target clock signal is the clock signal of the target circuit. The comparison circuit is configured to compare the first sampled data with second sampled data delayed from the first sampled data, and output a comparison result and second sampled data to the storage circuit. The storage circuit is configured to store the output data and determine whether to update the stored output data with the second sampled data based on the comparison result. This solves the problems of current asynchronous signal transmission methods, such as sampling incorrect intermediate values ​​or being unable to use circuits that are difficult to provide handshake signals.

In an example, a system includes one or more clock channels on a clock chip, each clock channel configured to provide a clock signal. The system also includes a signal line coupled to the one or more clock channels, the signal line configured to send clock signals to and receive clock signals from each clock channel. The system includes a controller configured to select a first clock signal from a first clock channel to drive the signal line. The system also includes divider timing synchronization circuitry in a second clock channel configured to align a second clock signal from the second clock channel with the first clock signal.

The present application relates to the field of communication and anti-interference technology, in particular to a kind of ultra-wideband frequency hopping circuit and fast synchronization method, using mirror frequency suppression receiving architecture to the wideband microwave frequency hopping signal is obtained to the intermediate frequency signal, and using double-channel AD differential sampling and rising edge detection and threshold detection combined mode, accurate identification and tracking to envelope detection signal phase are realized, and then the local oscillator frequency hopping signal of receiver is realized fast follow jump, solve the problems such as complex, poor acquisition accuracy and long time of synchronization process in the traditional frequency hopping synchronization process.Simultaneously with the present application, hardware resources are saved, and the time of synchronization establishment is shortened.

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit dies are synchronized using a synchronization circuit on one of the dies. The synchronization circuit receives a count phase and adjusts a clock signal, and in some embodiments, counts to synchronize the processors. In one embodiment, the synchronization circuit includes a phase detector that receives a particular bit of the count signal as the count phase.

In a synchronization circuit, a detection control module outputs a first control signal, a detection signal and a second control signal. In a case where the detection signal is received, the main control chip module generates a master clock signal and a frame synchronization signal. In a case where the first control signal is received, the master clock signal transmission module transmits the master clock signal to the output interface module, and the frame synchronization signal transmission module transmits the frame synchronization signal to the output interface module. In a case where the second control signal is received, the master clock signal transmission module transmits the master clock signal to the output interface module, the frame synchronization signal transmission module transmits the frame synchronization signal to the output interface module, and a camera module acquires a picture based on the frame synchronization signal and the master clock signal.