24 results about "Synchronous circuit" patented technology

The application discloses a circuit for preventing upper and lower pipes of a dcdc from conducting simultaneously, and relates to the technical field of synchronous Buck circuits, which comprises a control and regulation unit, wherein the control and regulation unit outputs a driving signal to a power switch unit; the driving signal of the control and regulation unit comprises a high-side driving signal (Hdrv), a low-side driving signal (Ldrv), a substrate selection control module, a substrate selection module and a VDD2 generation module; the control and regulation unit outputs a PG signal to the substrate selection control module; the output end of the substrate selection module is electrically connected with the input end of the substrate selection module; the output end of the VDD2 generation module is electrically connected with the input end of the substrate selection module; and the output end of the substrate selection module is electrically connected with the substrate (Psub) of the power switch tube (PM1). The substrate potential of the power switch tube (PM1) is dynamically switched through the substrate selection module, the upper and lower pipes are prevented from conducting simultaneously from the physical layer, the power device is effectively protected, and the circuit stability is improved.

This invention relates to the field of motor control technology, specifically to a control method and apparatus for preventing backflow of pump-generated voltage based on a synchronous BUCK circuit. The method includes: executing switching control of the synchronous BUCK circuit according to a set frequency and duty cycle of the switching transistors, and recording the values ​​of Vo and Vin once per switching control cycle; upon reaching a predetermined judgment period, reading the Vo and Vin values ​​recorded in each switching control cycle within the judgment period; determining whether a pump-generated voltage has occurred based on the changes in the Vo and Vin values ​​recorded in each switching control cycle within the judgment period; and if so, turning off both switching transistors Q1 and Q2. By acquiring the values ​​of Vin and Vo, the state of the synchronous BUCK circuit is determined using these two voltage values. When it is determined that a pump-generated voltage has occurred, both switching transistors Q1 and Q2 are turned off. That is, by controlling the switching state and duty cycle of Q1 and Q2, backflow of pump-generated voltage energy is prevented.

This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastable states cannot be simulated in EMU simulation verification environments before chip design. This application adds a metastable state simulation circuit after the trigger synchronization circuit constructed based on a multi-level trigger cascade mode. The metastable state simulation circuit simulates cross-clock domain metastable data output scenarios. The technical solution provided in this application complements the CDC simulation method in the DV design verification environment, effectively identifying potential problems in the design under test under CDC scenarios in the early stages of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the chip development process.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

This invention discloses a multi-oscillator true random number generator based on independent auxiliary TRNG control. It is characterized by comprising a main TRNG module and an auxiliary TRNG module. The main TRNG module provides a true random number sequence TR via an internal bus. The main TRNG module includes a random signal generation module, an asynchronous sampling circuit, and a post-processing circuit. The random signal generation module includes N ring oscillators RO_i, each RO_i having an independent enable terminal EN_i, i=0~N-1. The auxiliary TRNG module is a complete TRNG, outputting an M-bit auxiliary random number sequence F[M-1:0], where M>N≥2. The lower N bits of the auxiliary TRNG module's output F[N-1:0] are directly connected one-to-one to the enable terminal EN_i of the corresponding RO_i in the main TRNG module without any synchronization circuit, achieving EN_i=F[i], where F[i] corresponds to the i-th bit in F[N-1:0]. This invention can improve the entropy quality and attack resistance of the overall system.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain, a test data in (TDI) line, a test data out (TDO) line connected to the output terminal, a test access port (TAP) controller to control an operation of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal and a test mode select (TMS) signal, a power management unit to control power gating for the blocks, and a clock management unit to control a clock signal provided to the blocks. The TAP controller includes a first register that stores a first data for generating a first control signal controlling the power and clock management units, which control the operation of the blocks based on the first control signal.

This invention discloses an asynchronous sparse matrix outer product multiplier based on an event-driven circuit design. The multiplier employs a merging strategy that explicitly associates data with storage unit addresses, mapping matrix data address indices to corresponding addresses in the storage modules. Identical indices indicate identical storage locations, necessitating a merging operation. This strategy ensures the determinism of the data merging process and avoids complex sorting operations. Furthermore, the event-driven, clockless circuit used in this multiplier effectively mitigates some problems associated with synchronous circuits due to the absence of a clock and the use of an asynchronous controller to control data transmission. It also features low power consumption, high adaptability, and a certain degree of electromagnetic interference resistance, making it suitable for processing scenarios requiring ultra-low power consumption.

Out-of-band synchronization between a power transmitter and one or more power receivers. A system comprise a power transmitter; a power receiver; a power cable connected between the power transmitter and the power receiver; and a synchronization cable connected between the power transmitter and the power receiver. The power transmitter is configured to transmit over a pair of lines in the power cable to the power receiver, and to perform a safety check to detect a fault with respect to the pair of lines. The power transmitter includes a transmitter synchronization circuit and the power receiver includes a receiver synchronization circuit in communication with the transmitter synchronization circuit of the power transmitter via the synchronization cable. The transmitter synchronization circuit is configured to generate a synchronization clock signal sent to the receiver synchronization circuit via the synchronization cable.

This utility model discloses a multi-system, multi-channel digital TR synchronization circuit, comprising a GPS / BD timing module, a system clock source, a multi-channel digital TR board, and a system lead generation device. The rubidium clock and second pulse of the GPS / BD timing module are respectively connected to the system clock source and the lead generation device. The sampling clock and lead clock of the system clock source, and the lead signal of the system lead generation device are respectively connected to each multi-channel digital TR board. The system lead clock of the system clock source is also connected to the lead generation device. This scheme uses the rubidium clock and second pulse of the GPS / BD timing module as a reference, and the accuracy of the lead clock determines the synchronization accuracy (e.g., a 20MHz lead clock synchronization error ≤50ns). Multi-system expansion can be achieved by adding timing modules without refactoring the hardware architecture. Its hardware and software integration reduces FPGA logic complexity, reduces hardware costs by relying on chip synchronization functions and equal-length wiring design, and ensures multi-channel synchronization stability through same-source clock allocation and equal-length signal design.

An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

The application relates to the field of integrated circuit technology and discloses a high-speed clock delay controller, a system and a control method, the controller comprising: a low-frequency pulse generation circuit receiving a high-speed main clock signal and converting the high-speed main clock signal into a low-frequency pulse signal with a number corresponding to a preset delay period number; a clock synchronization circuit used for synchronizing the low-frequency pulse signal with the high-speed main clock signal and outputting a synchronization pulse signal; a clock pause control circuit used for shortening the pulse width of the synchronization pulse signal to one high-speed main clock period, inverting the synchronization pulse signal, and generating a clock pause control signal; and a high-speed clock driving circuit used for controlling the pause or output of the high-speed main clock signal according to the clock pause control signal, realizing integer period delay of the high-speed main clock signal, and obtaining a high-speed main clock delay signal. The application can provide adjustable delay with precision and without additional noise for the high-speed clock signal.

The phase adjustment circuit 11 of this receiving signal quality monitor can sweep the phase of the sampling clock signal φe of the reference sampler within a phase range of several times the unit interval (UI) of the serial data signal. The first synchronization circuit 13A receives the first output signal of one sampler in the plurality of data reception samplers and the second output signal of the reference sampler SMe. The comparison logic circuit 15 receives the first and second output signals synchronously output from the first synchronization circuit 13A and outputs a comparison result related to the quality of the received signal.

A clock signal synchronization circuit and a multi-channel PHY, the circuit is applied to a multi-channel PHY, the multi-channel PHY comprises a PCS sublayer and a plurality of PMA sublayers, each PMA sublayer comprises at least one receiver, the receiver is used for receiving data transmitted by a channel corresponding to the receiver, and transmitting the received data to the PCS sublayer based on a local clock signal of the receiver; the circuit comprises: a detection module deployed in the PCS sublayer, and a calibration module deployed in the receiver, each calibration module is connected to the detection module; the detection module is used for sending a PCS local clock signal to the receiver after the receiver is powered on, so that the receiver takes the received PCS local clock signal as a reference clock signal; the calibration module is used for synchronizing the local clock signal of the receiver with the reference clock signal; and transmitting data to the PCS sublayer based on the synchronized local clock signal, so that the PCS sublayer samples the received data using the PCS local clock signal.

The application provides a synchronization circuit based on clock phase adjustment, comprising: a clock dividing circuit, which is used for generating a divided clock signal from an input system clock; a phase detection circuit, which is connected with the clock dividing circuit and is used for obtaining a phase offset value according to an input synchronization reference signal and the divided clock signal; a phase adjustment circuit, which is connected with the clock dividing circuit and the phase detection circuit and is used for adjusting the phase of the input divided clock signal according to the phase offset value to obtain a phase-adjusted divided clock signal; and a synchronizer circuit, which is connected with the phase adjustment circuit and is used for obtaining a local synchronization reference signal according to the phase-adjusted divided clock signal and the synchronization reference signal. The application can quickly adjust the clock phase in real time according to the phase relationship between the reference signal and the divided clock, does not lose the sampling edge of the clock, and can be applied to integrated circuits with high sampling accuracy requirements.

This invention discloses a reference phase input module and a phase synchronization device for partial discharge detection, belonging to the field of partial discharge detection technology. The reference phase input module for partial discharge detection of this invention, by setting up a mains voltage synchronization circuit, a voltage transformer synchronization circuit, a leakage current synchronization circuit, a bus current synchronization circuit, and an electromagnetic field signal synchronization circuit, can synchronize reference phase information for various types of power equipment and different components. It is highly effective and widely applicable, with a scientific and reasonable solution, thus accurately acquiring the reference phase signal. Furthermore, this invention allows for flexible selection of synchronization circuits for different power equipment and components, making it applicable to complex test sites and effectively reducing the impact of various interference signals on partial discharge phase acquisition, avoiding phase signal acquisition failure, and thus improving the accuracy of partial discharge detection results.

To provide a delay synchronization circuit that enables high-speed and stable operation. [Solution] The hybrid delay synchronization circuit includes a digital control loop that includes a digital phase comparator with a dead zone, and an analog control loop that includes an analog phase comparator that operates in the dead zone.

An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

A vibration rectification error correction device, a sensor module, and a method thereof, in order to generate data synchronized with a signal that is not synchronized with a reference signal, do not require a large circuit size synchronization circuit or a heavy load operation. The vibration rectification error correction device includes a reference signal generation circuit that outputs a reference signal; a frequency delta sigma modulation circuit that frequency delta sigma modulates the reference signal using a measured signal to generate a frequency delta sigma modulation signal; a first filter that is provided at a subsequent stage of the frequency delta sigma modulation circuit and that operates in synchronization with the measured signal; and a second filter that is provided at a subsequent stage of the first filter and that operates in synchronization with a first frequency signal that is not synchronized with the reference signal.

This invention discloses a multi-group parallel dimming synchronization circuit, including multiple dimming synchronization sub-circuits and a synchronization signal line. Each sub-circuit includes a dimming signal input terminal, a signal detection circuit, a signal comparison circuit, a feedback network, a synchronization switch circuit, and a dimming control circuit. The synchronization signal line connects to the synchronization switch circuits of each sub-circuit. When the signal comparison circuit of any sub-circuit outputs a high level, all sub-circuits are forced to turn off synchronously via the synchronization signal line; when all sub-circuits output a low level, they are turned on synchronously. This application solves the problems of high cost and poor protocol compatibility in existing synchronous dimming technologies, achieves precise synchronous control of multiple power supplies, and reduces system complexity and maintenance costs.

Embodiments of the present application provide a system on chip, a circuit control method and device, which can be applied to artificial intelligence and other scenarios. The system on chip includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is configured to generate a reset signal for each IP unit. The reset synchronization circuit is configured to synchronize the reset signal according to a clock signal of each IP unit, to obtain a synchronized reset signal. The synchronized reset signal is used to reset at least one circuit unit included in each IP unit. The reset control unit is further configured to generate a gating signal for each IP unit according to the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit. The design of the reset circuit can be effectively simplified, and the timing convergence of the reset signal can be ensured.

The utility model discloses a kind of graphic processing systems based on embedded dual-core ARM chip control, it is related to embedded graphic processing technical field, and the problem of low processing efficiency, poor real-time performance and signal processing complexity existing in current graphic processing system is solved.A kind of graphic processing systems based on embedded dual-core ARM chip control, containing embedded dual-core ARM chip circuit, figure input module, figure processing module, figure storage module, figure output module, data interaction module, alarm module and display module;The utility model is provided with dual-core ARM chip circuit, and main core is responsible for figure rendering, and coordination core is responsible for system control and real-time signal processing, in combination with FPGA hardware acceleration unit and high-speed parallel bus, through multi-source signal synchronous circuit and multiple input and output interfaces, support multi-source signal input and high-resolution output, meet the graphic processing demand under complex scene.

A system for predictive modeling of sustainability outcomes using economic time series indicators, wherein the system comprises: a data acquisition unit with a variety of input ports, signal conditioning circuits, and synchronization circuits configured to receive time-indexed economic data streams from external sources and align the received data streams based on a common time reference; a buffer storage unit operationally connected to the data acquisition unit and comprising sequential storage registers configured to store the time-aligned data in an ordered sequence corresponding to the time intervals;a preprocessing unit electrically connected to the buffer storage unit, the preprocessing unit comprising filtering, normalization, and interpolation circuits configured to remove noise, scale the data, and compensate for missing or irregular data points in the stored time-series data; a feature extraction unit coupled to the preprocessing unit comprising vector transformation circuits configured to generate temporal feature vectors from the preprocessed data, including trend components, periodic components, and correlation values;a predictive processing unit consisting of a plurality of interconnected arithmetic processing elements, weighted signal multipliers, accumulation registers and activation circuits arranged in layered connections, wherein the predictive processing unit is configured to receive the temporal feature vectors and generate predictive outputs corresponding to the sustainability results; a temporal dependency processing unit consisting of delay elements, shift registers and sequence alignment circuits configured to preserve historical data dependencies over multiple time intervals and provide temporally extended data to the predictive processing unit;a decision processing unit coupled with the prediction processing unit, comprising comparator circuits, threshold evaluation circuits, and classification circuits configured to categorize prediction outputs into predefined sustainability states; an output interface unit consisting of display drivers, communication transceivers, and memory controllers configured to display and transmit the categorized sustainability states to external systems or display devices;a control processor with clock generators, control signal distribution circuits and bus arbitration circuits, configured to coordinate the operation of the data acquisition unit, the preprocessing unit, the feature extraction unit, the predictive processing unit, the temporal dependency processing unit, the decision processing unit and the output interface unit via a system bus; and a power control unit consisting of voltage regulators, current control circuits and thermal sensor elements configured to ensure stable operation of the system under varying load conditions.

An adaptive signal conditioning and noise reduction system in a multi-channel electronics processing environment, comprising: a plurality of input terminals configured to receive electrical signals from corresponding channels; a programmable analog conditioning circuit connected to each of the plurality of input terminals, each programmable analog conditioning circuit comprising a variable-gain amplifier, a tunable filter network, and an impedance matching arrangement; a multi-channel analog-to-digital converter circuit configured to simultaneously digitize conditioned signals from the programmable analog conditioning circuits;a digital signal processing circuit electrically coupled to the multi-channel analog-to-digital conversion circuit, wherein the digital signal processing circuit comprises a plurality of parallel processing paths, each having a reconfigurable filter structure and coefficient memory; a cross-channel interaction circuit configured to compute cross-channel correlation parameters and generate compensation signals based on the computed cross-channel correlation parameters; an adaptive control circuit operationally coupled to the programmable analog conditioning circuits and the digital signal processing circuit, wherein the adaptive control circuit is configured to generate control signals for dynamically adjusting gain, filter bandwidth, and filter coefficients based on evaluated signal quality parameters;a memory circuit configured to store historical signal data and adjustment parameters; a time synchronization circuit configured to ensure phase-in-phase operation across multiple channels; and an output interface circuit configured to transmit conditioned and noise-suppressed signals to an external device.

A time to digital conversion circuit includes a pulse signal generator configured to generate a pulse signal in response to activation of a transition detection signal, a latch circuit configured to latch a multiphase clock signal in response to a trailing edge of the pulse signal, an upper time to digital converter (TDC) configured to latch, in response to activation of a timing signal, a code whose value changes at the same period as a period of the multiphase clock signal, and a synchronization circuit. The latch circuit forms a lower TDC. The synchronization circuit supplies a signal synchronized by receiving the transition detection signal at a timing decided in accordance with a signal generated by the lower TDC as the timing signal to the upper TDC.