8 results about "And logic unit" patented technology

A memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (LUNs) and are associated with corresponding LUN queue groups. Each LUN queue group may include LUN queues that are each associated with a respective intra-LUN priority level that indicates a priority of a LUN queue within a LUN queue group. The LUN queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a LUN queue across LUN queue groups. A quantity of intra-LUN priority levels may be greater than a quantity of execution priority levels. A LUN scheduler may be configured to select and transfer commands from LUN queue groups to the execution queue group based on intra-LUN priority levels. A command executor may be configured to execute commands from the execution queue group based on execution priority levels.

This invention discloses a method for remotely updating a ZYNQ unit's LVDS interface. The ZYNQ unit comprises an embedded ZYNQ unit and a logic unit. An LVDS receiving module is configured in the ZYNQ logic unit to match the LVDS communication protocol with the embedded LVDS computer upgrade system, enabling the ZYNQ chip to establish LVDS interface communication with the embedded LVDS computer upgrade system. After the ZYNQ chip powers on and operates normally, establishing LVDS interface communication with the embedded LVDS computer upgrade system, the embedded LVDS computer upgrade system sends the BIN file to be updated to the ZYNQ chip via the LVDS interface for erasure and rewriting. This invention employs a working firmware and recovery firmware design, and through multiple boot modes, solves the problem of ZYNQ failing to start normally after an unexpected power outage during the update process. It has advantages such as simple operation, high reliability, and no need to unpack the device. Even if the device experiences an unexpected power outage during the update process, the multiple boot methods ensure that the device can still operate normally after power-on and re-update the program. This invention is suitable for field test program updates, solving the problem of having to unpack the device for field test program upgrades, and the remote program update is stable and reliable.

This invention relates to the field of high-precision industrial printing technology and discloses a multi-printerhead synchronous printing system based on a distributed architecture, including a workstation, an FPGA processing board, and print head modules. This system separates non-real-time large-scale computing from real-time high-precision control through a distributed architecture. When increasing the number of print heads, only additional computing tasks need to be added to the workstation, and logic units and I / O interfaces are expanded on the FPGA. The workstation parses the image data of each print job, completes dynamic load segmentation, establishes a segmentation index table, and then packages the data and embeds timestamps, ensuring that the FPGA processing board has sufficient time to complete decompression and caching, and also ensuring precise start of the printing operation at the specified time point. The distributed parsing has strong scalability, and the FPGA processing board constructs a global synchronization mechanism to ensure precise alignment of data from different channels in the time dimension. Waveform queries are performed on data packets to generate personalized drive waveforms adapted to each piezoelectric print head, resulting in excellent multi-printer collaboration.

The application discloses a kind of standardization data block processing systems of supporting multi-source data format, it is related to data processing field, the system includes preprocessing and format uniformity module, intelligent pre-analysis and strategy selection module, mixed inference depth block engine, block result optimization and check module, structured data output module.The application supports the compatible processing of multi-source data format;Based on the dynamic division of chapter structure and logic unit of text content, ensure semantic association content, avoid cross-modal semantic fragmentation;Improve the universality of block strategy;Intelligent block of multi-source data is realized, significantly reduces the demand of manual intervention, improves processing speed and efficiency, especially suitable for large-scale document processing scene;It can be directly connected knowledge graph construction, intelligent retrieval and other downstream applications, significantly improve data utilization efficiency.

The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

A transmitter circuit is provided having an additional delay path. A first transmitter output signal is generated according to a rising edge and falling edge of its data input signal. A second transmitter output signal is generated by delaying the first transmitter output signal. The disclosed transmitter circuit includes a rising and falling converter for outputting a converted data input signal, a delay and logic unit for receiving the converted data input signal and generating a carrier signal, an AND gate receiving the converted data input signal and the carrier signal, and outputting the first transmitter output signal, and a delay circuit receiving the first transmitter output signal and outputting the second transmitter output signal. Robustness and common mode voltage stability can be enhanced. Due to a definite and limited number of pulses of the carrier signal, the invention also achieves to reduce power consumption and electromagnetic interferences effectively.

The application discloses a kind of object data processing method and device, storage medium and electronic equipment, involve computer field technical field, comprising: receiving data write request;In the case where write operation is completed based on object data, the data storage address and transition layer address allocated for object data are obtained, wherein the data storage address is used to indicate the writing position of object data, and the mapping relationship between the logical unit address of object data and transition layer address is determined;In the first mapping relationship set, the first mapping relationship between the logical unit address and transition layer address is added;In the second mapping relationship set, the second mapping relationship between transition layer address and data storage address is added, so that the mapping relationship between data storage address and logical unit address is effectively dissociated based on transition layer address, and then the problem of low efficiency of existing data operation is solved.