50 results about "And logic unit" patented technology

An adaptive IGBT active drive circuit is divided into two parts: a gate drive circuit, and a feedback circuit. The gate drive circuit includes a totem pole unit, and multi-level resistance switching is achieved by using a totem pole parallel structure. The feedback circuit includes a comparison unit, and a logic unit. The comparison unit includes divided resistors, sampling resistors, and a comparator. Internal currents, after passing through the sampling resistor, are compared with current comparison thresholds of complementary transistors to output a digital signal to participate in control of the totem pole. The logic unit is responsible for logically combining a PWM signal and a signal output by the comparison unit to obtain a driving signal of the totem pole.

The invention discloses an approximate floating point multiplier, a chip and computing equipment, an approximate mantissa multiplier of the approximate floating point multiplier comprises an AND logic unit and a compressor unit, and the AND logic unit is used for performing AND operation on two input operands bit by bit to generate a partial product array with the size of 11 rows and 21 columns; the compressor unit is used for compressing the 11th column to the 21st column by column to obtain a final approximate mantissa, the compressor unit comprises two novel approximate 4-2 compressors ignoring carry design, and the error rate of the approximate 4-2 compressors is within an acceptable range by utilizing mutual compensation inside the compressors. The invention aims to excavate and use the characteristics of floating point multiplication to further improve the energy efficiency of floating point multiplication, realize the optimization of the approximate floating point multiplier in the overhead aspects of precision, power consumption, area and the like, and solve the problems of relatively complex circuit and low compression efficiency of the traditional approximate 4-2 compressor.

The embodiment of the invention provides a testing method and device for testing the performance of a solid state disk, a storage medium and electronic equipment. The method comprises the steps that a specification parameter set matched with a nonvolatile storage module on the solid state disk is obtained, the specification parameter set comprises channel number parameters, core number parameters and logic unit number parameters, the channel number parameters are used for indicating the number of data channels used for data transmission on the nonvolatile storage module, and the core number parameters are used for indicating the number of data channels used for data transmission on the nonvolatile storage module; the core number parameter is used for indicating the number of chips receiving and executing commands, and the logic unit number parameter is used for indicating the number of logic units used for executing logic operations; determining test units for executing the target test operation in the nonvolatile storage module and the target number of the test units according to the specification parameter set; and obtaining a state identifier of the test resource from the test resource set, and determining to execute a target test operation on the test unit according to the state identifier.

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source / drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

The invention discloses a communication device, a communication control method, an electronic device, a medium and a program product, and relates to the technical field of communication, by adopting the technical scheme provided by the invention, a target physical layer device is directly connected to a first multiplexer instead of being directly connected to a complex programmable logic device serving as a control element, so that the communication efficiency is improved. Therefore, when a plurality of physical layer devices need to be managed, a large number of MDIO pins do not need to be arranged on the control element so as to support switching control of MDIO signals. Therefore, the technical problem of shortage of pin resources and logic unit resources faced by a complex programmable logic device can be solved, and the technical effects of remarkably reducing the system cost and facilitating commercial application of products are achieved.

The invention provides a test method and a test device for a chip, relates to the technical field of chips, and solves the problems of insufficient protection or excessive protection and the like of protection measures adopted by the chip. According to the specific scheme, based on the number of logic units of each functional module of the chip and the single-particle features of the logic units, the single-particle function interruption occurrence frequency of each functional module is obtained; and based on the logic relationship among the plurality of function modules and the single-particle function interruption occurrence frequency of each function module, obtaining the single-particle function interruption occurrence frequency of the chip. Wherein the logic unit uses at least one protection measure, and the single particle feature is a corresponding relation between linear energy transfer of a single particle incident to the logic unit and a cross section.

The invention discloses a quick-positioning storage pressure test method and a storage medium thereof.The method comprises the steps that a write-in command is received, a test data packet is obtained, and the test data packet is provided with an initial logic block address, a write-in block number, a logic unit and a check value; the control unit performs verification operation according to the initial logic block address and the verification value in combination with a preset verification level and the verification level determined by the logic unit to obtain a verification result; when the verification result is successful, executing a write operation according to the initial logic block address and the write block number; and when the verification result is failure, storing a state log of the write-in operation, stopping executing the write-in operation, and outputting positioning information according to the logic unit, the verification result and the state log. Through the verification operation combining the initial logic block address and the verification value, data verification can be rapidly carried out, rapid positioning can be carried out under the condition of data errors and abnormities, and the accuracy and the test efficiency of the storage pressure test are improved.

The application discloses a data cache configuration method and a terminal. After generating a cache simulation memory block, the method creates a cache unit for data of an access object which can cache data according to an IO access request, fills data in the cache unit into the memory block, obtains processing logic of the cache unit, generates a logic unit, fills data in the logic unit into the memory block, and configures a cache index for the cache unit. In this way, hierarchical cache of module data such as the cache unit and the logic unit can be realized, and the access efficiency of the cache and the utilization rate of the cache resource can be effectively improved.

A memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (LUNs) and are associated with corresponding LUN queue groups. Each LUN queue group may include LUN queues that are each associated with a respective intra-LUN priority level that indicates a priority of a LUN queue within a LUN queue group. The LUN queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a LUN queue across LUN queue groups. A quantity of intra-LUN priority levels may be greater than a quantity of execution priority levels. A LUN scheduler may be configured to select and transfer commands from LUN queue groups to the execution queue group based on intra-LUN priority levels. A command executor may be configured to execute commands from the execution queue group based on execution priority levels.

The invention provides a UFS command priority scheduling processing method and device, electronic equipment and a medium, and relates to the technical field of scheduling processing, and the method comprises the steps: receiving a command from a host; classifying the commands according to priority types and logic unit types and mapping the commands to corresponding command queues based on command attributes obtained by analyzing UFS protocol information unit flag fields of the commands and device descriptor configuration information; determining a command execution sequence based on a preset dual priority rule; and taking out the commands from the command queue based on the command execution sequence and submitting the commands to the flash translation layer for processing. In the mode, the key command is prevented from being delayed to be executed for a long time, so that the overall performance and stability of the system are improved.

An apparatus includes a SRAM element having a clock input, an address input, an SRAM output, and a first and second address space A clock signal causes the SRAM element to output the logic value stored in a designated address space. A logic arrangement couples the SRAM output to a register A feedback path receives an output of the logic arrangement and provides a feedback clock and address signal. In an oscillation mode, a one is stored in the first address space and a zero in the second address space, and the feedback path provides the output of the logic cell arrangement to the address input and provides the feedback clock signal to trigger the output of the logic value stored in the currently designated address space, Thereby the feedback path, the SRAM element, and the logic cell arrangement form an oscillation loop.

The invention discloses a multi-voltage supply system for an OTP memory. The multi-voltage supply system comprises a band-gap reference unit, a first buffer, a second buffer, a protection voltage generation unit, a programming voltage generation unit, a read-write voltage generation unit and a logic unit, the protection voltage generation unit is used for generating protection voltage through a charge pump; the programming voltage generation unit is used for generating programming voltage through a charge pump; the read-write voltage generation unit is used for generating read-write voltage through voltage clamp. According to the invention, the defects of the traditional scheme in the aspects of voltage precision, power consumption and flexibility are effectively solved, the ripple of the output voltage is remarkably reduced, the high stability and temperature adaptability of the output voltage are ensured, and the integration level, power consumption optimization and dynamic regulation capability are remarkably improved.

The invention provides a voltage monitoring device, a voltage monitoring method and a related device, which have relatively low hardware complexity and can output a power supply in-place signal under the condition that the output voltage of a multi-level conversion chip is in a normal range. The device comprises a plurality of voltage comparison units and a line and logic unit, wherein the line and logic unit is connected with each voltage comparison unit; the plurality of voltage comparison units are in one-to-one correspondence with the plurality of voltage output units, the voltage comparison units are connected with the voltage output units corresponding to the voltage comparison units, and the voltage output units are used for outputting voltage; the voltage comparison unit is used for outputting an indication voltage signal when the target voltage output by the voltage output unit corresponding to the voltage comparison unit is greater than the reference voltage corresponding to the voltage output unit; and the line and logic unit is used for outputting a power supply in-place signal when each voltage comparison unit outputs the indicating voltage signal to the line and logic unit, and the power supply in-place signal represents that each voltage output unit can normally supply power.

The present invention provides a communication circuit structure for a robot and a robot, wherein the communication circuit structure includes a main control platform and a logic unit, the main control platform is connected to the logic unit via a universal serial bus, the logic unit is connected to multiple peripheral loads via a single-line serial port bus, and the logic unit converts the universal serial control signal of the main control platform into a single-line serial signal and outputs it to the multiple peripheral loads. The present invention can drive multiple peripheral loads while saving the number of interface pins of the main control platform, and can also improve the driving ability of the signal used to control the peripheral load.

A semiconductor device includes a memory cell connected to a signal line, a first voltage line for receiving a power supply voltage, and a second voltage line for receiving an electrical ground voltage, a logic unit configured to provide a logic function to the memory cell, a transition region, and an interconnect structure. A transition region extends from a first boundary of the memory cell to a second boundary of the logic cell, and an interconnect structure is over the memory cell and the logic cell. The interconnection structure comprises a signal line, a first voltage line and a second voltage line which are located on the same metal line layer of the interconnection structure. A signal line extends from within the second boundary of the logic cell into the first boundary of the memory cell. The transition region includes one or more functional transistors electrically coupled to the memory cell.

The present invention relates to an ultrasonic sensor unit comprising a first ultrasonic element and a logic unit, wherein the first ultrasonic element is configured to emit and / or receive at least one ultrasonic wave, wherein the logic unit is configured to generate an echo signal and a trace signal based on the at least one emitted and / or received ultrasonic wave, wherein the logic unit is configured to predict at least one further ultrasonic wave and one further echo signal based on the echo signal and the trace signal using a Kalman filter, and wherein the logic unit is configured to assign the further ultrasonic wave, the further echo signal and / or the further trace signal to the emitted ultrasonic wave, the echo signal and / or the trace signal using a Kuhn-Munkres algorithm.

The present invention relates to the technical field of multi-agent system cluster control, and specifically provides a distributed multi-agent cluster task collaborative management system based on a hierarchical encapsulation mechanism, which is intended to solve the behavior pattern design, task management and function planning problems of large-scale heterogeneous multi-agent clusters. The system consists of a task scheduling module, a data management module, a task construction module, and a task collaboration module; the task and function system is constructed through four levels of program plan (P), task chain (C), task (M), and task unit (F); and the tree topology structure and the graphic topology structure are used at the same time to organize the task function and scheduling logic at different task construction levels; and the autonomous scheduling and self-organization collaboration of the cluster function are realized through the bottom task unit and logic unit module. The scheme proposed by the present invention realizes the encapsulation of cluster functions at different levels, which is conducive to the reuse, combination and large-scale expansion of cluster functions, allowing people in the loop to control the cluster in real time, and has intuitiveness, autonomy, operability, scalability and ease of use.

The invention relates to an interlocking board card test platform. The interlocking board card test platform comprises a computer, a power supply board, a mother board and a logic machine cage, the logic machine cage is internally provided with a mother board, one side of the mother board is provided with a power supply board and a plurality of logic unit board cards, and one side, opposite to the logic unit board cards, of the mother board is provided with a rear plugboard; the power supply board supplies power to each logic unit board card through the mother board; the computer is in signal connection with the logic unit board card on the mother board, and test software is configured on the computer and used for testing the logic unit board card. Compared with the prior art, automation of the testing process is achieved, the testing efficiency and accuracy are greatly improved, and the dependency degree of manual operation is reduced.

The invention relates to a regulating unit (10) for a battery cell (100), comprising a pressure regulating unit (12), which is designed to adapt a pressure in the battery cell (100), and a logic unit (14), which is designed to detect a thermal breakdown of a battery cell (102) of the battery cell (100), the pressure regulating unit (12) being designed to adjust the pressure in the battery cell (100), and the logic unit (14) being designed to detect the thermal breakdown of the battery cell (102) of the battery cell (100). When a thermal breakdown is detected, the pressure of the battery cell (100) is reduced.

This invention discloses a method for remotely updating a ZYNQ unit's LVDS interface. The ZYNQ unit comprises an embedded ZYNQ unit and a logic unit. An LVDS receiving module is configured in the ZYNQ logic unit to match the LVDS communication protocol with the embedded LVDS computer upgrade system, enabling the ZYNQ chip to establish LVDS interface communication with the embedded LVDS computer upgrade system. After the ZYNQ chip powers on and operates normally, establishing LVDS interface communication with the embedded LVDS computer upgrade system, the embedded LVDS computer upgrade system sends the BIN file to be updated to the ZYNQ chip via the LVDS interface for erasure and rewriting. This invention employs a working firmware and recovery firmware design, and through multiple boot modes, solves the problem of ZYNQ failing to start normally after an unexpected power outage during the update process. It has advantages such as simple operation, high reliability, and no need to unpack the device. Even if the device experiences an unexpected power outage during the update process, the multiple boot methods ensure that the device can still operate normally after power-on and re-update the program. This invention is suitable for field test program updates, solving the problem of having to unpack the device for field test program upgrades, and the remote program update is stable and reliable.

The application discloses an interface generation method and system for mapping data by using a visual interaction panel, and belongs to the technical field of dynamic interface rendering. The method comprises the following steps: acquiring a multi-source data stream, extracting static and dynamic behavior characteristics, and generating feature anchor points; constructing a dynamic logic topology comprising components, links and logic units on the interaction panel; translating business association into layout instructions and fusing to generate a collaborative constraint network; inputting real-time data stream for rendering to generate an interface; and collecting feedback to collaboratively optimize logic parameters and layout weights. The application adopts a shadow deduction initialization and closed-loop feedback adjustment mechanism, can realize deep decoupling and adaptive alignment of data logic and interface layout, and improves the accuracy, robustness and interactive configuration efficiency under large-scale heterogeneous data of interface generation.

This invention relates to the field of high-precision industrial printing technology and discloses a multi-printerhead synchronous printing system based on a distributed architecture, including a workstation, an FPGA processing board, and print head modules. This system separates non-real-time large-scale computing from real-time high-precision control through a distributed architecture. When increasing the number of print heads, only additional computing tasks need to be added to the workstation, and logic units and I / O interfaces are expanded on the FPGA. The workstation parses the image data of each print job, completes dynamic load segmentation, establishes a segmentation index table, and then packages the data and embeds timestamps, ensuring that the FPGA processing board has sufficient time to complete decompression and caching, and also ensuring precise start of the printing operation at the specified time point. The distributed parsing has strong scalability, and the FPGA processing board constructs a global synchronization mechanism to ensure precise alignment of data from different channels in the time dimension. Waveform queries are performed on data packets to generate personalized drive waveforms adapted to each piezoelectric print head, resulting in excellent multi-printer collaboration.

This disclosure provides a miniature LED pixel driving circuit, which includes a logic operation module and a pixel driving module. The logic operation module receives an N-bit image data signal, where N is a positive integer. The logic operation module includes a conversion unit, an AND logic unit connected to the conversion unit, and a NOR logic unit connected to the AND logic unit. The conversion unit is used to convert the N-bit image data signal in a first format to a second format. The AND logic unit is used to convert the N-bit image data signal in the second format and a timing control signal to a third format. The NOR logic unit is used to convert the N-bit image data signal in the third format to a fourth format to control the on / off state of the pixel driving module.

The application discloses a kind of standardization data block processing systems of supporting multi-source data format, it is related to data processing field, the system includes preprocessing and format uniformity module, intelligent pre-analysis and strategy selection module, mixed inference depth block engine, block result optimization and check module, structured data output module.The application supports the compatible processing of multi-source data format;Based on the dynamic division of chapter structure and logic unit of text content, ensure semantic association content, avoid cross-modal semantic fragmentation;Improve the universality of block strategy;Intelligent block of multi-source data is realized, significantly reduces the demand of manual intervention, improves processing speed and efficiency, especially suitable for large-scale document processing scene;It can be directly connected knowledge graph construction, intelligent retrieval and other downstream applications, significantly improve data utilization efficiency.

Aspects of the present disclosure provide various techniques, apparatuses, and methods that may improve memory resource utilization of a data storage device that stores data using a non-volatile memory (NVM). In some aspects, a data storage device may be provided with multiple write buffers to improve write throughput of the device. In some aspects, a data storage device may track utilization information for each write buffer using a utilization array. In some aspects, a data storage device may vary the use of a memory with a low utilization write buffer to serve full active logic units to preserve the functionality of the write buffer of the active logic units.

The invention discloses an interface generation method and system for mapping data by using a visual interaction panel, and belongs to the technical field of dynamic interface rendering. The method comprises the following steps: acquiring a multi-source data stream and extracting static and dynamic behavior features to generate feature anchor points; constructing a dynamic logic topology comprising components, links and logic units on the interaction panel; translating the service association into layout instructions and fusing to generate a collaborative constraint network; inputting the real-time data stream for rendering to generate an interface; and collecting feedback to carry out collaborative optimization on the logic parameters and the layout weight. According to the method, a shadow deduction initialization and closed-loop feedback adjustment mechanism is adopted, deep decoupling and self-adaptive alignment of data logic and interface layout can be achieved, and the accuracy and robustness of interface generation and the interaction configuration efficiency under large-scale heterogeneous data are improved.

The invention discloses an object data processing method and device, a storage medium and electronic equipment, and relates to the technical field of computers. Under the condition that write-in operation is completed based on the object data, a data storage address and a transition layer address distributed for the object data are obtained, the data storage address is used for indicating the write-in position of the object data, and the transition layer address determines the mapping relation between the logic unit address of the object data and the transition layer address; adding a first mapping relation between the logic unit address and the transition layer address in the first mapping relation set; and in the second mapping relation set, a second mapping relation between the transition layer address and the data storage address is added, so that the mapping relation between the data storage address and the logic unit address is effectively dissociated based on the transition layer address, and the problem of low efficiency of existing data operation is solved.

The invention discloses a control system of an ANPC type three-level inverter and a zero crossing point switching method. The method comprises a processor, a programmable logic unit and the ANPC type three-level inverter. The processor is used for generating modulated waves as output signals of the processor based on internal signals of the processor, and the modulated waves comprise a first signal modulated wave PWMA, a second signal modulated wave PWMB and a periodic modulated wave PWMD; the programmable logic unit is used for generating a control signal of each switch tube in the ANPC type three-level inverter based on the modulation wave and an internal signal of the logic unit; and the ANPC type three-level inverter is used for performing on-off control on each switching tube based on the control signal of each switching tube output by the programmable logic unit. The operation of software in the processor can be simplified, the development difficulty and the maintenance cost of the software are reduced, and meanwhile subsequent updating iteration and troubleshooting work are facilitated.

The invention belongs to the technical field of power system relay protection, and particularly relates to a relay protection device hidden fault detection method and system. The method comprises the following steps: acquiring current detection values of multi-source monitoring parameters of the relay protection device, wherein the types of the multi-source monitoring parameters comprise at least two of a power supply parameter, an environment parameter, a communication performance parameter and a logic unit parameter; the power supply parameters comprise voltage fluctuation and / or ripple coefficients, the environment parameters comprise at least one of temperature, humidity and vibration, the communication performance parameters comprise transmission delay and / or bit error rate, and the logic unit parameters comprise CPU load and / or memory occupation; determining the deviation degree of the relay protection device based on the deviation between the current detection value of the multi-source monitoring parameter and the health baseline of the multi-source monitoring parameter; whether hidden faults exist or not is judged based on the deviation degree of the relay protection device and the hidden fault threshold value of the relay protection device, parameter gradual change type faults, environment coupling type faults and logic soft faults can be recognized, and detection blind areas are avoided.

The application discloses a successive approximation type analog-digital converter and a control method thereof, relates to the technical field of analog-digital conversion, and comprises a dynamic comparison unit, a capacitor array synchronizer, an output register and a logic unit, wherein the dynamic comparison unit comprises a dynamic comparator and an array capacitor circuit, the positive and negative terminals of the dynamic comparator are connected with one array capacitor circuit respectively, the output terminal of the dynamic comparator is connected with the logic unit, the output of the logic unit is connected with the output register, the array capacitor circuit and the capacitor array synchronizer, and the capacitor array synchronizer is connected with the dynamic comparator. In view of the technical problem of slow conversion speed of the existing high-speed asynchronous SAR ADC circuit, the application reduces the time waste of the array dac in the traditional scheme, greatly reduces the conversion time, and thus improves the high-speed characteristics of the asynchronous SAR ADC.