18 results about "And logic unit" patented technology

A memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (LUNs) and are associated with corresponding LUN queue groups. Each LUN queue group may include LUN queues that are each associated with a respective intra-LUN priority level that indicates a priority of a LUN queue within a LUN queue group. The LUN queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a LUN queue across LUN queue groups. A quantity of intra-LUN priority levels may be greater than a quantity of execution priority levels. A LUN scheduler may be configured to select and transfer commands from LUN queue groups to the execution queue group based on intra-LUN priority levels. A command executor may be configured to execute commands from the execution queue group based on execution priority levels.

The invention discloses a multi-voltage supply system for an OTP memory. The multi-voltage supply system comprises a band-gap reference unit, a first buffer, a second buffer, a protection voltage generation unit, a programming voltage generation unit, a read-write voltage generation unit and a logic unit, the protection voltage generation unit is used for generating protection voltage through a charge pump; the programming voltage generation unit is used for generating programming voltage through a charge pump; the read-write voltage generation unit is used for generating read-write voltage through voltage clamp. According to the invention, the defects of the traditional scheme in the aspects of voltage precision, power consumption and flexibility are effectively solved, the ripple of the output voltage is remarkably reduced, the high stability and temperature adaptability of the output voltage are ensured, and the integration level, power consumption optimization and dynamic regulation capability are remarkably improved.

The invention relates to an interlocking board card test platform. The interlocking board card test platform comprises a computer, a power supply board, a mother board and a logic machine cage, the logic machine cage is internally provided with a mother board, one side of the mother board is provided with a power supply board and a plurality of logic unit board cards, and one side, opposite to the logic unit board cards, of the mother board is provided with a rear plugboard; the power supply board supplies power to each logic unit board card through the mother board; the computer is in signal connection with the logic unit board card on the mother board, and test software is configured on the computer and used for testing the logic unit board card. Compared with the prior art, automation of the testing process is achieved, the testing efficiency and accuracy are greatly improved, and the dependency degree of manual operation is reduced.

This invention discloses a method for remotely updating a ZYNQ unit's LVDS interface. The ZYNQ unit comprises an embedded ZYNQ unit and a logic unit. An LVDS receiving module is configured in the ZYNQ logic unit to match the LVDS communication protocol with the embedded LVDS computer upgrade system, enabling the ZYNQ chip to establish LVDS interface communication with the embedded LVDS computer upgrade system. After the ZYNQ chip powers on and operates normally, establishing LVDS interface communication with the embedded LVDS computer upgrade system, the embedded LVDS computer upgrade system sends the BIN file to be updated to the ZYNQ chip via the LVDS interface for erasure and rewriting. This invention employs a working firmware and recovery firmware design, and through multiple boot modes, solves the problem of ZYNQ failing to start normally after an unexpected power outage during the update process. It has advantages such as simple operation, high reliability, and no need to unpack the device. Even if the device experiences an unexpected power outage during the update process, the multiple boot methods ensure that the device can still operate normally after power-on and re-update the program. This invention is suitable for field test program updates, solving the problem of having to unpack the device for field test program upgrades, and the remote program update is stable and reliable.

The application discloses an interface generation method and system for mapping data by using a visual interaction panel, and belongs to the technical field of dynamic interface rendering. The method comprises the following steps: acquiring a multi-source data stream, extracting static and dynamic behavior characteristics, and generating feature anchor points; constructing a dynamic logic topology comprising components, links and logic units on the interaction panel; translating business association into layout instructions and fusing to generate a collaborative constraint network; inputting real-time data stream for rendering to generate an interface; and collecting feedback to collaboratively optimize logic parameters and layout weights. The application adopts a shadow deduction initialization and closed-loop feedback adjustment mechanism, can realize deep decoupling and adaptive alignment of data logic and interface layout, and improves the accuracy, robustness and interactive configuration efficiency under large-scale heterogeneous data of interface generation.

This invention relates to the field of high-precision industrial printing technology and discloses a multi-printerhead synchronous printing system based on a distributed architecture, including a workstation, an FPGA processing board, and print head modules. This system separates non-real-time large-scale computing from real-time high-precision control through a distributed architecture. When increasing the number of print heads, only additional computing tasks need to be added to the workstation, and logic units and I / O interfaces are expanded on the FPGA. The workstation parses the image data of each print job, completes dynamic load segmentation, establishes a segmentation index table, and then packages the data and embeds timestamps, ensuring that the FPGA processing board has sufficient time to complete decompression and caching, and also ensuring precise start of the printing operation at the specified time point. The distributed parsing has strong scalability, and the FPGA processing board constructs a global synchronization mechanism to ensure precise alignment of data from different channels in the time dimension. Waveform queries are performed on data packets to generate personalized drive waveforms adapted to each piezoelectric print head, resulting in excellent multi-printer collaboration.

The application discloses a kind of standardization data block processing systems of supporting multi-source data format, it is related to data processing field, the system includes preprocessing and format uniformity module, intelligent pre-analysis and strategy selection module, mixed inference depth block engine, block result optimization and check module, structured data output module.The application supports the compatible processing of multi-source data format;Based on the dynamic division of chapter structure and logic unit of text content, ensure semantic association content, avoid cross-modal semantic fragmentation;Improve the universality of block strategy;Intelligent block of multi-source data is realized, significantly reduces the demand of manual intervention, improves processing speed and efficiency, especially suitable for large-scale document processing scene;It can be directly connected knowledge graph construction, intelligent retrieval and other downstream applications, significantly improve data utilization efficiency.

The invention discloses an interface generation method and system for mapping data by using a visual interaction panel, and belongs to the technical field of dynamic interface rendering. The method comprises the following steps: acquiring a multi-source data stream and extracting static and dynamic behavior features to generate feature anchor points; constructing a dynamic logic topology comprising components, links and logic units on the interaction panel; translating the service association into layout instructions and fusing to generate a collaborative constraint network; inputting the real-time data stream for rendering to generate an interface; and collecting feedback to carry out collaborative optimization on the logic parameters and the layout weight. According to the method, a shadow deduction initialization and closed-loop feedback adjustment mechanism is adopted, deep decoupling and self-adaptive alignment of data logic and interface layout can be achieved, and the accuracy and robustness of interface generation and the interaction configuration efficiency under large-scale heterogeneous data are improved.

The invention belongs to the technical field of power system relay protection, and particularly relates to a relay protection device hidden fault detection method and system. The method comprises the following steps: acquiring current detection values of multi-source monitoring parameters of the relay protection device, wherein the types of the multi-source monitoring parameters comprise at least two of a power supply parameter, an environment parameter, a communication performance parameter and a logic unit parameter; the power supply parameters comprise voltage fluctuation and / or ripple coefficients, the environment parameters comprise at least one of temperature, humidity and vibration, the communication performance parameters comprise transmission delay and / or bit error rate, and the logic unit parameters comprise CPU load and / or memory occupation; determining the deviation degree of the relay protection device based on the deviation between the current detection value of the multi-source monitoring parameter and the health baseline of the multi-source monitoring parameter; whether hidden faults exist or not is judged based on the deviation degree of the relay protection device and the hidden fault threshold value of the relay protection device, parameter gradual change type faults, environment coupling type faults and logic soft faults can be recognized, and detection blind areas are avoided.

The invention discloses an interaction method for constructing a data processing flow in a graphical user interface. According to the method, a data block capable of adapting to multi-industry requirements is provided as a unified interaction component, so that a user can intuitively construct a data processing network by recursively adding the block, visually connecting the configured data flow and automatically executing an updating mode. The core of the method is that multiple types of data blocks are provided, and different numbers and different types of format units and logic units are predefined in different types of data blocks to respectively match specific data processing requirements of different industries such as finance, medical treatment, logistics and the like, so that wide cross-industry adaptability is realized. Based on the unified interaction normal form, the invention further realizes the template multiplexing of the data processing network, supports multi-user collaborative editing and compiles and outputs the data processing network as an embedded code or an executable program.

The utility model discloses a test circuit, a chip and equipment. The test circuit comprises a first data selector, a sensing control scanning bypass and a logic unit, the first data selector comprises a first input end, a second input end and a first enabling end, the first input end is connected with a signal output end of a sensing control unit, the sensing control scanning bypass comprises storage units connected in a scanning chain mode, and the logic unit comprises a second enabling end and a second enabling end. One end of the logic unit is connected with the signal receiving end of the sensing control unit, the other end of the logic unit is connected with the second input end, and the logic unit is connected with the first enabling end and is configured to output a corresponding enabling signal to the first enabling end in a first test mode; therefore, the first data selector selectively outputs a test signal of the sensing control scanning bypass or outputs a sensing signal of the sensing control unit. Therefore, according to the embodiment of the invention, the operation parameters of the chip in the test mode can be normally obtained on the premise of not influencing the chip test, so that an analysis basis is provided for the test failure reason of the chip.

The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

A transmitter circuit is provided having an additional delay path. A first transmitter output signal is generated according to a rising edge and falling edge of its data input signal. A second transmitter output signal is generated by delaying the first transmitter output signal. The disclosed transmitter circuit includes a rising and falling converter for outputting a converted data input signal, a delay and logic unit for receiving the converted data input signal and generating a carrier signal, an AND gate receiving the converted data input signal and the carrier signal, and outputting the first transmitter output signal, and a delay circuit receiving the first transmitter output signal and outputting the second transmitter output signal. Robustness and common mode voltage stability can be enhanced. Due to a definite and limited number of pulses of the carrier signal, the invention also achieves to reduce power consumption and electromagnetic interferences effectively.

The invention provides a storage and calculation integrated chip which comprises an MAC unit and an auxiliary unit which are arranged in pairs, the MAC unit is used for carrying out multiply-accumulate calculation on weight data and input data, the auxiliary unit is used for carrying out multiply-accumulate calculation on the weight data and auxiliary data, and the auxiliary data are obtained after the input data are disordered; the logic unit is used for respectively performing ReLU activation and pooling operation on the multiply-accumulate calculation results of the MAC unit and the auxiliary unit to obtain an output result; the calculation module is also used for calculating an output difference value matrix and calculating an input difference value matrix if the convolutional layer needs to be trained; the auxiliary unit is also used for carrying out matrix multiplication calculation on the output difference value matrix and the input difference value matrix to obtain a weight updating matrix; and the control unit is used for executing the executable instruction so as to control the data flows of the MAC unit, the auxiliary unit and the logic unit. According to the invention, independent training among the convolution layers can be realized.

The invention relates to the technical field of electronics, and discloses a delay circuit, a PCB and a chip, and the delay circuit comprises a threshold generation unit, a delay generation unit, a following unit, a comparison unit and a logic unit. The threshold value generation unit is used for generating a voltage threshold value changing along with the temperature; the delay generation unit is used for generating capacitor charging voltage; the following unit is used for limiting the capacitor charging voltage to protect the comparison unit; the comparison unit is used for comparing the voltage threshold with the capacitor charging voltage so as to output a level change signal; the logic unit is used for outputting a delay signal according to the level change signal and adjusting the working states of the threshold value generation unit and the delay generation unit; through cooperation of the units, the problem of delay time deviation caused by a fixed threshold value and element temperature excursion of a traditional circuit is effectively solved.

A multi-node server with power scaling includes a power supply unit and a plurality of node motherboards. Each of the node motherboards includes a power switch unit, a protection module, and a processing module. The power switch unit is configured to generate an output voltage based on an operating current received from the power supply unit. The protection module includes a comparator unit and a logic unit. The comparator unit is configured to generate a first logic signal and a second logic signal based on the output voltage, a first reference voltage and a second reference voltage. The logic unit is configured to perform a logical operation based on the first logic signal, the second logic signal, and a setting signal in order to generate a power control signal that switches between a power suppressing logic level and a non-power suppressing logic level.

The application discloses a kind of object data processing method and device, storage medium and electronic equipment, involve computer field technical field, comprising: receiving data write request;In the case where write operation is completed based on object data, the data storage address and transition layer address allocated for object data are obtained, wherein the data storage address is used to indicate the writing position of object data, and the mapping relationship between the logical unit address of object data and transition layer address is determined;In the first mapping relationship set, the first mapping relationship between the logical unit address and transition layer address is added;In the second mapping relationship set, the second mapping relationship between transition layer address and data storage address is added, so that the mapping relationship between data storage address and logical unit address is effectively dissociated based on transition layer address, and then the problem of low efficiency of existing data operation is solved.

The invention relates to a circuit system (10) having a detection unit (12), a switching unit (14) and a logic unit (16). The detection unit (12) is designed to measure a dead time of the switching unit (14), and the logic unit (16) is designed to determine a change in the dead time on the basis of a value of the dead time measured by the detection unit (12) and thus ascertain a correction value for the dead time of the switching unit (14). Thus, the change in dead time in each step is not necessarily a previously specified constant value, but varies according to the measured dead time.