10921 results about "Semiconductor structure" patented technology

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on / in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: carrying out the etching of a substrate through employing an etching technology, so as to form a high-aspect-ratio etching structure on the substrate; after a periodic cycle step of a preset number of times of etching process is completed every time, a treatment process different from the etching process is used, and partial thickness of a passivation layer deposited on the side wall of an intermediate structure formed before the high aspect ratio etching structure is formed is removed. And removing at least part of the protruding part which exists on the side wall and is exposed from the surface of the residual passivation layer. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

A computer implemented method for defect detection comprises obtaining an imaging dataset of a wafer, and verifying a defect criterion in a subset of the imaging dataset of the wafer. The defect criterion comprises an observation representation of the subset of the imaging dataset with respect to a number of characteristic elements derived from reference images of semiconductor structures. The observation representation and the characteristic elements define a reconstruction of minimal reconstruction error, and a tolerance statistic on defect-free representations of subsets of defect-free observed imaging datasets. Each of the defect-free representations and the characteristic elements define a reconstruction of minimal reconstruction error of a subset of the defect-free imaging datasets. The computer implemented method further comprises generating defect information.

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source / drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source / drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source / drain feature; and a power rail disposed under and electrically connected to the first via.

Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

The invention provides an optical module, an optoelectronic integrated semiconductor structure and an optical switching system. The optical module comprises: an electrical input / output interface; an optical input / output interface; the light emitting unit is used for converting an input electric signal received from the electric input / output interface into an output light signal; the optical receiving unit is used for converting an input optical signal received from the optical input / output interface into an output electric signal; and a control unit for controlling the light emitting unit to convert the input electrical signal to the output optical signal, and controlling the light receiving unit to convert the input optical signal to the output electrical signal. The input electrical signal and the output electrical signal are PCIe electrical signals.

The invention provides a method for adjusting the height of a grid electrode and a semiconductor structure, and belongs to the field of semiconductors. The method of adjusting gate height includes providing a semiconductor substrate. And etching back the hard mask layer in the NMOS region to reduce the thickness of the hard mask layer in the NMOS region. And after back etching, gate structures are respectively formed in the PMOS region and the NMOS region. And filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region. And patterning a groove, etching the groove in the PMOS region, and when the groove is etched in the PMOS region, the thickness lost by the hard mask layer in the PMOS region is basically equal to the thickness lost by etching the hard mask layer in the NMOS region. By depositing the hard mask layer and etching the hard mask layer, the thickness of the hard mask layer in the PMOS region is basically equal to that of the hard mask layer in the NMOS region, so that the height of the formed grid electrode in the PMOS region is basically equal to that of the grid electrode in the NMOS region, and the performance of the device can be improved.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and particularly relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: providing an initial semiconductor structure, wherein a metal layer is deposited on the initial semiconductor structure; performing first annealing treatment on the metal layer to generate a metal silicon compound; processing the initial semiconductor structure by using a first cleaning solution, wherein the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide and ferrous ions; processing the initial semiconductor structure by using a second cleaning solution, wherein the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide and water; and performing second annealing treatment on the metal silicon compound to generate a self-aligned silicide layer. By adopting the preparation method of the semiconductor structure, the removal temperature of the unreacted metal layer can be reduced, the influence and damage of high temperature on the thermal stability of the metal silicon compound are avoided, and the product yield is improved.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The invention discloses a memory, a manufacturing method thereof and electronic equipment. The memory comprises a first semiconductor structure, and the first semiconductor structure comprises an active column row, a word line, a data storage unit and a first contact plug. The active column row comprises a plurality of active columns extending in the first direction and arranged in the second direction, the active columns comprise first active columns located in a first area and second active columns located in a second area, the second area is located on at least one side of the first area in the second direction, and the second direction is perpendicular to the first direction; a word line extending in the second direction in the first region and the second region, and coupled with a plurality of active pillars in the active pillar row; the data storage unit is positioned on the first side of the first active column in the first direction and is coupled with the first active column; the first contact plug is located in the second area and is coupled with the word line. The orthographic projection of the first contact plug along the first direction is overlapped with the orthographic projection of the second active column along the first direction.

Semiconductor structures including stacked transistors are provided. The semiconductor structures can include a pair of stacked forksheet transistors that have a shared second (top) gate electrode, or the structures can include a pair of stacked forksheet transistors that have non-shared second (top) gate electrodes. In either of these embodiments, the second (top) gate electrode is separated from a first (bottom) gate electrode by a frontside gate cut structure.

The invention discloses a semiconductor structure processing method and a semiconductor structure, and the processing method comprises the steps: providing a substrate with a high-aspect-ratio etching structure, and enabling the side wall of the high-aspect-ratio etching structure to have rough surface morphology; performing a first treatment on the surface of the sidewall using first neutral particles to generate an oxide layer on the surface of the sidewall; performing second treatment on the surface of the side wall by using second neutral particles so as to remove the oxide layer and reduce the roughness of the surface of the side wall; and performing third treatment on the surface of the side wall by using third neutral particles so as to repair lattice damage existing on the surface of the side wall. According to the method, different neutral particles are excited by using metastable state particles, and the rough surface of the side wall is correspondingly treated, so that the treatment degree can be finely controlled, lower damage is realized, the uniformity is more controllable, the surface of the treated side wall is smoother, and the performance of a device is improved.

A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a layer stack of an undoped semiconductor material layer and a source semiconductor layer. The undoped semiconductor material layer contacts a bottom end of the vertical semiconductor channel.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

A semiconductor structure including a stacked forksheet FET is provided. The semiconductor structure includes a frontside gate cut structure that physically isolates a bottom forksheet FET from a top forksheet FET. The frontside gate cut structure provides a physical barrier that allows for a first metal gate electrode to be removed from the top forksheet FET without negatively impacting (i.e., removing) the first metal gate electrode of the bottom FET. After removal of the first metal gate electrode from the top forksheet FET, a second metal gate electrode can be formed in the area of the top forksheet FET which was previously occupied by the first metal gate electrode.

The method comprises the following steps that S1, a substrate on which secondary side wall etching is to be carried out is provided, the substrate comprises a PMOS area and an NMOS area, grid structures are formed on the PMOS area and the NMOS area, and second side wall layers are formed on the surface of the substrate and the grid structures; s2, forming a planarization material layer on the substrate, wherein the surface of the planarization material layer is higher than the gate structure; s3, synchronously etching the planarization material and the second side wall layer and the gate structure below the planarization material until the height difference of the gate structure of the PMOS region and the NMOS region is reduced to be within a target range; s4, the remaining planarization material is removed; and S5, etching the second side wall layer to obtain a gate side wall. Before the second grid side wall etching process is started, the grid height difference is reduced or even eliminated, and the influence on other subsequent processes is avoided.

A semiconductor structure including a first nanosheet transistor device, a second nanosheet transistor device, a dielectric gate cut structure between and electrically isolating the first nanosheet transistor device from the second nanosheet transistor device, where a first portion of the dielectric gate cut structure has a positive tapered profile, and a second portion of the dielectric gate cut structure has a negative tapered profile.

A semiconductor structure including a high kappa (high-kappa) material for a source / drain (S / D) and / or heat spreader and a method of forming the same are provided. The semiconductor structure includes a substrate, a plurality of channel layers stacked over the substrate, a gate structure covering the plurality of channel layers, and S / D regions disposed over the substrate at opposite sides of the gate structure and connecting the plurality of channel layers. The material of the S / D region includes a highly thermally conductive material having a single crystal structure, such as boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. In this case, the high thermal conductivity material can effectively dissipate heat generated by the semiconductor structure, thereby improving the yield and reliability of the semiconductor structure.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor structure for optimizing source and drain contact, which comprises a drain, a semiconductor epitaxial layer, a source and a grid, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P well layer, an N well layer and a P-layer, the P-layer is internally provided with source polycrystalline silicon, and the N drift layer is internally provided with drain polycrystalline silicon. The top end of the source polycrystalline silicon is in ohmic contact with the source electrode; three metal oxide layers are arranged in the N well layer, and the top ends of the three metal oxide layers are connected with a source electrode; a plurality of semicircular metal layers are also arranged in the drain electrode; and the semicircular metal layers are in ohmic contact with the N substrate layer. According to the invention, a low-resistance channel is formed through the high-concentration phosphorus-doped heavily-doped gate, the charge and discharge time of gate charges is reduced, and the doped gate provides an additional conductive path, so that the switching time is reduced, the power conversion efficiency is improved, and the heat loss is reduced.

The problem of forming a deep trench isolation structure suitable for photodetectors with small pitch is solved by a process in which a grid of trenches is etched from the front side using high energy plasma followed by annealing. The trenches are filled with an oxide followed by etching to recess the oxide. The trench recesses are filled with semiconductor to form a grid-shaped semiconductor structure. After FEOL processing, BEOL processing, attachment to a second substrate, and thinning from the back side, an etch removes the oxide from the back side. The etch stops on the grid-shaped semiconductor structure. The trenches are then lined and filled from the back side. The front side etch allows the trenches to be made narrow and with highly vertical sidewalls. Lining and filling the trenches from the back side provides good optical and electrical isolation.

Techniques are provided for hybrid bonding metallic bonding pads embedded in high-K dielectric material to form a high capacitance device. For example, a device comprises a first semiconductor structure bonded to a second semiconductor structure, and a plurality of metal pads at an interface portion between the first semiconductor structure and the second semiconductor structure. The plurality of metal pads are disposed in a high-K dielectric layer. The plurality of metal pads and the high-K dielectric layer comprise at least one capacitor.

The embodiment of the invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate, a stacking structure and a bit line structure. The stack structure and the bit line structure are located on the semiconductor substrate. The stacked structure comprises separation layers and composite layers which are alternately stacked in the vertical direction. The bit line structure extends in the vertical direction and penetrates through the stacking structure. The semiconductor substrate comprises an array region and a peripheral region; the stacked structure located in the peripheral area comprises a capacitor area. A row of bit line structures are respectively formed outside two opposite sides of the capacitor area along the first direction. Wherein the composite layer of the capacitor region comprises a first polar plate. The first polar plates are distributed on the two opposite sides of the composite layer of the capacitor area at intervals in the first direction and protrude outwards. Each first polar plate is connected to a corresponding bit line structure.

Aspects of the disclosed invention provide a semiconductor structure for a semiconductor chip with two layers of semiconductor devices, where the first layer of semiconductor devices directly contacts a semiconductor substrate and connects to a first frontside interconnect wiring. The first layer of semiconductor devices includes at least one trench semiconductor device such as a deep trench capacitor. The first frontside interconnect wiring is electrically connected to the second frontside interconnect wiring by one or more joined metal plugs. The second layer of active devices connects to a backside power delivery network and the second frontside interconnect wiring. The semiconductor chip with two layers of semiconductor devices that are bonded together provides one layer of semiconductor devices capable of being in a portion of the semiconductor substrate and a second layer of semiconductor devices with a backside power delivery network.