5698 results about "Semiconductor structure" patented technology

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention discloses a memory, a manufacturing method thereof and electronic equipment. The memory comprises a first semiconductor structure, and the first semiconductor structure comprises an active column row, a word line, a data storage unit and a first contact plug. The active column row comprises a plurality of active columns extending in the first direction and arranged in the second direction, the active columns comprise first active columns located in a first area and second active columns located in a second area, the second area is located on at least one side of the first area in the second direction, and the second direction is perpendicular to the first direction; a word line extending in the second direction in the first region and the second region, and coupled with a plurality of active pillars in the active pillar row; the data storage unit is positioned on the first side of the first active column in the first direction and is coupled with the first active column; the first contact plug is located in the second area and is coupled with the word line. The orthographic projection of the first contact plug along the first direction is overlapped with the orthographic projection of the second active column along the first direction.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

Methods, devices, and systems for managing layouts of semiconductor structures in memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory block, and the second semiconductor structure includes a driver circuit. The first semiconductor structure and the second semiconductor structure are stacked along a first direction. The driver circuit at least partially overlaps with the first memory block in a plan view perpendicular to the first direction.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention discloses a semiconductor structure, a manufacturing method thereof and electronic equipment. The manufacturing method comprises the following steps: forming a first stack structure on a semiconductor substrate; forming a horizontal opening in the first region of the first stack structure, and forming a first vertical opening exposing the semiconductor substrate and a second vertical opening not exposing the semiconductor substrate at two sides of the first region; epitaxially growing using the first vertical opening to form a single crystal active pattern in the horizontal opening; a transistor is formed based on the active pattern. The process difficulty of forming the single crystal active pattern can be reduced, the defect that holes exist in the active pattern can be avoided or reduced, and the electrical performance of the transistor can be improved.

The invention relates to a semiconductor structure, a preparation method thereof and a magnetic tunnel junction sensor. The semiconductor structure comprises a substrate, and a buffer layer, a solid magnetic layer, a tunnel barrier layer, a free layer and a protective layer which are located on the substrate. The solid magnetic layer comprises an antiferromagnetic pinning layer and a reference layer which are stacked, the antiferromagnetic pinning layer is located on the top surface of the buffer layer, and the magnetization direction of the reference layer is pinned by the antiferromagnetic pinning layer; the tunnel barrier layer is located on the top surface of the reference layer; the free layer is located on the top surface of the tunnel barrier layer, the thickness of the free layer in the direction perpendicular to the substrate continuously and smoothly changes in the preset direction, the thickness value distribution of the free layer conforms to a preset gradient function, and a preset included angle is formed between the preset direction and the pinned magnetization direction of the reference layer; the protective layer is on the top surface of the free layer. Multi-range or continuous wide-range detection can be realized in a single-chip semiconductor device, and high sensitivity is realized.

A semiconductor structure includes an active region including a semiconductor fin base, a stack of nanostructures over the semiconductor fin base, and an epitaxial feature over the semiconductor fin base and connected to at least one of the nanostructures, the active region extending lengthwise in a first direction. The semiconductor structure further includes a gate structure wrapping around each of the nanostructures, the gate structure extending lengthwise in a second direction perpendicular to the first direction, and a backside butted contact disposed directly under and electrically connected to the epitaxial feature and the gate structure. A portion of the backside butted contact extends into the gate structure and the epitaxial feature.

The present disclosure provides a semiconductor structure, a system, and a method of forming a stacked transistor structure with vertically staggered contact vias. The semiconductor structure may include a first stacked transistor cell including a first backside contact having a first contact thickness. The semiconductor structure may also include a second stacked transistor cell including a second backside contact having a second contact thickness different from the first contact thickness. The system may include a semiconductor structure. The method may include forming a first bottom epi and a second bottom epi, filling a first opening in the first stacked transistor cell with one or more metal materials, recessing the one or more metal materials, and filling a second opening in the second stacked transistor cell with the one or more metal materials.

The embodiment of the invention discloses a semiconductor structure, an alignment detection method and a semiconductor device. The semiconductor structure comprises a first semiconductor structure which comprises a first conductive column and a first identifier which are arranged at an interval; the first conductive column extends along a first direction; the first direction is perpendicular to the plane of the first semiconductor structure; the material of the first identifier comprises a conductive material; the plurality of first identifiers are arranged at intervals around the first conductive column in the direction parallel to the plane where the first semiconductor structure is located; the intervals between the first marks located on the two sides of the first conductive column in the second direction and the first conductive column are equal; the second direction is parallel to the plane of the first semiconductor structure. The first conductive column and one first identifier jointly form a capacitor, and the capacitance value of the capacitor represents the alignment degree of the first conductive column and one first identifier.

The invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; forming a laminated structure formed by alternately stacking a plurality of semiconductor material layers and a plurality of insulating material layers on the substrate; channel region laminations and an initial gate column are formed in the lamination structure, the initial gate column at least comprises an initial gate conductive layer and an initial gate dielectric layer, the initial gate column is provided with two opposite first side walls which are in contact with the two adjacent channel region laminations respectively, and a second side wall is not in contact with the channel region laminations; at least removing the gate dielectric layer and the gate conductive layer on the second side wall to form a target gate column, the target gate column having two opposite third side walls in contact with the two adjacent channel region lamination layers, the gate conductive layer on the third side walls having a first length and the gate dielectric layer having a second length, the first length being smaller than the second length, the semiconductor structure with relatively high performance can be obtained through the manufacturing method.

The invention provides a semiconductor structure and a method for preparing the semiconductor structure. The method comprises the following steps: depositing a trap-rich layer on the surface of a substrate; an ultrasonic treatment is applied to the trap-rich layer to reduce the grain size in the trap-rich layer to a range of 30 nm to 150 nm.

In certain examples, methods and semiconductor structures are directed to a strain sensor integrated with a membrane substrate, a pressure sensor, and a plurality of material layers. The material layers are to integrate the strain sensor, the pressure sensor and the membrane substrate, with the pressure and strain sensors operating co-operatively to indicate, in response to a force applied to or towards the pressure sensor, characterization information of the force applied and of deformation of the membrane substrate. In a more specific example, the strain sensor and the membrane substrate are integrated with the aforesaid at least one of the material layers, and at least a portion of the pressure sensor and the membrane substrate are stacked to permit sensing of the force concurrently by the strain sensor and the pressure sensor.

A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

The invention discloses an optical proximity correction method, a mask plate and a semiconductor structure forming method, and the optical proximity correction method comprises the steps: obtaining a reference layout which comprises a plurality of first metal wire patterns, a plurality of second metal wire patterns and a plurality of cutting patterns; a to-be-corrected graph is obtained from the multiple cut-off graphs, the to-be-corrected graph comprises a first to-be-corrected graph and a second to-be-corrected graph, the first to-be-corrected graph and the second to-be-corrected graph are adjacent, and the distance between the first to-be-corrected graph and the second to-be-corrected graph is smaller than a first preset size; determining a target reference pattern corresponding to the to-be-corrected pattern from the plurality of second metal wire patterns; on the basis of the target reference graph, the first to-be-corrected graph and the second to-be-corrected graph are combined and corrected, a combined graph is obtained, the combined graph is formed, and the situation that a mask design rule is violated is avoided.

A method includes: forming an interposer die using a substrate, the interposer die including a plurality of conductive vias in the substrate; bonding the interposer die to a first redistribution layer (RDL); encapsulating the interposer die; forming a second RDL over the interposer die on a side opposite to the first RDL; bonding a first semiconductor die with one of the first RDL and the second RDL; and encapsulating the first semiconductor die.

Embodiments include a semiconductor structure having a first lower transistor and a second lower transistor. Upper transistors are formed above the first and second lower transistors, the first lower transistor having a first work function material, the second lower transistor having a second work function material different from the first work function material. A portion of the second work function material extends below a bottom surface of the first work function material.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

A semiconductor structure includes a source / drain (S / D) region, one or more dielectric layers over the S / D region, one or more semiconductor channel layers connected to the S / D region, an isolation structure under the S / D region and the one or more semiconductor channel layers, and a via under the S / D region and electrically connected to the S / D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S / D region and the isolation structure.

A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.

A method is provided that includes providing a substrate having an N-type region for n-type field effect transistors (nFETs) and a P-type region for p-type field effect transistors (pFETs); forming a gate dielectric layer in the N-type region and the P-type region to wrap the vertically stacked channels; performing dipole processing on the first part of the gate dielectric layer in the N-type region, and keeping the second part of the gate dielectric layer in the P-type region unprocessed; depositing a P-type metal layer in the gate dielectric layer of the P-type region and the N-type region; and forming a filling metal layer on the P-type metal layer of the P-type region and the N-type region.

The invention provides a semiconductor structure, which comprises a substrate, an oxide layer located on a surface of the substrate, a gate electrode located on the substrate and partially contacting the substrate, a first field plate located on the oxide layer, a first dielectric layer covering the gate electrode, a second dielectric layer located on the first dielectric layer, a second field plate located between the first dielectric layer and the second dielectric layer, and a third field plate located on the second dielectric layer, wherein a horizontal position of the second field plate is located between a horizontal position of the first field plate and a horizontal position of the third field plate when viewed from a sectional view.

A semiconductor structure includes a substrate, plurality of active channels, a metal gate, a plurality of inner spacers and a first isolation layer. The substrate has an upper surface and a recess recessed relative to the upper surface. The active channels are vertically stacked on the upper surface of the substrate. The metal gate is disposed on the active channels. The inner spacers are disposed on a lateral surface of the metal gate. The first isolation layer is disposed within the recess and connected with the bottommost inner spacer. The first isolation layer protrudes relative to the upper surface of the substrate.

The invention provides a memory device, a forming method and a memory system, and relates to the technical field of semiconductors. The memory device comprises a first semiconductor structure, and the first semiconductor structure comprises a stacking structure which comprises at least two first insulating layers and at least two second insulating layers which are alternately stacked along a first direction; the capacitor structure penetrates through the stacking structure; and the transistor is connected with the capacitor structure. According to the technical scheme, on one hand, the probability of bending of the capacitor can be reduced while the process difficulty can be reduced, and on the other hand, the total height of the capacitor structure can be increased, so that the capacitance of the capacitor can be increased, and the sensing tolerance of reading the storage unit is improved.

A semiconductor device includes: a first semiconductor structure including a first semiconductor substrate, one or more first conductive patterns, a plurality of first conductive plugs, and a first bonding pad; a second semiconductor structure including a second semiconductor substrate, a plurality of second conductive patterns, one or more second conductive plugs, and a second bonding pad; and two through electrodes penetrating the second semiconductor substrate and respectively connected to two second conductive patterns positioned at opposite ends of the plurality of second conductive patterns, wherein the second bonding pad is bonded to the first bonding pad so that the plurality of second conductive patterns, the one or more second conductive plugs, the second bonding pad, the first bonding pad, the plurality of first conductive plugs, and the one or more first conductive patterns form a daisy chain.

A semiconductor structure includes a conductive bump disposed between a substrate and a board; an isolation member disposed over the board and surrounding the conductive bump and the substrate; a metallic member disposed between the isolation member and the conductive bump; and a solder disposed between the substrate and the board and configured to attach the metallic member to the substrate and the board. A method of manufacturing a semiconductor structure includes disposing a first solder on a first surface of a substrate; disposing a metallic member to the first surface of the substrate by the first solder; disposing a second solder on a board; and bonding the metallic member to the board by the second solder.

Semiconductor structures and methods of forming the same are provided. An exemplary method incudes forming a first dielectric layer over a first conductive feature, forming a conductive via extending through the first dielectric layer and coupled to the first conductive feature, forming a hard mask layer over the conductive via, patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer on the sacrificial layer, after the forming of the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask layer disposed directly over the conductive via with a second conductive feature.