9628 results about "Electroplating" patented technology

Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.

An exemplary apparatus and method of forming a ruthenium tetroxide containing gas to form a ruthenium containing layer on a surface of a substrate is described herein. The method and apparatus described herein may be especially useful for fabricating electronic devices that are formed on a surface of the substrate or wafer. Generally, the method includes exposing a surface of a substrate to a ruthenium tetroxide vapor to form a catalytic layer on the surface of a substrate and then filling the device structures by an electroless, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) or plasma enhanced ALD (PE-ALD) processes. In one embodiment, the ruthenium containing layer is formed on a surface of a substrate by creating ruthenium tetroxide in an external vessel and then delivering the generated ruthenium tetroxide gas to a surface of a temperature controlled substrate positioned in a processing chamber. In one embodiment, a ruthenium tetroxide containing solvent formation process is used to form ruthenium tetroxide using a ruthenium tetroxide containing source material. In one embodiment, of a ruthenium containing layer is formed on a surface of a substrate, using the ruthenium tetroxide containing solvent. In another embodiment, the solvent is separated from the ruthenium tetroxide containing solvent mixture and the remaining ruthenium tetroxide is used to form a ruthenium containing layer on the surface of a substrate.

Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

The present invention generally provides an apparatus and method for selectively forming a metallized feature, such as an electrical interconnect feature, on a electrically insulating surface of a substrate. The present invention also provides a method of forming a mechanically robust, adherent, oxidation resistant conductive layer selectively over either a defined pattern or as a conformal blanket film. Embodiments of the invention also generally provide a new chemistry, process, and apparatus to provide discrete or blanket electrochemically or electrolessly platable ruthenium or ruthenium dioxide containing adhesion and initiation layers. In general, aspects of the present invention can be used for flat panel display processing, semiconductor processing, solar cell device processing, or any other substrate processing, being particularly well suited for the application of stable adherent coating on glass as well as flexible plastic substrates. This invention may be especially useful for the formation of electrical interconnects on the surface of flat panel display or solar cell type substrates where the line sizes are generally larger than semiconductor devices or where the formed feature are not generally as dense.

Electrochemical cells, and more specifically, rechargeable batteries comprising lithium anodes for use in water and/or air environments, as well as non-aqueous and non-air environments, are presented. In one embodiment, an electrochemical cell includes an anode comprising lithium and a multi-layered structure positioned between the anode and an electrolyte of the cell. A multi-layered structure can include at least a first single-ion conductive material layer (e.g., a lithiated metal layer), and at least a first polymeric layer positioned between the anode and the single-ion conductive material. The invention also can provide an electrode stabilization layer positioned within the electrode, i.e., between one portion and another portion of an electrode, to control depletion and re-plating of electrode material upon charge and discharge of a battery. Advantageously, electrochemical cells comprising combinations of structures described herein are not only compatible with environments that are typically unsuitable for lithium, but the cells may be also capable of displaying long cycle life, high lithium cycling efficiency, and high energy density.

An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

A wafer chuck for holding a wafer during electropolishing and/or electroplating of the wafer includes a top section, a bottom section, and a spring member. In accordance with one aspect of the present invention, the top section and the bottom section are configured to receive the wafer for processing. The spring member is disposed on the bottom section and configured to apply an electric charge to the wafer. In accordance with another aspect of the present invention, the spring member contacts a portion of the outer perimeter of the wafer. In one alternative configuration of the present invention, the wafer chuck further includes a seal member to seal the spring member from the electrolyte solution used in the electropolishing and/or electroplating process.

An exemplary apparatus and method of forming a ruthenium tetroxide containing gas to form a ruthenium containing layer on a surface of a substrate is described herein. The method and apparatus described herein may be especially useful for fabricating electronic devices that are formed on a surface of the substrate or wafer. Generally, the method includes exposing a surface of a substrate to a ruthenium tetroxide vapor to form a catalytic layer on the surface of a substrate and then filling the device structures by an electroless, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) or plasma enhanced ALD (PE-ALD) processes. In one embodiment, the ruthenium containing layer is formed on a surface of a substrate by creating ruthenium tetroxide in an external vessel and then delivering the generated ruthenium tetroxide gas to a surface of a temperature controlled substrate positioned in a processing chamber. In one embodiment, a ruthenium tetroxide containing solvent formation process is used to form ruthenium tetroxide using a ruthenium tetroxide containing source material. In one embodiment, of a ruthenium containing layer is formed on a surface of a substrate, using the ruthenium tetroxide containing solvent. In another embodiment, the solvent is separated from the ruthenium tetroxide containing solvent mixture and the remaining ruthenium tetroxide is used to form a ruthenium containing layer on the surface of a substrate.

A method of producing an electrode brain probe assembly, using a flexible substrate comprising a polymeric layer bearing a conductive material coating. Photolithography and electroplating are used to form a set of contacts and conductors on the polymeric layer of the flexible substrate. Also, the flexible substrate is shaped to have a distal end and to be at least 5 mm long, but less than 5 mm wide and less than 1 mm thick.

The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package, that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a plated rivet-shaped connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.

Various techniques for the fabrication of highly accurate master molds with precisely defined microstructures for use in plastic replication using injection molding, hot embossing, or casting techniques are disclosed herein. Three different fabrication processes used for master mold fabrication are disclosed wherein one of the processes is a combination of the other two processes. In an embodiment of the first process, a two-step electroplating approach is used wherein one of the metals forms the microstructures and the second metal is used as a sacrificial support layer. Following electroplating, the exact height of the microstructures is defined using a chemical mechanical polishing process. In an embodiment of the second process, a modified electroforming process is used for master mold fabrication. The specific modifications include the use of Nickel-Iron (80:20) as a structural component of the master mold, and the use of a higher saccharin concentration in the electroplating bath to reduce tensile stress during plating and electroforming on the top as well as sides of the dummy substrate to prevent peel off of the electroform. The electroforming process is also well suited towards the fabrication of microstructures with non-rectangular cross sectional profiles. Also disclosed is an embodiment of a simple fabrication process using direct deposition of a curable liquid molding material combined with the electroforming process. Finally, an embodiment of a third fabrication process combines the meritorious features of the first two approaches and is used to fabricate a master mold using a combination of the two-step electroplating plus chemical mechanical polishing approach and the electroforming approach to fabricate highly accurate master molds with precisely defined microstructures. The microstructures are an integral part of the master mold and hence the master mold is more robust and well suited for high volume production of plastic MEMS devices through replication techniques such as injection molding.

An apparatus for electroplating a layer of metal on the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer (preferably within 5 mm of the wafer surface) which serves to modulate ionic current at the wafer surface, and a second cathode configured to divert a portion of current from the wafer surface. The ionically resistive ionically permeable element in a preferred embodiment is a disk made of a resistive material having a plurality of perforations formed therein, such that perforations do not form communicating channels within the body of the disk. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.

A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof passivated and coated with a solder-wetting material. A vent hole is then formed from the opposite surface (e.g., wafer back side) to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and solder-wetting material at both the active surface and the thinned back side. A metal layer such as nickel, having a glass transition temperature greater than that of the solder, may be plated to form a dam structure covering one or both ends of the TWI including the solder and solder-wetting material to prevent leakage of molten solder from the TWI during high temperature excursions. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

The present invention provides a wafer carrier that includes a plurality of concentric sealing members that provide a seal, with the outer seal independently movable to allow cleaning of a peripheral backside of the wafer to occur while the wafer is still attached to the wafer carrier, and a plurality of vacuum openings that a re disposed only adjacent to an inner side of the inner seal at a location corresponding to the backside periphery of the wafer.

The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

The present invention relates to a bone plating system and method for fracture fixation of bone. The bone plating system includes a bone plate, at least one locking screw, and at least one non-locking screw. The bone plate has locking holes with threads and non-locking holes. The locking screws have a shaft with a thread for engaging bone and a head with a thread configured and dimensioned to mate with the thread of the locking holes. The non-locking screws have a thread for engaging bone and a non-threaded head. Both the locking and non-locking screws remain seated in their respective holes for substantially as long as the bone plate is implanted. The non-locking screws compress the bone plate against the bone and hold fracture reduction while the locking screws are secured to the plate at a fixed angular relationship. The mixed fixation achieved by this bone plating system and method is particularly useful for treatment of per-articular fractures.

An inductive write element is disclosed for use in a magnetic data recording system. The write element provides increased data rate and data density capabilities through improved magnetic flux flow through the element. The write element includes a magnetic yoke constructed of first and second magnetic poles. The first pole includes a pedestal constructed of a high magnetic moment (high B_sat) material, which is preferably FeRhN nanocrystalline films with lamination layers of CoZrCr. The second pole includes a thin inner layer of high B_sat material (also preferably FeRhN nanocrystalline films with lamination layers of CoZrCr), the remainder being constructed of a magnetic material capable of being electroplated, such as a Ni—Fe alloy. An electrically conductive coil passes through the yoke between the first and second poles to induce a magnetic flux in the yoke when an electrical current is caused to flow through the coil. Magnetic flux in the yoke produces a fringing field at a write gap whereby a signal can be imparted onto a magnetic medium passing thereby.

A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrodes. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the internal electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups. Each exposed portion is within a predetermined distance from other exposed portions in a given group such that termination structures may be formed by deposition and controlled bridging of a thin-film plated material among selected of the exposed internal conductive elements. Electrolytic plating may be employed in conjunction with optional cleaning and annealing steps to form directly plated portions of copper, nickel or other conductive material. Once an initial thin-film metal is directly plated to a component periphery, additional portions of different materials may be plated thereon.

A method and system for plating CoNiFe is disclosed. The method and system include providing a plating solution including hydroxymethyl-p-tolylsulfone and plating the CoNiFe film on a substrate in the plating solution. The plating solution is configured to provide a CoNiFe film having a high saturation magnetic flux density and having a composition of 50-70 weight percent of Fe and 3-8 weight percent of Ni. In another aspect, the method and system include plating at least a portion of a first and/or second pole of a write head using the plating solution including hydroxymethyl-p-tolylsulfone and configured to plate the CoNiFe film having a high saturation magnetic flux density and a composition of 50-70 weight percent of Fe and 3-8 weight percent of Ni.

A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. The semiconductor nanowire forms an FET device with a FET channel region between a source region and a drain region formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire and then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire.

A nanopost glass array contains up to 1012/cm2 of magnetizable nanoposts having diameter of 10-1000 nm that are straight and parallel to each other and are typically of a uniform diameter relative to each other and along the post length. The array is made using a reference electrode and a nanochannel glass template structure connected to each other electrically through an electrical source and both disposed in a plating solution. A magnetizable material is electroplated from the plating solution into the channels of the template structure.

Electrode protection in electrochemical cells, and more specifically, electrode protection in both aqueous and non-aqueous electrochemical cells, including rechargeable lithium batteries, are presented. In one embodiment, an electrochemical cell includes an anode comprising lithium and a multi-layered structure positioned between the anode and an electrolyte of the cell. A multi-layered structure can include at least a first single-ion conductive material layer (e.g., a lithiated metal layer), and at least a first polymeric layer positioned between the anode and the single-ion conductive material. The invention also can provide an electrode stabilization layer positioned within the electrode, i.e., between one portion and another portion of an electrode, to control depletion and re-plating of electrode material upon charge and discharge of a battery. Advantageously, electrochemical cells comprising combinations of structures described herein are not only compatible with environments that are typically unsuitable for lithium, but the cells may be also capable of displaying long cycle life, high lithium cycling efficiency, and high energy density.

The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.

A method and apparatus for fabricating a solar cell and forming metal contact is disclosed. Solar cell contact and wiring is formed by depositing a thin film stack of a first metal material and a second metal material as an initiation layer or seed layer for depositing a bulk metal layer in conjunction with additional sheet processing, photolithography, etching, cleaning, and annealing processes. In one embodiment, the thin film stack for forming metal silicide with reduced contact resistance over the sheet is deposited by sputtering or physical vapor deposition. In another embodiment, the bulk metal layer for forming metal lines and wiring is deposited by sputtering or physical vapor deposition. In an alternative embodiment, electroplating or electroless deposition is used to deposit the bulk metal layer.

A laminate is prepared in which adjacent internal electrodes are electrically insulated from each other at an end surface at which the internal electrodes are exposed, a space between the adjacent internal electrodes, which is measured in the thickness direction of insulating layers, is about 10 μm or less, and a withdrawn distance of the adjacent internal electrodes from the end surface is about 1 μm or less. In an electroplating step, electroplating deposits deposited on the ends of the adjacent internal electrodes are grown so as to be connected to each other.

Separate leads and a common lead are provided on the upper and lower surfaces of a substrate. A plurality of LED elements are disposed in an array on the common lead on the upper surface of the substrate. The common lead provided on the upper surface of the substrate is connected to the common lead provided on the lower surface of the substrate through through-hole plating. Heat generated from the plurality of LED elements is transferred through the common lead provided on the upper surface of the substrate and the through-hole plating to the common lead provided on the lower surface of the substrate and is released therefrom into the air. By virtue of this construction, an light emitting device can be realized in which heat radiating properties are homogenized, heat radiation efficiency is improved, and a compact structure is obtained and, thus, the color balance is improved and unfavorable phenomena such as lowering in the output of light emitting elements and shortening of the service life are avoided.

In order for it to be possible to manufacture a transition with a cost-effective stamping or diecasting or cold-molding process or with a plastic injection-molding process with subsequent metal plating, at least one ridge situated in the waveguide, which reduces the waveguide cross section in the direction of the stripline, has a cross section which tapers conically in the direction of the stripline.

A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

A novel method and apparatus of wet processing workpieces, such as electroplating semiconductor wafers and the like, that incorporates reciprocating processing fluid agitation to control fluid flow at the workpiece, and where electric fields are involved as in such electroplating, controlling the electric field distribution.