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9628 results about "Electroplating" patented technology

Electroplating is a process that uses an electric current to reduce dissolved metal cations so that they form a thin coherent metal coating on an electrode. The term is also used for electrical oxidation of anions on to a solid substrate, as in the formation of silver chloride on silver wire to make silver/silver-chloride electrodes. Electroplating is primarily used to change the surface properties of an object (such as abrasion and wear resistance, corrosion protection, lubricity, aesthetic qualities), but may also be used to build up thickness on undersized parts or to form objects by electroforming.

Method to selectively fill recesses with conductive metal

Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.
Owner:GLOBALFOUNDRIES INC

Ruthenium containing layer deposition method

An exemplary apparatus and method of forming a ruthenium tetroxide containing gas to form a ruthenium containing layer on a surface of a substrate is described herein. The method and apparatus described herein may be especially useful for fabricating electronic devices that are formed on a surface of the substrate or wafer. Generally, the method includes exposing a surface of a substrate to a ruthenium tetroxide vapor to form a catalytic layer on the surface of a substrate and then filling the device structures by an electroless, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) or plasma enhanced ALD (PE-ALD) processes. In one embodiment, the ruthenium containing layer is formed on a surface of a substrate by creating ruthenium tetroxide in an external vessel and then delivering the generated ruthenium tetroxide gas to a surface of a temperature controlled substrate positioned in a processing chamber. In one embodiment, a ruthenium tetroxide containing solvent formation process is used to form ruthenium tetroxide using a ruthenium tetroxide containing source material. In one embodiment, of a ruthenium containing layer is formed on a surface of a substrate, using the ruthenium tetroxide containing solvent. In another embodiment, the solvent is separated from the ruthenium tetroxide containing solvent mixture and the remaining ruthenium tetroxide is used to form a ruthenium containing layer on the surface of a substrate.
Owner:APPLIED MATERIALS INC

Ruthenium layer deposition apparatus and method

An exemplary apparatus and method of forming a ruthenium tetroxide containing gas to form a ruthenium containing layer on a surface of a substrate is described herein. The method and apparatus described herein may be especially useful for fabricating electronic devices that are formed on a surface of the substrate or wafer. Generally, the method includes exposing a surface of a substrate to a ruthenium tetroxide vapor to form a catalytic layer on the surface of a substrate and then filling the device structures by an electroless, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) or plasma enhanced ALD (PE-ALD) processes. In one embodiment, the ruthenium containing layer is formed on a surface of a substrate by creating ruthenium tetroxide in an external vessel and then delivering the generated ruthenium tetroxide gas to a surface of a temperature controlled substrate positioned in a processing chamber. In one embodiment, a ruthenium tetroxide containing solvent formation process is used to form ruthenium tetroxide using a ruthenium tetroxide containing source material. In one embodiment, of a ruthenium containing layer is formed on a surface of a substrate, using the ruthenium tetroxide containing solvent. In another embodiment, the solvent is separated from the ruthenium tetroxide containing solvent mixture and the remaining ruthenium tetroxide is used to form a ruthenium containing layer on the surface of a substrate.
Owner:APPLIED MATERIALS INC

Microfabricated structures and processes for manufacturing same

Various techniques for the fabrication of highly accurate master molds with precisely defined microstructures for use in plastic replication using injection molding, hot embossing, or casting techniques are disclosed herein. Three different fabrication processes used for master mold fabrication are disclosed wherein one of the processes is a combination of the other two processes. In an embodiment of the first process, a two-step electroplating approach is used wherein one of the metals forms the microstructures and the second metal is used as a sacrificial support layer. Following electroplating, the exact height of the microstructures is defined using a chemical mechanical polishing process. In an embodiment of the second process, a modified electroforming process is used for master mold fabrication. The specific modifications include the use of Nickel-Iron (80:20) as a structural component of the master mold, and the use of a higher saccharin concentration in the electroplating bath to reduce tensile stress during plating and electroforming on the top as well as sides of the dummy substrate to prevent peel off of the electroform. The electroforming process is also well suited towards the fabrication of microstructures with non-rectangular cross sectional profiles. Also disclosed is an embodiment of a simple fabrication process using direct deposition of a curable liquid molding material combined with the electroforming process. Finally, an embodiment of a third fabrication process combines the meritorious features of the first two approaches and is used to fabricate a master mold using a combination of the two-step electroplating plus chemical mechanical polishing approach and the electroforming approach to fabricate highly accurate master molds with precisely defined microstructures. The microstructures are an integral part of the master mold and hence the master mold is more robust and well suited for high volume production of plastic MEMS devices through replication techniques such as injection molding.
Owner:CINCINNATI UNIVERISITY OF THE

Plated terminations

InactiveUS6960366B2Improved termination featureEliminate and greatly simplifyResistor terminals/electrodesFinal product manufactureTermination problemEngineering
Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.
Owner:KYOCERA AVX COMPONENTS CORP

Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby

A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.
Owner:INVENSAS CORP
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