20744 results about "Electroplating" patented technology

Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.

An exemplary apparatus and method of forming a ruthenium tetroxide containing gas to form a ruthenium containing layer on a surface of a substrate is described herein. The method and apparatus described herein may be especially useful for fabricating electronic devices that are formed on a surface of the substrate or wafer. Generally, the method includes exposing a surface of a substrate to a ruthenium tetroxide vapor to form a catalytic layer on the surface of a substrate and then filling the device structures by an electroless, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) or plasma enhanced ALD (PE-ALD) processes. In one embodiment, the ruthenium containing layer is formed on a surface of a substrate by creating ruthenium tetroxide in an external vessel and then delivering the generated ruthenium tetroxide gas to a surface of a temperature controlled substrate positioned in a processing chamber. In one embodiment, a ruthenium tetroxide containing solvent formation process is used to form ruthenium tetroxide using a ruthenium tetroxide containing source material. In one embodiment, of a ruthenium containing layer is formed on a surface of a substrate, using the ruthenium tetroxide containing solvent. In another embodiment, the solvent is separated from the ruthenium tetroxide containing solvent mixture and the remaining ruthenium tetroxide is used to form a ruthenium containing layer on the surface of a substrate.

Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

The present invention generally provides an apparatus and method for selectively forming a metallized feature, such as an electrical interconnect feature, on a electrically insulating surface of a substrate. The present invention also provides a method of forming a mechanically robust, adherent, oxidation resistant conductive layer selectively over either a defined pattern or as a conformal blanket film. Embodiments of the invention also generally provide a new chemistry, process, and apparatus to provide discrete or blanket electrochemically or electrolessly platable ruthenium or ruthenium dioxide containing adhesion and initiation layers. In general, aspects of the present invention can be used for flat panel display processing, semiconductor processing, solar cell device processing, or any other substrate processing, being particularly well suited for the application of stable adherent coating on glass as well as flexible plastic substrates. This invention may be especially useful for the formation of electrical interconnects on the surface of flat panel display or solar cell type substrates where the line sizes are generally larger than semiconductor devices or where the formed feature are not generally as dense.

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.

Electrochemical cells, and more specifically, rechargeable batteries comprising lithium anodes for use in water and/or air environments, as well as non-aqueous and non-air environments, are presented. In one embodiment, an electrochemical cell includes an anode comprising lithium and a multi-layered structure positioned between the anode and an electrolyte of the cell. A multi-layered structure can include at least a first single-ion conductive material layer (e.g., a lithiated metal layer), and at least a first polymeric layer positioned between the anode and the single-ion conductive material. The invention also can provide an electrode stabilization layer positioned within the electrode, i.e., between one portion and another portion of an electrode, to control depletion and re-plating of electrode material upon charge and discharge of a battery. Advantageously, electrochemical cells comprising combinations of structures described herein are not only compatible with environments that are typically unsuitable for lithium, but the cells may be also capable of displaying long cycle life, high lithium cycling efficiency, and high energy density.

An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

A wafer chuck for holding a wafer during electropolishing and/or electroplating of the wafer includes a top section, a bottom section, and a spring member. In accordance with one aspect of the present invention, the top section and the bottom section are configured to receive the wafer for processing. The spring member is disposed on the bottom section and configured to apply an electric charge to the wafer. In accordance with another aspect of the present invention, the spring member contacts a portion of the outer perimeter of the wafer. In one alternative configuration of the present invention, the wafer chuck further includes a seal member to seal the spring member from the electrolyte solution used in the electropolishing and/or electroplating process.

An exemplary apparatus and method of forming a ruthenium tetroxide containing gas to form a ruthenium containing layer on a surface of a substrate is described herein. The method and apparatus described herein may be especially useful for fabricating electronic devices that are formed on a surface of the substrate or wafer. Generally, the method includes exposing a surface of a substrate to a ruthenium tetroxide vapor to form a catalytic layer on the surface of a substrate and then filling the device structures by an electroless, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) or plasma enhanced ALD (PE-ALD) processes. In one embodiment, the ruthenium containing layer is formed on a surface of a substrate by creating ruthenium tetroxide in an external vessel and then delivering the generated ruthenium tetroxide gas to a surface of a temperature controlled substrate positioned in a processing chamber. In one embodiment, a ruthenium tetroxide containing solvent formation process is used to form ruthenium tetroxide using a ruthenium tetroxide containing source material. In one embodiment, of a ruthenium containing layer is formed on a surface of a substrate, using the ruthenium tetroxide containing solvent. In another embodiment, the solvent is separated from the ruthenium tetroxide containing solvent mixture and the remaining ruthenium tetroxide is used to form a ruthenium containing layer on the surface of a substrate.

A method of producing an electrode brain probe assembly, using a flexible substrate comprising a polymeric layer bearing a conductive material coating. Photolithography and electroplating are used to form a set of contacts and conductors on the polymeric layer of the flexible substrate. Also, the flexible substrate is shaped to have a distal end and to be at least 5 mm long, but less than 5 mm wide and less than 1 mm thick.

The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package, that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a plated rivet-shaped connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.

Various techniques for the fabrication of highly accurate master molds with precisely defined microstructures for use in plastic replication using injection molding, hot embossing, or casting techniques are disclosed herein. Three different fabrication processes used for master mold fabrication are disclosed wherein one of the processes is a combination of the other two processes. In an embodiment of the first process, a two-step electroplating approach is used wherein one of the metals forms the microstructures and the second metal is used as a sacrificial support layer. Following electroplating, the exact height of the microstructures is defined using a chemical mechanical polishing process. In an embodiment of the second process, a modified electroforming process is used for master mold fabrication. The specific modifications include the use of Nickel-Iron (80:20) as a structural component of the master mold, and the use of a higher saccharin concentration in the electroplating bath to reduce tensile stress during plating and electroforming on the top as well as sides of the dummy substrate to prevent peel off of the electroform. The electroforming process is also well suited towards the fabrication of microstructures with non-rectangular cross sectional profiles. Also disclosed is an embodiment of a simple fabrication process using direct deposition of a curable liquid molding material combined with the electroforming process. Finally, an embodiment of a third fabrication process combines the meritorious features of the first two approaches and is used to fabricate a master mold using a combination of the two-step electroplating plus chemical mechanical polishing approach and the electroforming approach to fabricate highly accurate master molds with precisely defined microstructures. The microstructures are an integral part of the master mold and hence the master mold is more robust and well suited for high volume production of plastic MEMS devices through replication techniques such as injection molding.

An apparatus for electroplating a layer of metal on the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer (preferably within 5 mm of the wafer surface) which serves to modulate ionic current at the wafer surface, and a second cathode configured to divert a portion of current from the wafer surface. The ionically resistive ionically permeable element in a preferred embodiment is a disk made of a resistive material having a plurality of perforations formed therein, such that perforations do not form communicating channels within the body of the disk. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.

A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof passivated and coated with a solder-wetting material. A vent hole is then formed from the opposite surface (e.g., wafer back side) to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and solder-wetting material at both the active surface and the thinned back side. A metal layer such as nickel, having a glass transition temperature greater than that of the solder, may be plated to form a dam structure covering one or both ends of the TWI including the solder and solder-wetting material to prevent leakage of molten solder from the TWI during high temperature excursions. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

In one embodiment of the invention, an anterior fixation system includes a plate defining a plurality of screw holes, a number of screws and a number of locking assemblies for fixing the screws to the plate. The system includes two bone screws a fixed angle screw and a variable angle screw, that are configured to extend through the same screw openings in the fixation plate. The surgeon can select either the fixed or variable angled screws to be implanted with a single plate and can place either type of screw into any of the screw holes along the plate. The fixation plate according to the invention can include several screw holes in various patterns that provide the surgeon with great flexibility in the placement of bone screws depending upon the spinal anatomy and pathology. The invention further contemplates a locking assembly to lock one or more bone screws within a respective screw hole. In one embodiment, the locking assembly includes a washer that is held to the plate by a staked locking screw. The washer includes an outer surface that overlaps one or more screw holes. The washer is initially loosely held to the plate by the locking screw so that various tools and bone screws can be passed through the screw holes. In one embodiment of the washer, the washer includes cut-outs corresponding to the screw holes, along with a notch and key configuration for setting the locking washer in its locked configuration.

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

The present invention provides a wafer carrier that includes a plurality of concentric sealing members that provide a seal, with the outer seal independently movable to allow cleaning of a peripheral backside of the wafer to occur while the wafer is still attached to the wafer carrier, and a plurality of vacuum openings that a re disposed only adjacent to an inner side of the inner seal at a location corresponding to the backside periphery of the wafer.