2481 results about "Active surface" patented technology

A fingerprint-reading system includes a fingerprint sensor having an active surface sensitive to the pressure and temperature of a finger. The surface area of this sensor is far smaller than the surface area of the fingerprint to be read. The reading is done when the sensor and the finger are in contact and in a relative motion of sliding of the sensor and the finger with respect to each other. The system reconstitutes a complete image of the fingerprint from the partial images given by the sensor during this motion.

A thermally enhanced quad flat non-lead package of semiconductor comprises a chip a plurality of leads, and a molding compound. The chip has its active surface bonded to the top surface of the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pads on the active surface of the chip. The leads are disposed at the periphery of the die pad wherein the bottom surface of the lead has a stepped structure with a relatively thin portion to form a wire-bonding protruded zone. A plurality of bonding wires is used to electrically connect the wire-bonding protruded zone of the leads to the bonding pads of the chip. The molding compound encapsulates the chip, bonding wires, the die pad, and a portion of the surface of the leads, but exposes the bottom surface of the die pad. In this way, the encapsulating process makes the side surface of the lead, and the portion excluding the wire-bonding protruded zone of the bottom surface of the lead exposed in order to make the lead become the external connecting points of the package structure.

Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

Methods for forming blind wafer interconnects (BWIs) from the back side of a previously thinned substrate structure such as a semiconductor wafer to the underside of a bond pad on its active surface includes the formation of a blind hole from the back side, application of a passivating layer therein, anisotropically etching to remove passivation material from the blind hole bottom, blanket-depositing at least one conductive layer within the blind hole and over the back side, blanket-depositing a resist in the blind hole and over the back side, planarizing the back side to remove resist and the at least one conductive layer, removing resist from the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material. Variations in the methods include formation of a conductive pad adjacent the back side surface, disposition of a solder ball or other conductive structure on the BWI, or forming an end thereof in the form of an extended slug protruding from the back side (for ball-less attachment) as the outer terminus of the BWI.

PCT No. PCT/GB96/01830 Sec. 371 Date Apr. 21, 1998 Sec. 102(e) Date Apr. 21, 1998 PCT Filed Jul. 25, 1996 PCT Pub. No. WO97/05280 PCT Pub. Date Feb. 13, 1997The invention relates to the detection of target nucleic acids or nucleic acid units in a sample, by obtaining a SER(R)S spectrum for a SER(R)S-active complex containing, or derived directly from, the target. The complex includes at least a SER(R)S-active label, and optionally a target binding species containing a nucleic acid or nucleic acid unit. In this detection method, the concentration of the target present in the SER(R)S-active complex, or of the nucleic acid or unit contained in the target binding species in the SER(R)S-active complex, is no higher than 10-10 moles per liter. Additionally or alternatively, one or more of the following features may be used with the method: i) the introduction of a polyamine; ii) modification of the target, and/or of the nucleic acid or nucleic acid unit contained in the target binding species, in a manner that promotes or facilitates its chemi-sorption onto a SER(R)S-active surface; iii) inclusion of a chemi-sorptive functional group in the SER(R)S-active label. The invention also provides SER(R)S-active complexes for use in such a method, a kit for use in carrying out the method or preparing the complexes and a method for sequencing a nucleic acid which comprises the use of the detection method to detect at least one target nucleotide or sequence of nucleotides within the acid.

An improved bone graft is provided for human implantation, bone graft includes a substrate block of high strength biocompatible material having a selected size and shape to fit the anatomical space, and a controlled porosity analogous to natural bone. The substrate block may be coated with a bio-active surface coating material such as hydroxyapatite or a calcium phosphate to promote bone ingrowth and enhanced bone fusion. Upon implantation, the bone graft provides a spacer element having a desired combination of mechanical strength together with osteoconductivity and osteoinductivity to promote bone ingrowth and fusion, as well as radiolucency for facilitated post-operative monitoring. The bone graft may additionally carry one or more natural or synthetic therapeutic agents for further promoting bone ingrowth and fusion.

A touch screen 1111 having an active surface area 1112 which extends in three physical dimensions (x-, y- and z-dimensions) is provided. In the figure the active surface area has an U-shaped form. When a user slides his finger over the active surface area the tactile feedback gives him information about the position of the finger. The touch screen is activated when the active surface area senses a certain pressure from the finger. The use of the touch screen is facilitated especially when the user is on the move or when the touch screen is out of sight. Such use is common when operating hand-held terminals.

Active surface coupled polymerases, surfaces that include such polymerases, and methods of making and using surface-attached polymerases are provided.

A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof passivated and coated with a solder-wetting material. A vent hole is then formed from the opposite surface (e.g., wafer back side) to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and solder-wetting material at both the active surface and the thinned back side. A metal layer such as nickel, having a glass transition temperature greater than that of the solder, may be plated to form a dam structure covering one or both ends of the TWI including the solder and solder-wetting material to prevent leakage of molten solder from the TWI during high temperature excursions. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

A pillar-to-pillar flip-chip assembly primarily comprises a substrate, a chip disposed on the substrate, a plurality of first copper pillars on the bonding pads of the chip, a plurality of second copper pillars on the bump pads of the substrate, and a soldering material. A first height of the first copper pillars protruding from the active surface of the chip is the same as a second height of the second copper pillars from the solder mask on the substrate. When the soldering material electrically and mechanically connects the first copper pillars to the second copper pillars, a plurality of central points of the soldering material are formed on an equal-dividing plane between the chip and the substrate to reduce the direct stresses exerted at the soldering material to avoid peeling or breaks from the bump pads. Moreover, each of conventional solder balls is replaced with two soldered copper pillars to meet the lead-free requirements with higher reliability and lower costs.

A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

A microelectronic device includes a microelectronic die having an interfacial metal layer deposited over an active surface thereof to perform a signal distribution function within the device. The microelectronic die is fixed within a package core to form a die/core assembly. One or more metallization layers may then be built up over the die/core assembly as part of a packaging scheme. The interfacial metal layer can be applied either before or after the die is fixed within the package core. In one approach, the interfacial layer is applied during wafer-level processing.

A stack structure with semiconductor chips embedded in carriers comprises two carriers stacking together as a whole, at least two semiconductor chips having active surfaces with electrode pads and inactive surfaces corresponding thereto placed in the cavities of the carriers, at least one dielectric layer formed on the active surface of the semiconductor chip and the surface of the carrier, at least a conductive structure formed in the opening of the dielectric layer, and at least a circuit layer formed on the surface of the dielectric layer wherein the circuit layer is electrically connected to the electrode pad by the conductive structure, so as to form a three-dimensional module to increase the storage capacity dramatically and integrate the semiconductor chips in the carriers for efficiently reducing the size of the module, so that the combinations can be changed flexibly to form the required storage capacity according to the demands.

A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial substrate. The sacrificial substrate may include conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. The device substrate is then severed along each street and the newly formed peripheral edge of each semiconductor device coated with dielectric material. If the sacrificial substrate includes conductive elements, they may be exposed between adjacent semiconductor devices and subsequently serve as lower sections of contacts. Peripheral sections of contacts are formed on the peripheral edge. Upper sections of the contacts may also be formed over the active surfaces of the semiconductor devices. Once the contacts are formed, the sacrificial substrate is substantially removed from the back sides of the semiconductor devices.