1229 results about "Chip size" patented technology

To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.

A wafer level chip size package (WLCSP) and a method of manufacturing the same are disclosed. Lands are formed at the ends of redistribution layers. The redistribution layers excluding the lands and a first dielectric layer are covered with a second dielectric layer. After forming a first under bump metallurgy (UBM) layer on the land, a solder ball is reflowed to the first UBM layer. A second UBM layer is widely formed on the entire second dielectric layer that is the outer circumference of the first UBM layer and is connected to the redistribution layer through a via-hole. Therefore, the second UBM layer having a large area can be used as a ground plane or a power plane. In addition, the second UBM layer can electrically connect the redistribution layers physically separated from each other. Therefore, the plurality of redistribution layers can cross each other without being electrically shorted with each other.

A chip-size wavelength detector includes a film with laterally varying transmission properties and a position-sensitive detector. The film transmits a different wavelength as a function of lateral position across the film. The position of a spot of light transmitted through the film will shift, depending on the wavelength of the light. The shift is measured by the position-sensitive detector.

A voltage control system and methodology for maintaining internally generated voltage levels in a semiconductor chip. The method comprises the steps of intermittently sampling an internal voltage supply level during a low power or "sleep" mode of operation; comparing the internal voltage supply level against a predetermined voltage reference level; and, activating a voltage supply generator for increasing the internal voltage supply level when the internal voltage supply level falls below the predetermined voltage reference level. The voltage supply generator is subsequently deactivated when the voltage supply level is restored to the predetermined voltage reference level. The sampling cycle may be appropriately tailored according to chip condition, chip temperature, and chip size. In one embodiment, the voltage control system and methodology is implemented in DRAM circuits during a refresh operation. The voltage levels that are suitable for sampling including DRAM band-gap reference voltage, boost wordline line voltage, wordline low voltage, bitline high voltage and bitline equalization voltages.

A semiconductor wafer provided with columnar electrodes which have plated nickel, palladium, and gold films successively formed at the top thereof, or have a plated solder film at their top. The semiconductor wafer can be preferably used for producing a chip-sized semiconductor device provided with columnar electrodes to which an external connection terminal, such as a solder ball, is to be bonded. Methods of producing the semiconductor wafer and device by use of plating are also disclosed.

A trailing edge of a control signal of a transistor controller for controlling an output transistor is detected by an edge detector of a clamp controlling circuit. A surge voltage from a back electromotive voltage induced in an inductance L1 is absorbed from the output transistor, only for a given period immediately after the solenoid is turned off, by turning a switching transistor into an on-state by a timer to force a clamping circuit into conduction. At a normal operation, since the clamping circuit is cut off from an output terminal, the clamping voltage can be set in a manner to reduce to a normal voltage in an IGN-line. Therefore, a peak power value of a power loss caused by the surge voltage at the output transistor can be reduced, whereby generation of heat at the output transistor can be reduced. Therefore, the chip size of the power IC can be reduced.

A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

The invention relates to a side-emitting LED package and a manufacturing method thereof. The side-emitting LED package includes a substrate with an electrode formed thereon, and a light source disposed on the substrate and electrically connected to the electrode. The side-emitting LED package also includes a molded part having an upper surface with a center thereof depressed concavely, covering and protecting the substrate and the light source, and a reflection layer covering an entire upper surface of the molded part to reflect light sideward from the molded part which forms a light transmitting surface. The package is not restricted in the shape of the molded part and is not affected by the LED chip size, enabling a compact structure. The invention can also process a substrate by a PCB process, enabling mass-production.

A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

A refraction-type LED ceiling lamp, especially a plate-type ceiling lamp which is used on an indoor ceiling, includes primarily a fiber light guide plate, a reflection surface of which is provided with multiple chip-shape reflection elements, distributed in arrays. A chip size of the reflection elements decreases gradually toward an entrance surface by a geometric series; whereas, a gap between the reflection elements increases gradually. A reflection curve of the reflection element allows light to be projected out uniformly and a required illumination angle to be achieved.

A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

An image sensor package includes an image sensor having an active area and bond pads on a front surface of the image sensor. A window is mounted to the image sensor by flip chip bumps formed between the bond pads of the image sensor and interior traces on an interior surface of the window. The window has an area less than an area of the front surface of the image sensor. A bead is formed between the window and the front surface of the image sensor thus forming a sealed cavity in which the active area is located. The bead has sides coplanar with sides of the image sensor such that the image sensor package is chip size.

The present invention intends to prevent the communication distance from becoming shorter with a reduction in size of a coil antenna to the chip size and with a consequent decrease of an induced voltage. According to the present invention there is provided a semiconductor chip having a coil antenna and a circuit surface and adapted to transmit and receive signals by radio to and from an external device. The semiconductor chip has a configuration for increasing an electromagnetic coupling coefficient between the coil antenna and the external device. According to a concrete example thereof, a magnetic material is disposed, the coil antenna is formed by a stacked structure comprising plural conductor layers and insulating layers superimposed one on another, or the coil antenna is disposed outside an external form of a circuit of the semiconductor chip.

Existing multi-band/multi-mode (MB/MM) power amplifiers (PAs) use separate signal paths for the different covered frequency bands. This results in a large degree of hardware duplication and to a large die size and cost. Solutions that achieve hardware sharing between the different signal paths of MB/MM PAs are shown. Such sharing includes bias circuit and bypass capacitors sharing, as well as sharing front-end stages and the output stage of the PA. Signal multiplexing may be realized in the transmitter or at the PA front-end while the signal de-multiplexing can be realized either in the PA output stage or at the front-end of the output stage. Such circuits can be applied with saturated and linear MB/MM PAs with adjacent or non-adjacent bands.