137 results about "Chip size" patented technology

Embodiments of the present disclosure provide a fully decoupled three-axis MEMS gyroscope and an electronic product. The gyroscope comprises: a substrate, and an X / Y proof mass, Z proof masses, driving structures and Z decoupling masses that are fixed on the substrate; the X / Y proof mass is arranged around outer sides of the Z proof masses, the driving structures and the Z decoupling masses; the Z proof masses are oppositely arranged in an x-axis direction; the driving structures are oppositely arranged at outer sides of the Z proof masses in the x-axis direction; and the Z decoupling masses are oppositely arranged at inner sides of the Z proof masses in the x-axis direction. The X / Y proof mass is elastically connected to the driving structures adjacent thereto, the Z proof masses are elastically connected to the driving structures adjacent thereto, and the Z decoupling masses are elastically connected to the Z proof masses adjacent thereto. The gyroscope improves the Coriolis conversion rate of the X / Y proof mass, maximizes the utilization of the chip area, reduces chip size and cost, and reduces coupling errors and quadrature errors, thereby improving sensing accuracy.

The invention discloses an image sensing chip board-level packaging structure and a manufacturing method thereof.The packaging structure comprises a cofferdam type chip unit, the cofferdam type chip unit comprises a transparent substrate, a cofferdam structure and an image sensing chip, the front face of the image sensing chip is provided with a photosensitive area and a bonding pad, the transparent substrate covers the photosensitive area, and the cofferdam structure covers the bonding pad; a cofferdam structure is arranged between the transparent substrate and the image sensing chip, and the cofferdam structure surrounds the photosensitive area to form a closed area; the plastic package body wraps the side surface and the back surface of the cofferdam type chip unit; the first rewiring layer is arranged on one side, close to the front surface of the image sensing chip, of the plastic package body and is electrically connected with a bonding pad of the image sensing chip; the second rewiring layer penetrates through the plastic package body and is electrically connected with the first rewiring layer; and the external interconnection structure is electrically connected with the second rewiring layer. The packaging structure has excellent electrical quality and reliability, the packaging size is larger than the size of a bare chip, and the problem that the heat dissipation capacity is limited due to miniaturization of wafer-level packaging can be solved.

An inertial sensor and a method therefor. The inertial sensor includes: a first substrate; a medium layer stacked on the first substrate; a first electric-conductive layer stacked on the medium layer, first openings being formed in the first electric-conductive layer and spaced from one another; second electric-conductive layers being bonded to the first electric-conductive layer through bonding structures, a gap being formed between adjacent second electric-conductive layers, which are connected to each other by a connection part, and second openings being formed in each of the second electric-conductive layers and spaced from one another; and a second substrate covering the first substrate, a closed space being formed between the second substrate and the first substrate. Compared with a traditional single-layer structure, the die size is reduced, the manufacturing cost is reduced, and the integration of device into portable consumer applications is improved, and XY axis sensitivity is improved.

The invention relates to the technical field of packaging tests, in particular to a test method and system for simulating the filling effect of an adhesive on a BGA chip, and the method comprises the following steps: the BGA chip filling test method comprises the steps: obtaining a chip size and an image sample, setting adhesive spraying parameters, extracting boundary pixels, collecting a fitting image, and evaluating the stability; and injecting simulation colloid, extracting a propulsion contour, and counting a filling image to generate an effect overview. According to the method, a structural boundary image set is constructed by extracting packaging design drawing parameters, glue spraying, attaching and glue injection operations in a simulation environment are realized in combination with an image recognition and path judgment mode, a glue propelling state and boundary changes are continuously recorded by using an image frame sequence, and traditional slice observation is replaced by a whole-process image recognition means. And material consumption and slicing errors are avoided, the test efficiency and controllability are improved, the precision and adaptability of filling process verification are enhanced, and the limitations of evaluation result lagging and high operation dependence in the prior art are improved.

A wafer structure is disclosed comprising a top silicon layer with a polished surface, an oxide layer selectively removed in defined regions, and a bottom silicon layer. Selective oxide removal improves dicing, prevents small molecule ingress, and enhances MEMS device release and performance. The invention addresses challenges of conventional silicon-on-insulator (SOI) wafers, including jagged edges, particle generation during stealth dicing, slow and uncontrolled under-etch rates, and high resistive losses in radio frequency (RF) applications due to parasitic surface conduction. Patterning the oxide layer enables precise MEMS structure release, reduces die size, and improves RF isolation. The wafer structure is suitable for high-speed electronics, RF analog circuits, and MEMS devices such as resonators, accelerometers, and waveguides, offering improved manufacturability and device reliability.

The invention discloses a Micro-OLED (Organic Light Emitting Diode) chip packaging structure, a Micro-OLED chip packaging method and a Micro-OLED display device. The packaging structure comprises a semiconductor wafer which is provided with a conductive through hole penetrating to a metal bonding pad on the front surface of the semiconductor wafer; the plurality of metal bumps are formed on the back surface of the semiconductor wafer and are electrically connected with the metal bonding pads on the front surface through the conductive through holes and the metal rewiring layer on the back surface; the Micro-OLED light emitting layer is formed on the front surface of the semiconductor wafer; and the transparent cover plate is bonded with the front surface of the semiconductor wafer through a supporting wall. According to the invention, the wafer-level chip size packaging process sequence of the Micro-OLED is optimized as follows: the through holes and the salient points are firstly manufactured on the back surface, and then the OLED is manufactured on the front surface. According to the method, the metal bonding pads are allowed to be led out from the two sides, three sides or four sides of the chip, and particularly, the large-current power supply / ground bonding pads are arranged at the four corners of the chip, so that the internal current distribution of the chip is remarkably optimized, the IR voltage drop is reduced, and thinner and smaller Micro-OLED wafer-level packaging with better electrical performance is realized.

The utility model belongs to the technical field of micro electro mechanical systems (MEMS), and particularly relates to a large-capacitance capacitive chip structure. The utility model provides a large-capacitance capacitive chip structure with a small chip size. The utility model comprises a first pole plate (01), and is characterized in that the upper end face of the first pole plate (01) is provided with a groove (61), the upper end face of the first pole plate (01) is provided with a first insulating medium layer (41), and the upper end face of the first insulating medium layer (41) is provided with a second pole plate (02).

A microelectronic device includes a die with input / output (I / O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I / O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I / O terminals, and a head contacting the column at an opposite end of the column from the I / O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

The invention provides a high-speed sorting machine with a wafer picking and overturning function for wafer loading type chip carrier plates and a working method. The high-speed sorting machine comprises a ring box loading and unloading carrying table; ring is carried out on the ring carrying platform; a ring clamping device; the material sheet jacking device is used for jacking the material sheet; a positioning camera; the first transfer flying shuttle and the second transfer flying shuttle are used for conveying ring rings; the single-suction-nozzle transferring device is used for sucking the material sheets; the multi-suction-nozzle overturning device is used for overturning the material sheets; the multi-suction-nozzle transferring device is used for sucking and transferring the material sheets; a tray transfer device; an empty tray loading bin; a tray bin loading and unloading device; the invention discloses a tray grabbing and transferring device. Through the film stretching assembly and the ejector pin assembly, the chip carrier plate can be accurately ejected out; the overturning mechanism is designed in the rear section of the action process, the material sheets are transferred through the double-shuttle-car mechanism, the sheet picking step and the overturning / sorting step are connected, the overturning mechanism is compatible with multiple chip sizes and compatible with the overturning action mode and the non-overturning action mode, production is efficient, layout is compact, and cost is reduced.

The invention provides a three-dimensional chip packaging structure and a manufacturing method, and relates to the technical field of integrated circuit manufacturing. The display device at least comprises a first substrate; the second substrate is arranged on the first substrate, and an accommodating space is formed between the second substrate and the first substrate; and the chip stacking structure is arranged in the accommodating space between the first substrate and the second substrate, and the chip stacking structure is electrically connected with the second substrate and the first substrate. According to the invention, the integrated three-dimensional integration of multiple chips can be realized, the integration level of the transistor and the function unit is obviously improved, the interconnection density and the space utilization rate are optimized, the problems of insufficient interconnection density, bottleneck of electrical interconnection performance and the like of the traditional packaging are solved, and the packaging efficiency is improved. The chip size is reduced, the data transmission rate and the overall efficiency of the system are effectively improved, and high-speed and low-delay data interaction is achieved.

The invention provides a memory device. The memory device includes: a substrate; a plurality of memory arrays formed of stacked bodies disposed on the substrate; and a step structure provided between the plurality of memory arrays, in which first dummy pillars (11, 21) that do not function as memory cells and penetrate the plurality of dielectric layers and the conductive layers are provided at edges of the stack, and second dummy pillars (12, 22) adjacent to the first dummy pillars (11, 21) are provided in the step structure. The second dummy pillars (12, 22) are covered by a filler filled in the stepped structure. According to the invention, more pseudo columns are introduced into the step structure, so that the physical bending and displacement of the effective memory array caused by stress can be reduced under the condition of not influencing the size of the memory chip, thereby improving the yield and reliability in the vertical direction.

The invention relates to the technical field of semiconductors, in particular to a surface acoustic wave resonance device, which comprises a substrate comprising a piezoelectric layer; the interdigital electrode is located on the piezoelectric layer, and the interdigital electrode sequentially comprises a first bus, a first gap part, an overlapping part, a second gap part and a second bus in the first direction; the piezoelectric layer sequentially comprises a first part, a first failure part, an effective part, a second failure part and a second part in the first direction, and the electromechanical coupling effect of the effective part is effective; the first bus is located on the first portion, the first gap portion is located on the first failure portion, the overlapping portion is located on the effective portion, the second gap portion is located on the second failure portion, and the second bus is located on the second portion. On the premise of not obviously influencing insertion loss, power tolerance and chip size, high-order nonlinearity, such as cubic nonlinearity, caused by electromechanical coupling outside a resonance area is effectively inhibited. In addition, the failure part extends to the bus, so that gap mode can be effectively inhibited.

This invention relates to the field of LED packaging technology, specifically to an LED packaging structure with same-side die bonding. Multiple first and second chips are respectively disposed in a first mounting area and a second mounting area on opposite sides of a substrate, and electrical connections are achieved using a circuit layer. This avoids the limitation on the size of the first chip that can be mounted when the first and second chips are arranged on the same side of the substrate, as is the case with traditional methods. By concentrating multiple first chips used for light mixing in the first mounting area on the same side of the substrate, the light-emitting area is more concentrated. Simultaneously, the wire bonding distance is significantly shortened, the number of wires is reduced, and sufficient space is freed up to install larger-sized light-emitting chips, thereby effectively improving the overall brightness. It also avoids the light dispersion phenomenon caused by the mixing of chips and ICs in traditional solutions. Combined with short-pitch circuit connections, it improves the mixing consistency of different colors of light, further enhancing the electrical reliability and optical performance of the packaging structure.

The application provides a scanning and shooting device and a shooting method for a semiconductor chip, relates to the technical field of semiconductor chip detection, and comprises a controller, a base, a gantry slidably connected to the base, and a sliding seat slidably connected to the gantry. The sliding seat is slidably connected to the base along a vertical direction. The mounting seat is driven to lift by a servo cylinder. The camera is fixed on the mounting seat. The distance measuring sensor is arranged on the sliding seat. The distance measuring sensor is electrically connected to the controller. The camera and the distance measuring sensor are both arranged downward. The distance measuring sensor is located on the left side or the right side of the camera. In the shooting process, the camera is automatically lifted to avoid the problem of near large and far small, so that the chip size in the image remains accurate, the accuracy of image recognition is improved, the chip picture in the zooming process is avoided to be shot, image errors are avoided, and subsequent image processing and splicing are facilitated. The lifting of the camera is adapted to the mechanical and electrical response time, invalid travel is avoided, and efficiency is improved.

The present invention provides a resin composition for wafer-level chip-size package type semiconductor devices that can form a coating film with good high-frequency characteristics, minimal thickness variation, and reduced likelihood of semiconductor substrate warping, as well as a semiconductor device using the same and a method for manufacturing a semiconductor device. [Solution] A resin composition for wafer-level chip-size package type semiconductor device, comprising (A) a modified polyphenylene ether resin having an unsaturated double bond at its terminus, and (B) an elastomer having a butadiene skeleton, and optionally (C) a solvent; a semiconductor device using the same; and a method for manufacturing a semiconductor device.

The invention discloses a radio frequency receiver and a method for receiving a radio frequency input signal. The radio frequency receiver comprises a radiating element, a chip and a phase shift circuit. The radiating element is configured to receive a radio frequency input signal to generate a plurality of electrical signals. The chip includes an amplifier circuit. The amplifier circuit is configured to receive a plurality of phase-shifted signals from a plurality of input terminals, respectively, and amplify the plurality of phase-shifted signals to generate a radio frequency output signal. The phase shift circuit is located outside the chip and is coupled to the radiating element and the plurality of input terminals. The phase shift circuit is used for performing phase shift operation on the plurality of electric signals and generating the plurality of phase shift signals according to the plurality of electric signals. The phase shift circuit and the radiating element are formed on the same substrate. According to the radio frequency receiver, the size of a required chip can be reduced, the production cost is reduced, and the signal loss is reduced.

The invention relates to the technical field of semiconductor die bonding, in particular to a semiconductor die bonding device capable of reducing grabbing warping probability and optimizing truss architecture, which comprises a bottom truss, a side truss is fixedly connected to the rear side of the top of the bottom truss, a bearing table is arranged at the top of the bottom truss, and a binding head frame is fixedly connected to the inner side of the side truss through bolts. A motor mounting seat is arranged on the front side of the binding head frame, a driving servo motor is mounted at the bottom of the motor mounting seat, a grabbing arm is fixedly connected to the output end of the driving servo motor, and a suction nozzle assembly is fixedly connected to the front side of the grabbing arm. According to the semiconductor die bonding device capable of reducing the grabbing warping probability and optimizing the truss framework, the bendable suction nozzle assembly is matched with the multiple evenly-distributed suction cups and the vacuum system for synchronous pressure supply, the suction cups can be attached to the surface in a self-adaptive mode according to the chip size, multi-point even adsorption is achieved, and the grabbing warping probability is reduced. Warping caused by overlarge center stress and insufficient edge vacuum of a traditional single suction cup is avoided.

The present invention provides an optical element that enables a gas sensor with high tolerance to fluctuations while increasing the effective light-receiving or light-emitting surface area without increasing the chip size. [Solution] The optical element has an internal wiring section (30) that electrically connects a first contact electrode section (24) of one unit element and a second contact electrode section (25) of another unit element, and a second region (212), an active layer (22), and a second conductivity semiconductor layer (23) that constitute a mesa structure, and a pad electrode (40) that is arranged to cover a plurality of unit elements (20) and electrically connected to at least one of the first contact electrode section (24) and the second contact electrode section (25), and a first insulating section (50) that is arranged between the pad electrode (40) and the side surface of the mesa structure and the first region (211) of the first conductivity semiconductor layer (21), and the diameter of the circle that circumscribes the region in contact with the pad electrode and the connection section is 15% or more of the length of the short side of the substrate.

A wafer level package (1) comprises: a lower substrate (22); an upper substrate (23) facing the lower substrate (22); a plurality of elements (20) arranged in an array, the plurality of elements (20) being formed on at least one of the lower substrate (22) and the upper substrate (23), or being mounted between the lower substrate (22) and the upper substrate (23); a first eutectic material f formed on the surface of the lower substrate (22) facing the upper substrate (23); a second eutectic material f' formed on the surface of the upper substrate (23) facing the lower substrate (22); a plurality of frame bodies (24) surrounding the plurality of elements (20) respectively; and connection parts (26) that connect parts of the frame bodies (24) respectively surrounding adjacent elements (20) from among the plurality of elements (20). The frame bodies (24) and the connection parts (26) are formed by eutectically bonding the first eutectic material f and the second eutectic material f'. The eutectic material ratio between the first eutectic material f and the second eutectic material f' is different between at least the frame bodies (24) and a part of the connection parts (26).

The invention discloses a radio frequency receiver and a method for receiving a radio frequency input signal. The radio frequency receiver comprises a radiating element, a chip and a phase shift circuit. The radiating element is configured to receive a radio frequency input signal to generate a plurality of electrical signals. The chip includes an amplifier circuit. The amplifier circuit is configured to receive a plurality of phase-shifted signals from a plurality of input terminals, respectively, and amplify the plurality of phase-shifted signals to generate a radio frequency output signal. The phase shift circuit is located outside the chip and is coupled to the radiating element and the plurality of input terminals. The phase shift circuit is used for performing phase shift operation on the plurality of electric signals and generating the plurality of phase shift signals according to the plurality of electric signals. The phase shift circuit and the radiating element are formed on the same substrate. According to the radio frequency receiver, the size of a required chip can be reduced, the production cost is reduced, and the signal loss is reduced.

The utility model is mainly used for the back section packaging process of a semiconductor chip, and relates to an integrally formed semiconductor packaging fixing clamp, which comprises a first force arm, a second force arm and an elastic part which are integrally formed, and the elastic part extends inwards from the end parts of the first force arm and the second force arm to form an arc-shaped structure. The end parts of the first force arm and the second force arm are opposite to form an opening part which is used for clamping a semiconductor to be packaged. Therefore, the semiconductor to be packaged is clamped through the first force arm, the second force arm and the elastic part, a complex jig and a clamp do not need to be customized according to the size of a chip, the chip cover plate can have constant clamping force through the first force arm and the second force arm, production is facilitated, and use is easy.

The application provides a paper frame device compatible with the size of a tube core and a thermal printer, comprising two paper frame blocks, a first spring and a sliding block, the paper frame block is provided with a receiving protrusion column, the outer periphery of the receiving protrusion column is provided with a first receiving peripheral wall, the paper frame block is provided with a ring groove at the outer periphery of the first receiving peripheral wall, the sliding block is provided with a sliding hole, the outer periphery of the sliding block is provided with a second receiving peripheral wall, the receiving protrusion column passes through the sliding hole, by arranging the paper frame device in a paper bin, the paper frame device has a sliding block which can move in the paper width direction, in a first receiving state, the sliding block is retracted into the ring groove, the second receiving peripheral wall is retracted into the ring groove, and then the first receiving peripheral wall is used for receiving a tube core with a smaller diameter, in a second receiving state, the sliding block is extended towards a paper clamping position, and the second receiving peripheral wall is used for receiving a tube core with a larger diameter, so that the support for tube cores with different diameters and sizes can be realized.

The application relates to the technical field of semiconductor production equipment, in particular to an electronic component packaging and detecting integrated machine which comprises a taping machine body, an expansion structure, a resisting structure, a driving structure, a detecting structure, a collecting structure, a first conveying device, a three-dimensional adjusting device, a second conveying device, a unwinding roller and a taking and placing device; the resisting structure is arranged to facilitate quick fixing of a winding drum on the unwinding roller, improves the winding drum replacement efficiency, and further improves the processing efficiency; the detecting structure is arranged to facilitate chip overturning and hollow tube driving chip rotation, can detect each position of the chip, improves the detection precision, detects unqualified chips, adjusts the position of the hollow tube by the three-dimensional adjusting device, the expansion structure is arranged to facilitate expansion of a carrier tape groove, facilitates accurate chip placement, avoids chip size mismatching with the groove from causing jamming or placement deviation, improves the placement efficiency and packaging quality, and the driving structure facilitates driving of the mounting frame to continuously drive the expansion plate to move up and down.

The embodiment of the invention discloses a capacitance sensing interface circuit and a capacitance sensing chip, through setting that the voltage output by an excitation signal output module is adjustable, when the capacitance value of a compensation capacitor connected to a compensation module cannot meet the compensation requirement of an offset capacitor, the capacitance value of the offset capacitor can be adjusted by adjusting the amplitude of the voltage output by the excitation signal output module; therefore, the area of the compensation module can be reduced, the compensation of the offset capacitance can be realized through the smaller compensation capacitance, and the size of a chip can be reduced.

The semiconductor device (1) is a chip-scale semiconductor device (1) that is square in plan view, and is provided with a semiconductor layer (40), a vertical MOS transistor (10) formed on the semiconductor layer (40), and a Schottky barrier diode (20) in which the semiconductor layer (40) functions as an anode or a cathode. A first pad (51), a second pad (52), a third pad (53), and a fourth pad (54) are provided on the upper surface of a semiconductor device (1), and the center of the first pad (51) and the center of the third pad (53) are located on one diagonal line of the semiconductor device (1) in a plan view of the semiconductor device (1). The center of the second pad (52) and the center of the fourth pad (54) are located on the other diagonal line of the semiconductor device (1), and the first pad (51), the second pad (52), the third pad (53), and the fourth pad (54) are circles having the same diameter.

The utility model discloses an LED die bonder die bonding clamp, and relates to the technical field of die bonders, the LED die bonder die bonding clamp comprises a clamp main body, a mounting plate and a fixing block, and the upper side of the clamp main body is provided with a placing groove; the mounting plates are symmetrically mounted above the clamp main body, upward elastic mechanisms are mounted between the bottoms of the two groups of mounting plates and the upper side of the clamp main body, sliding grooves are formed in the outer parts of the mounting plates, sliding blocks are slidably connected into the sliding grooves, a connecting plate is fixedly connected between the upper sides of the two groups of sliding blocks, and a mounting rod is fixedly connected between the lower sides of the two groups of sliding blocks; a pressing mechanism is mounted at the bottom of the mounting rod; and a pull-down mechanism is mounted in the clamp main body. According to the device, the distance between the positioning strips is adjusted through manual sliding to adapt to the size of a chip, a motor is matched with a winding pull rope to drive the symmetrical mounting plates to press downwards, pressure is rapidly released through elastic reset of springs, one-key clamping and loosening are achieved, the repeated adjusting step of a traditional clamp is simplified, and the positioning efficiency and stability of the chips of multiple sizes are improved.

The invention discloses a radio frequency receiver and a method for receiving a radio frequency input signal. The radio frequency receiver comprises a radiating element, a chip and a phase shift circuit. The radiating element is configured to receive a radio frequency input signal to generate a plurality of electrical signals. The chip includes an amplifier circuit. The amplifier circuit is configured to receive a plurality of phase-shifted signals from a plurality of input terminals, respectively, and amplify the plurality of phase-shifted signals to generate a radio frequency output signal. The phase shift circuit is located outside the chip and is coupled to the radiating element and the plurality of input terminals. The phase shift circuit is used for performing phase shift operation on the plurality of electric signals and generating the plurality of phase shift signals according to the plurality of electric signals. The phase shift circuit and the radiating element are formed on the same substrate. According to the radio frequency receiver, the size of a required chip can be reduced, the production cost is reduced, and the signal loss is reduced.

The application discloses a light emitting device array image correction method and device and a storage medium, which are used for converting irregular light emitting device arrays into array images with fixed repeating periods so as to facilitate defect detection and improve defect detection efficiency. The application comprises the following steps: acquiring a chip array image shot on a target screen, and acquiring coordinate positions of the chips in the target screen and row and column numbers of the chips; constructing a chip coordinate matrix according to the coordinate positions of the chips; calculating row and column spacings between the chips according to the coordinate positions of the chips and preset chip size parameters; constructing theoretical dot array coordinates according to the preset chip size parameters, the row and column numbers of the chips and the row and column spacings between the chips; dividing the chip coordinate matrix into a first area coordinate group; calculating regional transformation matrices according to the theoretical dot array coordinates and the first area coordinate group; and processing the first area coordinate group according to the regional transformation matrices to obtain a corrected image.

The utility model provides a film coating clamp suitable for various chip sizes, which relates to the technical field of chip film coating clamps and comprises a mounting substrate, and two support plates are fixedly connected to the upper surface, close to two ends, of the mounting substrate. During use, a chip is horizontally placed between the two clamping plates, the output end of the motor drives the two-way lead screw to rotate, the two adjusting plates are close to each other, the opposite surfaces of the two clamping plates are attached to the outer surface of the chip, the two-way lead screw continues to rotate, the two adjusting plates extrude the springs and the dampers, and the two dampers and the springs synchronously compress the specified stroke. The clamping device absorbs kinetic energy, provides stable clamping force for the chip, prevents the clamping force from being too high or too low, guarantees the clamping effect, prevents the chip from being damaged by the too high clamping force or prevents the chip from falling off during operation due to the too low clamping force, can be suitable for chips of different specifications, does not need additional adjustment and correction, and improves the working efficiency. And the processing efficiency and the processing quality of products are ensured.

The utility model discloses a Mini LED sorting jig which comprises a jig body, a sorting opening formed in the middle of the jig body and a plurality of positioning blocks arranged on the jig body. The multiple positioning blocks are arranged on the periphery of the sorting opening in the circumferential direction, and a mounting area for containing sorted grade bearing iron rings is defined based on the multiple positioning blocks. According to the sorting jig for the upper iron rings, the positioning blocks and the magnetic attraction blocks are arranged on the sorting jig for the upper iron rings, so that the sorting jig for the upper iron rings can meet the assembling requirement of sorting equipment, meanwhile, the assembling requirement of sorted grade bearing iron rings can be met, and the upper iron rings and the sorted grade bearing iron rings can be combined for use; and the convenience of replacing the chip sorting jig according to the size of the chip is improved, so that the sorting efficiency and the sorting reliability of the sorting equipment on the Mini LED chips are improved.