237 results about "Chip size" patented technology

Embodiments of the present disclosure provide a fully decoupled three-axis MEMS gyroscope and an electronic product. The gyroscope comprises: a substrate, and an X / Y proof mass, Z proof masses, driving structures and Z decoupling masses that are fixed on the substrate; the X / Y proof mass is arranged around outer sides of the Z proof masses, the driving structures and the Z decoupling masses; the Z proof masses are oppositely arranged in an x-axis direction; the driving structures are oppositely arranged at outer sides of the Z proof masses in the x-axis direction; and the Z decoupling masses are oppositely arranged at inner sides of the Z proof masses in the x-axis direction. The X / Y proof mass is elastically connected to the driving structures adjacent thereto, the Z proof masses are elastically connected to the driving structures adjacent thereto, and the Z decoupling masses are elastically connected to the Z proof masses adjacent thereto. The gyroscope improves the Coriolis conversion rate of the X / Y proof mass, maximizes the utilization of the chip area, reduces chip size and cost, and reduces coupling errors and quadrature errors, thereby improving sensing accuracy.

The invention provides an FPVA biochip layout method considering reagent type difference in unit multiplexing, which comprises the following steps of: modeling a biochip layout task as a Markov decision process: according to the size of an input FPVA chip, the dependency relationship of each operation in a biochemical reaction sequence diagram, the reagent type contained in each operation and a binding scheduling scheme, determining the FPVA biochip layout task; initializing an FPVA mesh model and defining a state space, an action space and a reward function; wherein the reward function is set according to the total unit multiplexing complexity of the current layout scheme, the legality of the current component layout and the distance between the component and the center point of the FPVA chip; and finally, completing the FPVA biochip layout through the dual deep Q network based on a Markov decision process. By designing a reward function, the unit multiplexing complexity is minimized, and the distance between components containing the same type of reagents is reduced, so that the purposes of minimizing the cross contamination degree of a final layout scheme, the total length of a fluid transportation path and the bioassay completion time are achieved.

The invention relates to an MEMS-CMOS device vertical interconnection integrated packaging preparation method, which comprises the following steps of: processing a TSV (Through Silicon Via) on a first silicon wafer (3), and filling crystalline silicon (2a); respectively processing a CMOS circuit layer and an RDL layer on the first silicon wafer, and processing a germanium bonding point (8) on the other surface of the first silicon wafer; a second SOI silicon wafer (10) and a third SOI silicon wafer (11) are fused and bonded to form a cavity (9), an aluminum / titanium / aluminum bonding point (12) is prepared on the third silicon wafer, an MEMS movable microstructure (13) is prepared on the third silicon wafer, the metal aluminum / titanium / aluminum bonding point and the MEMS movable microstructure are electrically connected, and the aluminum-germanium bonding point of the first silicon wafer and the aluminum-germanium bonding point of the third silicon wafer are subjected to eutectic bonding. According to the invention, the size of an integrated packaging chip of the MEMS device and the CMOS processing circuit is greatly reduced, and meanwhile, the RDL structure can realize wafer-level bonding packaging without considering the types, layout and size of the MEMS device and the CMOS circuit.

The invention discloses a power supply self-adaptive active temperature compensation attenuator which comprises a radio frequency attenuation circuit, a positive voltage temperature compensation driving circuit and a power supply self-adaptive adjusting circuit. The radio frequency attenuation circuit is connected in series in a signal link and comprises a transistor and a resistor; the positive voltage temperature compensation driving circuit comprises a transistor, a diode and a resistor. The driving transistor outputs a voltage playing a temperature compensation role by utilizing the temperature change of the electrical characteristic of the diode, and outputs the voltage to the radio frequency attenuation circuit in a voltage division manner; the power supply self-adaptive adjusting circuit comprises a resistor and a diode, the resistor and the diode adjust the grid voltage of a transistor in the driving circuit when the power supply fluctuates, the output voltage of the whole driving circuit is adjusted, and the influence of power supply fluctuation on the driving circuit is counteracted. Positive voltage is used for working, the structure is novel, the chip size is small, the temperature compensation characteristic is good, and the application range is wide; and the power supply interference resistance is good.

The invention discloses an image sensing chip board-level packaging structure and a manufacturing method thereof.The packaging structure comprises a cofferdam type chip unit, the cofferdam type chip unit comprises a transparent substrate, a cofferdam structure and an image sensing chip, the front face of the image sensing chip is provided with a photosensitive area and a bonding pad, the transparent substrate covers the photosensitive area, and the cofferdam structure covers the bonding pad; a cofferdam structure is arranged between the transparent substrate and the image sensing chip, and the cofferdam structure surrounds the photosensitive area to form a closed area; the plastic package body wraps the side surface and the back surface of the cofferdam type chip unit; the first rewiring layer is arranged on one side, close to the front surface of the image sensing chip, of the plastic package body and is electrically connected with a bonding pad of the image sensing chip; the second rewiring layer penetrates through the plastic package body and is electrically connected with the first rewiring layer; and the external interconnection structure is electrically connected with the second rewiring layer. The packaging structure has excellent electrical quality and reliability, the packaging size is larger than the size of a bare chip, and the problem that the heat dissipation capacity is limited due to miniaturization of wafer-level packaging can be solved.

The utility model belongs to the technical field of chip sealing detection, and particularly relates to a multi-row rotatable suction nozzle module which is applied to chip detection and packaging equipment and is used for sucking chips, and the multi-row rotatable suction nozzle module is adjustable in spacing. The suction nozzle lifting module is used for driving a suction nozzle rotating module to move in the Z-axis direction, and the suction nozzle rotating module is used for driving the multi-suction-nozzle module to rotate around the Z axis; wherein the multi-suction-nozzle module is provided with a plurality of air cylinders and suction nozzles which are independently controlled, multiple or single chips can be sucked at a time, and actions of sucking, moving, steering, storing and the like are achieved; and meanwhile, the distance between the suction nozzles can be automatically adjusted according to different sizes of chips and different storage distances, so that application scenes such as TRAY disc material taking and placing, sorting and placing and taping chip material taking and placing are met, and the chip taking and placing device has the advantages of being compact in structure, diverse in function, convenient to adjust, high in efficiency, wide in compatible range, diverse in application scenes and the like.

An inertial sensor and a method therefor. The inertial sensor includes: a first substrate; a medium layer stacked on the first substrate; a first electric-conductive layer stacked on the medium layer, first openings being formed in the first electric-conductive layer and spaced from one another; second electric-conductive layers being bonded to the first electric-conductive layer through bonding structures, a gap being formed between adjacent second electric-conductive layers, which are connected to each other by a connection part, and second openings being formed in each of the second electric-conductive layers and spaced from one another; and a second substrate covering the first substrate, a closed space being formed between the second substrate and the first substrate. Compared with a traditional single-layer structure, the die size is reduced, the manufacturing cost is reduced, and the integration of device into portable consumer applications is improved, and XY axis sensitivity is improved.

The invention relates to the technical field of packaging tests, in particular to a test method and system for simulating the filling effect of an adhesive on a BGA chip, and the method comprises the following steps: the BGA chip filling test method comprises the steps: obtaining a chip size and an image sample, setting adhesive spraying parameters, extracting boundary pixels, collecting a fitting image, and evaluating the stability; and injecting simulation colloid, extracting a propulsion contour, and counting a filling image to generate an effect overview. According to the method, a structural boundary image set is constructed by extracting packaging design drawing parameters, glue spraying, attaching and glue injection operations in a simulation environment are realized in combination with an image recognition and path judgment mode, a glue propelling state and boundary changes are continuously recorded by using an image frame sequence, and traditional slice observation is replaced by a whole-process image recognition means. And material consumption and slicing errors are avoided, the test efficiency and controllability are improved, the precision and adaptability of filling process verification are enhanced, and the limitations of evaluation result lagging and high operation dependence in the prior art are improved.

The invention discloses a ball mounting device and method suitable for BGAs of different sizes and shapes, and belongs to the technical field of electronic component packaging and maintenance, and the device comprises a bottom base which is provided with a vacuum adsorption hole in the center and is used for adsorbing and fixing a BGA chip; the plurality of groups of replaceable positioning clamping pins are fixed on the bottom-layer base and are used for enclosing a positioning frame matched with the BGA chip in size; the middle-layer limiting frame is placed on the bottom-layer base, is used for bearing a ball mounting steel mesh and is provided with a positioning magnet for adsorbing and fixing the ball mounting steel mesh; and the top layer fixing frame is connected with the middle layer limiting frame, is provided with a height adjusting screw, and is used for finely adjusting the height difference between the bonding pad of the BGA chip and the ball mounting steel mesh. The method can effectively solve the problems of poor flexibility, high cost and low efficiency caused by a special jig in the traditional ball mounting process, has excellent tolerance fault-tolerant capability, and can meet the ball mounting requirements of BGA chips with different sizes and different shapes.

The invention provides a working mode reconfigurable power division chip circuit structure and a working method thereof. The circuit structure comprises an input port tap, two output port taps, a three-wire coupling spiral coil, a grounding pole and two control switches. One input port tap is connected with a middle coil of the three-wire coupling spiral coil to serve as an incident signal input port; the two output port taps are connected with two ends of an outer side coil of the three-wire coupling spiral coil to serve as output signal output ports; the two ends of the grounding pole are connected between the tail ends of the middle coils of the three-wire coupling spiral coils through the control switches respectively. The two control switches are used for switching the working mode of the working mode reconfigurable power division chip circuit structure. According to the power divider, the connection state of the three-wire coupling spiral coil and the grounding pole is changed by switching the on-off state of the control switch, switching of two working modes of power division and balun is achieved in the same compact circuit structure, and efficient utilization of the chip size is achieved.

A wafer structure is disclosed comprising a top silicon layer with a polished surface, an oxide layer selectively removed in defined regions, and a bottom silicon layer. Selective oxide removal improves dicing, prevents small molecule ingress, and enhances MEMS device release and performance. The invention addresses challenges of conventional silicon-on-insulator (SOI) wafers, including jagged edges, particle generation during stealth dicing, slow and uncontrolled under-etch rates, and high resistive losses in radio frequency (RF) applications due to parasitic surface conduction. Patterning the oxide layer enables precise MEMS structure release, reduces die size, and improves RF isolation. The wafer structure is suitable for high-speed electronics, RF analog circuits, and MEMS devices such as resonators, accelerometers, and waveguides, offering improved manufacturability and device reliability.

The invention discloses a Micro-OLED (Organic Light Emitting Diode) chip packaging structure, a Micro-OLED chip packaging method and a Micro-OLED display device. The packaging structure comprises a semiconductor wafer which is provided with a conductive through hole penetrating to a metal bonding pad on the front surface of the semiconductor wafer; the plurality of metal bumps are formed on the back surface of the semiconductor wafer and are electrically connected with the metal bonding pads on the front surface through the conductive through holes and the metal rewiring layer on the back surface; the Micro-OLED light emitting layer is formed on the front surface of the semiconductor wafer; and the transparent cover plate is bonded with the front surface of the semiconductor wafer through a supporting wall. According to the invention, the wafer-level chip size packaging process sequence of the Micro-OLED is optimized as follows: the through holes and the salient points are firstly manufactured on the back surface, and then the OLED is manufactured on the front surface. According to the method, the metal bonding pads are allowed to be led out from the two sides, three sides or four sides of the chip, and particularly, the large-current power supply / ground bonding pads are arranged at the four corners of the chip, so that the internal current distribution of the chip is remarkably optimized, the IR voltage drop is reduced, and thinner and smaller Micro-OLED wafer-level packaging with better electrical performance is realized.

The utility model belongs to the technical field of micro electro mechanical systems (MEMS), and particularly relates to a large-capacitance capacitive chip structure. The utility model provides a large-capacitance capacitive chip structure with a small chip size. The utility model comprises a first pole plate (01), and is characterized in that the upper end face of the first pole plate (01) is provided with a groove (61), the upper end face of the first pole plate (01) is provided with a first insulating medium layer (41), and the upper end face of the first insulating medium layer (41) is provided with a second pole plate (02).

The present disclosure provides a semiconductor device and a control method thereof. The semiconductor device comprises a detection module, a chip carrying module and a control unit. The control unit is electrically connected with the detection module and the chip carrying module. The control unit is configured to generate a first control signal according to a geometric parameter collected by the detection module. The chip carrying module is responsive to the first control signal and adjusts a clamping space of a first clamping mechanism in the chip carrying module along a first direction so as to adapt the clamping space to the geometric size of the chip. In the present disclosure, the control unit can adjust the clamping space in the chip carrying module according to the geometric parameter detected by the detection module, thereby solving the problems of high tool procurement cost, high storage cost and long downtime for replacing tools caused by the fixed adaptation mode of "one chip size corresponds to one tool" in the related art.

The invention discloses a method and a device for correcting a light-emitting device array image and a storage medium, which are used for converting an irregular light-emitting device array into an array image with a fixed repetition period so as to facilitate defect detection and improve the defect detection efficiency. The method comprises the following steps: acquiring a chip array diagram for shooting a target screen, and acquiring coordinate positions of chips in the target screen and the number of rows and columns of the chips; constructing a chip coordinate matrix according to the coordinate position of the chip; according to the coordinate positions of the chips and preset chip size parameters, the row and column spacing between the chips is obtained through calculation; according to preset chip size parameters, the number of rows and columns of the chips and the row and column spacing between the chips, theoretical dot matrix coordinates are constructed; dividing the chip coordinate matrix into a first area coordinate group; according to the theoretical dot matrix coordinates and the first region coordinate group, performing regional calculation to obtain a region transformation matrix; and processing the first region coordinate group according to the region transformation matrix to obtain a corrected image.

A microelectronic device includes a die with input / output (I / O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I / O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I / O terminals, and a head contacting the column at an opposite end of the column from the I / O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

The invention provides a high-speed sorting machine with a wafer picking and overturning function for wafer loading type chip carrier plates and a working method. The high-speed sorting machine comprises a ring box loading and unloading carrying table; ring is carried out on the ring carrying platform; a ring clamping device; the material sheet jacking device is used for jacking the material sheet; a positioning camera; the first transfer flying shuttle and the second transfer flying shuttle are used for conveying ring rings; the single-suction-nozzle transferring device is used for sucking the material sheets; the multi-suction-nozzle overturning device is used for overturning the material sheets; the multi-suction-nozzle transferring device is used for sucking and transferring the material sheets; a tray transfer device; an empty tray loading bin; a tray bin loading and unloading device; the invention discloses a tray grabbing and transferring device. Through the film stretching assembly and the ejector pin assembly, the chip carrier plate can be accurately ejected out; the overturning mechanism is designed in the rear section of the action process, the material sheets are transferred through the double-shuttle-car mechanism, the sheet picking step and the overturning / sorting step are connected, the overturning mechanism is compatible with multiple chip sizes and compatible with the overturning action mode and the non-overturning action mode, production is efficient, layout is compact, and cost is reduced.

The invention provides a three-dimensional chip packaging structure and a manufacturing method, and relates to the technical field of integrated circuit manufacturing. The display device at least comprises a first substrate; the second substrate is arranged on the first substrate, and an accommodating space is formed between the second substrate and the first substrate; and the chip stacking structure is arranged in the accommodating space between the first substrate and the second substrate, and the chip stacking structure is electrically connected with the second substrate and the first substrate. According to the invention, the integrated three-dimensional integration of multiple chips can be realized, the integration level of the transistor and the function unit is obviously improved, the interconnection density and the space utilization rate are optimized, the problems of insufficient interconnection density, bottleneck of electrical interconnection performance and the like of the traditional packaging are solved, and the packaging efficiency is improved. The chip size is reduced, the data transmission rate and the overall efficiency of the system are effectively improved, and high-speed and low-delay data interaction is achieved.

Embodiments provide a memory device whose chip size is not limited by the size of a peripheral circuit. A memory device of an embodiment has: a first chip; and a second chip disposed on the first chip and attached so as to be in contact with the first chip. The first chip includes: a first peripheral circuit disposed on a first semiconductor substrate; a first memory cell array disposed above the first peripheral circuit; and a first electrode disposed above the first memory cell array. The second chip includes: a second electrode in contact with the first electrode; a second memory cell array disposed above the second electrode; a second peripheral circuit disposed above the second memory cell array; a second semiconductor substrate disposed above the second peripheral circuit; and a pad disposed above the second peripheral circuit and capable of receiving a command and an address from a memory controller. The first peripheral circuit controls either one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad, and the second peripheral circuit controls the other one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad.

The present invention discloses an optical gyroscope integrated chip based on a thin-film lithium niobate photonic integrated platform. The overall structure adopts a hybrid curved waveguide with multiple parts of continuously variable curvature, which reduces the insertion loss caused by the mode field mismatch between the straight waveguide and the curved waveguide at the junction, reduces the excitation of high-order modes, and helps to reduce the overall size of the chip. In addition, the curved waveguide increases the polarization extinction ratio of the chip and filters out quasi-TE 00 The present invention utilizes waveguide mode leakage to achieve single-mode, single-polarization operation of the lithium niobate waveguide. The single-TE mode lithium niobate waveguide on the entire chip, excluding the curved waveguide of the folded modulator and the coupler, forms a waveguide polarizer with a high polarization extinction ratio. This allows on-chip single-mode, single-polarization operation to be achieved without the need for an additional polarizer design, effectively reducing chip complexity, improving chip stability, and reducing chip size.

The invention provides a memory device. The memory device includes: a substrate; a plurality of memory arrays formed of stacked bodies disposed on the substrate; and a step structure provided between the plurality of memory arrays, in which first dummy pillars (11, 21) that do not function as memory cells and penetrate the plurality of dielectric layers and the conductive layers are provided at edges of the stack, and second dummy pillars (12, 22) adjacent to the first dummy pillars (11, 21) are provided in the step structure. The second dummy pillars (12, 22) are covered by a filler filled in the stepped structure. According to the invention, more pseudo columns are introduced into the step structure, so that the physical bending and displacement of the effective memory array caused by stress can be reduced under the condition of not influencing the size of the memory chip, thereby improving the yield and reliability in the vertical direction.

To reduce the chip size of a chip-type electronic component including a capacitor and an inductor. A chip-type electronic component includes a capacitor constituted by a lower electrode pattern, an upper electrode pattern, and an insulating layer, an insulating layer covering the capacitor, and an inductor pattern disposed on the insulating layer. The inductor pattern has a section overlapping the capacitor, whereby an auxiliary capacitor is added. The inductor pattern is thus made to partly overlap the capacitor, so that a larger inductance can be obtained with a small chip size. In addition, characteristics can also be improved by auxiliary capacitance.

The invention relates to the technical field of semiconductors, in particular to a surface acoustic wave resonance device, which comprises a substrate comprising a piezoelectric layer; the interdigital electrode is located on the piezoelectric layer, and the interdigital electrode sequentially comprises a first bus, a first gap part, an overlapping part, a second gap part and a second bus in the first direction; the piezoelectric layer sequentially comprises a first part, a first failure part, an effective part, a second failure part and a second part in the first direction, and the electromechanical coupling effect of the effective part is effective; the first bus is located on the first portion, the first gap portion is located on the first failure portion, the overlapping portion is located on the effective portion, the second gap portion is located on the second failure portion, and the second bus is located on the second portion. On the premise of not obviously influencing insertion loss, power tolerance and chip size, high-order nonlinearity, such as cubic nonlinearity, caused by electromechanical coupling outside a resonance area is effectively inhibited. In addition, the failure part extends to the bus, so that gap mode can be effectively inhibited.

This invention relates to the field of LED packaging technology, specifically to an LED packaging structure with same-side die bonding. Multiple first and second chips are respectively disposed in a first mounting area and a second mounting area on opposite sides of a substrate, and electrical connections are achieved using a circuit layer. This avoids the limitation on the size of the first chip that can be mounted when the first and second chips are arranged on the same side of the substrate, as is the case with traditional methods. By concentrating multiple first chips used for light mixing in the first mounting area on the same side of the substrate, the light-emitting area is more concentrated. Simultaneously, the wire bonding distance is significantly shortened, the number of wires is reduced, and sufficient space is freed up to install larger-sized light-emitting chips, thereby effectively improving the overall brightness. It also avoids the light dispersion phenomenon caused by the mixing of chips and ICs in traditional solutions. Combined with short-pitch circuit connections, it improves the mixing consistency of different colors of light, further enhancing the electrical reliability and optical performance of the packaging structure.

The invention relates to a manufacturing method of an axial low-voltage-drop high-voltage fast-recovery OJ diode. The manufacturing method comprises the steps of material preparation, material surface treatment, packaging treatment, welding, acid pickling, gluing, curing, mold pressing, aging, reflow soldering and secondary aging. According to the method, the ground wafer and the glass passivated and cut chip are used, low-temperature welding is carried out, welding air holes are smaller, forward voltage drop and voltage consistency are better, the problem that the welding air holes of a tunnel furnace are too large is solved, and the forward voltage drop of a high-voltage diode product of over 3000V produced by the method can be reduced by 0.3 V to the minimum and can be reduced by 0.7 * nV (n is the number of rectifier tube chips) to the maximum. Under the same chip size, the switching time of the product can be shorter, the forward voltage drop can be smaller, the chip production cost is greatly reduced, and the gold expansion is reduced by more than 30%-50%.

A flip chip size packaged semiconductor device (1) is provided with: a semiconductor layer (40); a vertical MOS transistor (10) formed in the semiconductor layer (40); a protective film (35); a first wiring electrode (12) connected to a source electrode (13) of the vertical MOS transistor (10); and a second wiring electrode (52) connected to a gate electrode (19) of the vertical MOS transistor (10), a first outer peripheral structure (101) protruding upward of the semiconductor device (1) is formed by sequentially stacking the source electrode (13), the protective film (35), and the first wiring electrode (12) at an outer peripheral portion of the first wiring electrode (12) in a plan view of the semiconductor layer (40), and a second outer peripheral structure (102) protruding upward of the semiconductor device (1) is formed by sequentially stacking the gate electrode (19), the protective film (35), and the second wiring electrode (52) at an outer peripheral portion of the second wiring electrode (52) in the plan view of the semiconductor layer (40).

The application provides a scanning and shooting device and a shooting method for a semiconductor chip, relates to the technical field of semiconductor chip detection, and comprises a controller, a base, a gantry slidably connected to the base, and a sliding seat slidably connected to the gantry. The sliding seat is slidably connected to the base along a vertical direction. The mounting seat is driven to lift by a servo cylinder. The camera is fixed on the mounting seat. The distance measuring sensor is arranged on the sliding seat. The distance measuring sensor is electrically connected to the controller. The camera and the distance measuring sensor are both arranged downward. The distance measuring sensor is located on the left side or the right side of the camera. In the shooting process, the camera is automatically lifted to avoid the problem of near large and far small, so that the chip size in the image remains accurate, the accuracy of image recognition is improved, the chip picture in the zooming process is avoided to be shot, image errors are avoided, and subsequent image processing and splicing are facilitated. The lifting of the camera is adapted to the mechanical and electrical response time, invalid travel is avoided, and efficiency is improved.

The application provides a chip regularizing device, which comprises a mounting base, a horizontal rotation driving part, a regularizing base, a plurality of regularizing components, a transmission rod and a lifting driving part; the horizontal rotation driving part is movably fixed on the mounting base; the regularizing base is movably fixed on the horizontal rotation driving part; the regularizing components are movably fixed on the regularizing base and are arranged around the regularizing base; one end of the transmission rod penetrates through the regularizing base and abuts against the lifting driving part; the other end of the transmission rod is directed to the bottom of the regularizing components; when the transmission rod is lifted under the driving of the lifting driving part, the other end of the transmission rod abuts against the bottom of each regularizing component and pushes each regularizing component apart, so that each regularizing component is away from each other; when the transmission rod falls under the driving of the lifting driving part, each regularizing component is close to each other. The chip regularizing device can complete the large-angle adjustment and fine adjustment of the direction of the chip at one time.

The present invention provides a resin composition for wafer-level chip-size package type semiconductor devices that can form a coating film with good high-frequency characteristics, minimal thickness variation, and reduced likelihood of semiconductor substrate warping, as well as a semiconductor device using the same and a method for manufacturing a semiconductor device. [Solution] A resin composition for wafer-level chip-size package type semiconductor device, comprising (A) a modified polyphenylene ether resin having an unsaturated double bond at its terminus, and (B) an elastomer having a butadiene skeleton, and optionally (C) a solvent; a semiconductor device using the same; and a method for manufacturing a semiconductor device.

The invention discloses a radio frequency receiver and a method for receiving a radio frequency input signal. The radio frequency receiver comprises a radiating element, a chip and a phase shift circuit. The radiating element is configured to receive a radio frequency input signal to generate a plurality of electrical signals. The chip includes an amplifier circuit. The amplifier circuit is configured to receive a plurality of phase-shifted signals from a plurality of input terminals, respectively, and amplify the plurality of phase-shifted signals to generate a radio frequency output signal. The phase shift circuit is located outside the chip and is coupled to the radiating element and the plurality of input terminals. The phase shift circuit is used for performing phase shift operation on the plurality of electric signals and generating the plurality of phase shift signals according to the plurality of electric signals. The phase shift circuit and the radiating element are formed on the same substrate. According to the radio frequency receiver, the size of a required chip can be reduced, the production cost is reduced, and the signal loss is reduced.