340 results about "Chip size" patented technology

The utility model relates to a near-infrared floating focusing machine vision lens, and belongs to the technical field of imaging optical system design. Comprising a first lens G1, a second lens G2, a third lens G3, a fourth lens G4, a fifth lens G5, a diaphragm STOP, a sixth lens G6, a seventh lens G7, an eighth lens G8, a ninth lens G9, a tenth lens G10, an eleventh lens G11 and a protection lens which are sequentially arranged from an object space to an image space along an optical axis. According to the utility model, eleven full-spherical lenses are used, floating focusing is adopted, and the diaphragm front lens group is controlled to move so as to cooperate with work under different working distances. The lens can be suitable for a chip with the size of 1 '', has a large aperture, and meets the requirements of high illumination, low chromatic aberration, small distortion and the like of a semiconductor detection lens in the field of machine vision detection.

To provide an optical waveguide element having a structure in which a proper tolerance is ensured in bonding, an optical connection loss between heterogeneous waveguides is small, and a chip size can be reduced even in the optical waveguide element obtained by bonding a low refractive index substrate and a TFLN.SOLUTION: The optical waveguide element comprises: a low refractive index substrate 1 composed of a material having a lower refractive index than that of lithium niobate (LN); a thin film 2 composed of LN and having a thickness of 1 μm or less, arranged on a part of the substrate 1, wherein an optical waveguide 10 having a higher refractive index than the substrate 1 and composed of materials other than LN is arranged on the substrate 1, at least a part of the optical waveguide 10 is continuously arranged from on the substrate 1 to on the thin film 2, the thin film 2 is shaped in slope in a thickness direction in a region (transition region) where the optical waveguide 10 crosses over an outer peripheral edge of the thin film 2, and an inclination (tanθ) of an edge is set to be 0.189 or less.SELECTED DRAWING: Figure 3

The invention discloses a wafer processing method and device, a chip sorting machine, a storage medium and a program product. The method comprises the following steps: acquiring a scanning map of a target wafer; dividing the scanning map into a plurality of areas according to the chip size in the scanning map; according to a preset rule, based on the neighborhood of the grain-free area, determining a target empty area needing crystal supplement in the grain-free area; and determining a crystal supplementing position in the target empty region and the region with the crystal grains, and supplementing the crystal according to the crystal supplementing position. According to the technical scheme provided by the invention, a certain number of chips are supplemented in the wafer which is originally distributed in a scattered manner, so that the wafer is continuously arranged. And furthermore, through screening of the empty areas, the number of supplemented crystals can be reduced as much as possible on the premise that the requirements of subsequent packaging equipment are met. Therefore, the production efficiency is improved, and the production cost is reduced.

The invention provides a flip LED chip and a manufacturing method thereof. According to the method, a traditional slender flip LED chip is designed and optimized to be of a wide and short structure, the layout of slender strip-shaped P / N electrode bonding pads is adopted, and the distance between the two electrode bonding pads is controlled to be 50-250 micrometers. The specific process comprises the steps of growing an LED epitaxial structure on a patterned substrate, forming an MESA, determining the size of a chip, sequentially preparing a transparent conductive layer, a medium reflecting layer and a metal reflecting layer, and improving the light emitting efficiency; and then depositing a double-layer insulating passivation layer and windowing, and manufacturing a two-stage metal electrode to form a P / N bonding pad. Through the design, the stress distribution of the chip is more uniform, the crystal breaking risk caused by stress concentration in the solid crystal packaging process is greatly reduced, meanwhile, the tin connection short circuit is avoided through the moderate bonding pad distance, and the reliability and the product yield of the LED chip are remarkably improved.

Embodiments of the present disclosure provide a fully decoupled three-axis MEMS gyroscope and an electronic product. The gyroscope comprises: a substrate, and an X / Y proof mass, Z proof masses, driving structures and Z decoupling masses that are fixed on the substrate; the X / Y proof mass is arranged around outer sides of the Z proof masses, the driving structures and the Z decoupling masses; the Z proof masses are oppositely arranged in an x-axis direction; the driving structures are oppositely arranged at outer sides of the Z proof masses in the x-axis direction; and the Z decoupling masses are oppositely arranged at inner sides of the Z proof masses in the x-axis direction. The X / Y proof mass is elastically connected to the driving structures adjacent thereto, the Z proof masses are elastically connected to the driving structures adjacent thereto, and the Z decoupling masses are elastically connected to the Z proof masses adjacent thereto. The gyroscope improves the Coriolis conversion rate of the X / Y proof mass, maximizes the utilization of the chip area, reduces chip size and cost, and reduces coupling errors and quadrature errors, thereby improving sensing accuracy.

The invention provides an FPVA biochip layout method considering reagent type difference in unit multiplexing, which comprises the following steps of: modeling a biochip layout task as a Markov decision process: according to the size of an input FPVA chip, the dependency relationship of each operation in a biochemical reaction sequence diagram, the reagent type contained in each operation and a binding scheduling scheme, determining the FPVA biochip layout task; initializing an FPVA mesh model and defining a state space, an action space and a reward function; wherein the reward function is set according to the total unit multiplexing complexity of the current layout scheme, the legality of the current component layout and the distance between the component and the center point of the FPVA chip; and finally, completing the FPVA biochip layout through the dual deep Q network based on a Markov decision process. By designing a reward function, the unit multiplexing complexity is minimized, and the distance between components containing the same type of reagents is reduced, so that the purposes of minimizing the cross contamination degree of a final layout scheme, the total length of a fluid transportation path and the bioassay completion time are achieved.

The invention relates to an MEMS-CMOS device vertical interconnection integrated packaging preparation method, which comprises the following steps of: processing a TSV (Through Silicon Via) on a first silicon wafer (3), and filling crystalline silicon (2a); respectively processing a CMOS circuit layer and an RDL layer on the first silicon wafer, and processing a germanium bonding point (8) on the other surface of the first silicon wafer; a second SOI silicon wafer (10) and a third SOI silicon wafer (11) are fused and bonded to form a cavity (9), an aluminum / titanium / aluminum bonding point (12) is prepared on the third silicon wafer, an MEMS movable microstructure (13) is prepared on the third silicon wafer, the metal aluminum / titanium / aluminum bonding point and the MEMS movable microstructure are electrically connected, and the aluminum-germanium bonding point of the first silicon wafer and the aluminum-germanium bonding point of the third silicon wafer are subjected to eutectic bonding. According to the invention, the size of an integrated packaging chip of the MEMS device and the CMOS processing circuit is greatly reduced, and meanwhile, the RDL structure can realize wafer-level bonding packaging without considering the types, layout and size of the MEMS device and the CMOS circuit.

The invention discloses a power supply self-adaptive active temperature compensation attenuator which comprises a radio frequency attenuation circuit, a positive voltage temperature compensation driving circuit and a power supply self-adaptive adjusting circuit. The radio frequency attenuation circuit is connected in series in a signal link and comprises a transistor and a resistor; the positive voltage temperature compensation driving circuit comprises a transistor, a diode and a resistor. The driving transistor outputs a voltage playing a temperature compensation role by utilizing the temperature change of the electrical characteristic of the diode, and outputs the voltage to the radio frequency attenuation circuit in a voltage division manner; the power supply self-adaptive adjusting circuit comprises a resistor and a diode, the resistor and the diode adjust the grid voltage of a transistor in the driving circuit when the power supply fluctuates, the output voltage of the whole driving circuit is adjusted, and the influence of power supply fluctuation on the driving circuit is counteracted. Positive voltage is used for working, the structure is novel, the chip size is small, the temperature compensation characteristic is good, and the application range is wide; and the power supply interference resistance is good.

According to the pressure auxiliary tool for nano-silver sintering and the sintering method, on the basis of a nano-silver sintering film material, a technological method of single-chip pre-fixing and multi-chip synchronous sintering is adopted, and integrated sintering of multiple chips on different assembling faces of a high-power module can be achieved through the integrated pressure auxiliary tool. The pressure auxiliary tool is made of a tungsten steel material which is high in structural strength and good in heat conduction performance, pressure heads with multiple heights are manufactured on the end face, and the heights and sizes of the pressure heads are used for being matched with the height difference of chip assembling faces and the sizes of chips. Compared with a mode of applying pressure to a single chip and synchronously applying pressure to a plurality of chips on a single assembly surface in the sintering process, the pressure auxiliary tool and the sintering method can greatly improve the sintering assembly efficiency, and can also meet the sintering requirements of the plurality of chips on different assembly surfaces.

The invention discloses an image sensing chip board-level packaging structure and a manufacturing method thereof.The packaging structure comprises a cofferdam type chip unit, the cofferdam type chip unit comprises a transparent substrate, a cofferdam structure and an image sensing chip, the front face of the image sensing chip is provided with a photosensitive area and a bonding pad, the transparent substrate covers the photosensitive area, and the cofferdam structure covers the bonding pad; a cofferdam structure is arranged between the transparent substrate and the image sensing chip, and the cofferdam structure surrounds the photosensitive area to form a closed area; the plastic package body wraps the side surface and the back surface of the cofferdam type chip unit; the first rewiring layer is arranged on one side, close to the front surface of the image sensing chip, of the plastic package body and is electrically connected with a bonding pad of the image sensing chip; the second rewiring layer penetrates through the plastic package body and is electrically connected with the first rewiring layer; and the external interconnection structure is electrically connected with the second rewiring layer. The packaging structure has excellent electrical quality and reliability, the packaging size is larger than the size of a bare chip, and the problem that the heat dissipation capacity is limited due to miniaturization of wafer-level packaging can be solved.

The invention relates to the field of immersed liquid cooling systems, and discloses a performance evaluation device and method for an immersed liquid cooling system, and the performance evaluation device for the immersed liquid cooling system comprises a plate heat exchanger; the cooling liquid circulating unit comprises a liquid cooling case and a cooling liquid pump, the liquid cooling case, the cooling liquid pump and the plate heat exchanger are connected through pipelines, and the pipelines are provided with flow regulating valves, pressure gauges and temperature sensors; by means of the testing device and method, various influence factors such as the chip size, the power density, the cooling liquid flow speed and internal disturbance can be tested, the performance of the immersed liquid cooling system can be comprehensively evaluated, and a scientific basis is provided for system design and optimization. And comprehensive monitoring and intelligent diagnosis of the immersed liquid cooling system can be realized by combining a deep fault diagnosis and health monitoring system, potential problems in the system can be found in time, fault occurrence can be predicted, and maintenance suggestions can be provided.

The utility model belongs to the technical field of chip sealing detection, and particularly relates to a multi-row rotatable suction nozzle module which is applied to chip detection and packaging equipment and is used for sucking chips, and the multi-row rotatable suction nozzle module is adjustable in spacing. The suction nozzle lifting module is used for driving a suction nozzle rotating module to move in the Z-axis direction, and the suction nozzle rotating module is used for driving the multi-suction-nozzle module to rotate around the Z axis; wherein the multi-suction-nozzle module is provided with a plurality of air cylinders and suction nozzles which are independently controlled, multiple or single chips can be sucked at a time, and actions of sucking, moving, steering, storing and the like are achieved; and meanwhile, the distance between the suction nozzles can be automatically adjusted according to different sizes of chips and different storage distances, so that application scenes such as TRAY disc material taking and placing, sorting and placing and taping chip material taking and placing are met, and the chip taking and placing device has the advantages of being compact in structure, diverse in function, convenient to adjust, high in efficiency, wide in compatible range, diverse in application scenes and the like.

A described example includes; a semiconductor die (300) having bond pads (208) on a device side surface, having a backside surface opposite the device side surface and having four sides extending between the device side surface and the backside surface; a layer of light blocking material (215) deposited on the device side surface, the light blocking material also covering the four sides; semiconductor material (225) on the exterior of the light blocking material covering the four sides, the semiconductor material spaced from the semiconductor device die by the light blocking material covering the four sides; a backside coating of light blocking tape (223) covering the backside surface; openings in the layer of light blocking material on the device side surface, the openings exposing under-bump material (207) formed on the bond pads; and terminals (221) that are formed by solder bumps or conductive post connects formed on the under-bump material.

The invention relates to a high-voltage SiC power device and a manufacturing method thereof in the technical field of semiconductors, the high-voltage SiC power device comprises a surface electrode, a terminal area and a passivation structure arranged on the terminal area, the passivation structure is in contact with the surface electrode, and the passivation structure extends from the surface of the terminal area to an exposed surface area between the surface electrode and a scribing channel. The passivation structure is arranged in a non-planar mode, the creepage path of the passivation structure is larger than the distance between the surface electrode and the scribing channel, and the problems that a passivation layer of an existing terminal structure is limited by a two-dimensional plane, and partial discharge initial voltage and long-term reliability are difficult to improve on the premise that the chip size is not increased are solved.

An inertial sensor and a method therefor. The inertial sensor includes: a first substrate; a medium layer stacked on the first substrate; a first electric-conductive layer stacked on the medium layer, first openings being formed in the first electric-conductive layer and spaced from one another; second electric-conductive layers being bonded to the first electric-conductive layer through bonding structures, a gap being formed between adjacent second electric-conductive layers, which are connected to each other by a connection part, and second openings being formed in each of the second electric-conductive layers and spaced from one another; and a second substrate covering the first substrate, a closed space being formed between the second substrate and the first substrate. Compared with a traditional single-layer structure, the die size is reduced, the manufacturing cost is reduced, and the integration of device into portable consumer applications is improved, and XY axis sensitivity is improved.

The invention relates to the technical field of packaging tests, in particular to a test method and system for simulating the filling effect of an adhesive on a BGA chip, and the method comprises the following steps: the BGA chip filling test method comprises the steps: obtaining a chip size and an image sample, setting adhesive spraying parameters, extracting boundary pixels, collecting a fitting image, and evaluating the stability; and injecting simulation colloid, extracting a propulsion contour, and counting a filling image to generate an effect overview. According to the method, a structural boundary image set is constructed by extracting packaging design drawing parameters, glue spraying, attaching and glue injection operations in a simulation environment are realized in combination with an image recognition and path judgment mode, a glue propelling state and boundary changes are continuously recorded by using an image frame sequence, and traditional slice observation is replaced by a whole-process image recognition means. And material consumption and slicing errors are avoided, the test efficiency and controllability are improved, the precision and adaptability of filling process verification are enhanced, and the limitations of evaluation result lagging and high operation dependence in the prior art are improved.

According to the chip packaging structure with the fuse, the fuse is arranged in the first metal layer, and the first chip and the second chip are arranged on the fifth metal layer and the sixth metal layer respectively, so that the area of the first chip and the area of the second chip are not affected by existence of the fuse; the size of the chip in the packaging structure provided by the utility model can be consistent with the size of the chip without the fuse in the packaging structure in the prior art.

The invention discloses a ball mounting device and method suitable for BGAs of different sizes and shapes, and belongs to the technical field of electronic component packaging and maintenance, and the device comprises a bottom base which is provided with a vacuum adsorption hole in the center and is used for adsorbing and fixing a BGA chip; the plurality of groups of replaceable positioning clamping pins are fixed on the bottom-layer base and are used for enclosing a positioning frame matched with the BGA chip in size; the middle-layer limiting frame is placed on the bottom-layer base, is used for bearing a ball mounting steel mesh and is provided with a positioning magnet for adsorbing and fixing the ball mounting steel mesh; and the top layer fixing frame is connected with the middle layer limiting frame, is provided with a height adjusting screw, and is used for finely adjusting the height difference between the bonding pad of the BGA chip and the ball mounting steel mesh. The method can effectively solve the problems of poor flexibility, high cost and low efficiency caused by a special jig in the traditional ball mounting process, has excellent tolerance fault-tolerant capability, and can meet the ball mounting requirements of BGA chips with different sizes and different shapes.

The utility model relates to the technical field of probe cards, and discloses a probe card with a buffer function, which comprises a shell, a probe plate is mounted in the middle of the shell, clamping rods are slidably connected to the front end and the rear end of the outer side of the top of the probe plate, and sliding strips are slidably connected to the sides, away from each other, of the two clamping rods. Rotating short columns are rotatably connected to the tops of the sliding strips, rotating circular plates are fixedly connected to the tops of the rotating short columns, connecting ropes are fixedly connected to the adjacent sides of the two rotating short columns, and a plurality of first springs are fixedly connected to the bottom of the probe plate at equal intervals. According to the utility model, when detection begins, the protective sleeve is rotated to enable the circular plate and the short column to rotate, the connecting rope is driven to wind the outer wall of the short column, the clamping rod moves along the sliding strip, the position of the probe plate is expanded, and after the size of the probe plate is selected according to the size of a chip, the second spring rebounds and is combined with the clamping rod, and the bottom of the probe plate is provided with a plurality of first springs for buffering.

The invention provides a working mode reconfigurable power division chip circuit structure and a working method thereof. The circuit structure comprises an input port tap, two output port taps, a three-wire coupling spiral coil, a grounding pole and two control switches. One input port tap is connected with a middle coil of the three-wire coupling spiral coil to serve as an incident signal input port; the two output port taps are connected with two ends of an outer side coil of the three-wire coupling spiral coil to serve as output signal output ports; the two ends of the grounding pole are connected between the tail ends of the middle coils of the three-wire coupling spiral coils through the control switches respectively. The two control switches are used for switching the working mode of the working mode reconfigurable power division chip circuit structure. According to the power divider, the connection state of the three-wire coupling spiral coil and the grounding pole is changed by switching the on-off state of the control switch, switching of two working modes of power division and balun is achieved in the same compact circuit structure, and efficient utilization of the chip size is achieved.

A wafer structure is disclosed comprising a top silicon layer with a polished surface, an oxide layer selectively removed in defined regions, and a bottom silicon layer. Selective oxide removal improves dicing, prevents small molecule ingress, and enhances MEMS device release and performance. The invention addresses challenges of conventional silicon-on-insulator (SOI) wafers, including jagged edges, particle generation during stealth dicing, slow and uncontrolled under-etch rates, and high resistive losses in radio frequency (RF) applications due to parasitic surface conduction. Patterning the oxide layer enables precise MEMS structure release, reduces die size, and improves RF isolation. The wafer structure is suitable for high-speed electronics, RF analog circuits, and MEMS devices such as resonators, accelerometers, and waveguides, offering improved manufacturability and device reliability.

The invention belongs to the technical field of laser cutting, and particularly relates to a laser cutting device for semiconductor materials, which comprises a cutting table, a guide rail mechanism is arranged on one side of the upper end surface of the cutting table, a laser cutting head is arranged on the guide rail mechanism, and a chip taking mechanism is further arranged on the cutting table; the chip taking mechanism comprises a groove plate connected to one side of the upper end face of the cutting table in a sliding mode, and a sliding groove of the groove plate is connected with a transverse moving plate in a sliding mode. By means of the chip taking mechanism, after the laser cutting head cuts the chips on the wafer into a plurality of independent chips with the same specification, the chips are separated from the wafer in a suction cup adsorption mode, and due to the fact that the number of the suction cups is multiple, and the distance between the adjacent suction cups can be matched with the specification of the chips in an adjusting mode, the chip taking efficiency is greatly improved. And a row of chips can be uniformly taken down from the wafer at a time, so that the taking efficiency of the chips is improved.

The present application relates to a method for establishing a wafer chip model based on the wafer size with a special decimal point, including: providing a wafer image, which is divided into multiple chip regions, and the size specifications of the chip regions have a special decimal point; determining the coordinate position of the center point of the wafer image; calculating a reference area based on the rounding error formed by the special decimal point; scanning the wafer based on the reference area; and establishing a wafer chip model. By adopting the above technical solution, since the reference area is calculated based on the rounding error generated by the special decimal point of the chip size, there will be no large rounding error when the chip regions in the reference area are automatically established, thus avoiding the probe station error reporting situation caused by the error.

The invention discloses a fast recovery diode semiconductor device and a preparation method thereof, and the device comprises a substrate, a plurality of upper grooves which are formed through downward etching from the upper surface of the substrate, and a plurality of lower grooves which are formed through upward etching from the lower surface of the substrate. The inner side wall of the upper groove and the upper surface area connected between the upper grooves are doped to form a first doped layer, the inner side wall of the lower groove and the lower surface area connected between the lower grooves are doped to form a second doped layer, the upper grooves are filled with metal to form first electrodes, and the lower grooves are filled with metal to form second electrodes. Compared with a traditional FRD device, the area utilization rate can be improved on the premise that the chip size is guaranteed, and the FRD device has more advantages in electrical parameters such as conduction voltage drop under the same size; the cost of the chip is effectively reduced, and the promotion of national electrification is facilitated; meanwhile, according to the structure, the junction edge position uses the surface of the silicon substrate to enable the junction edge position to be approximate to a planar junction, the complexity of terminal design is greatly reduced, and the chip size is further optimized.

The invention discloses a Micro-OLED (Organic Light Emitting Diode) chip packaging structure, a Micro-OLED chip packaging method and a Micro-OLED display device. The packaging structure comprises a semiconductor wafer which is provided with a conductive through hole penetrating to a metal bonding pad on the front surface of the semiconductor wafer; the plurality of metal bumps are formed on the back surface of the semiconductor wafer and are electrically connected with the metal bonding pads on the front surface through the conductive through holes and the metal rewiring layer on the back surface; the Micro-OLED light emitting layer is formed on the front surface of the semiconductor wafer; and the transparent cover plate is bonded with the front surface of the semiconductor wafer through a supporting wall. According to the invention, the wafer-level chip size packaging process sequence of the Micro-OLED is optimized as follows: the through holes and the salient points are firstly manufactured on the back surface, and then the OLED is manufactured on the front surface. According to the method, the metal bonding pads are allowed to be led out from the two sides, three sides or four sides of the chip, and particularly, the large-current power supply / ground bonding pads are arranged at the four corners of the chip, so that the internal current distribution of the chip is remarkably optimized, the IR voltage drop is reduced, and thinner and smaller Micro-OLED wafer-level packaging with better electrical performance is realized.

The utility model belongs to the technical field of micro electro mechanical systems (MEMS), and particularly relates to a large-capacitance capacitive chip structure. The utility model provides a large-capacitance capacitive chip structure with a small chip size. The utility model comprises a first pole plate (01), and is characterized in that the upper end face of the first pole plate (01) is provided with a groove (61), the upper end face of the first pole plate (01) is provided with a first insulating medium layer (41), and the upper end face of the first insulating medium layer (41) is provided with a second pole plate (02).

The present disclosure provides a semiconductor device and a control method thereof. The semiconductor device comprises a detection module, a chip carrying module and a control unit. The control unit is electrically connected with the detection module and the chip carrying module. The control unit is configured to generate a first control signal according to a geometric parameter collected by the detection module. The chip carrying module is responsive to the first control signal and adjusts a clamping space of a first clamping mechanism in the chip carrying module along a first direction so as to adapt the clamping space to the geometric size of the chip. In the present disclosure, the control unit can adjust the clamping space in the chip carrying module according to the geometric parameter detected by the detection module, thereby solving the problems of high tool procurement cost, high storage cost and long downtime for replacing tools caused by the fixed adaptation mode of "one chip size corresponds to one tool" in the related art.

The utility model discloses a biasing circuit, a biasing chip and a biasing device, which relate to the technical field of integrated circuits and comprise a first capacitor, a second capacitor, an inductor and a resistor, the first end of the first capacitor is connected with the first end of the inductor and serves as the input end of the biasing circuit, and the second end of the first capacitor serves as the output end of the biasing circuit; the first end of the resistor is connected with the first end of the inductor, the second end of the resistor is connected with the first end of the second capacitor and serves as the input end of the direct current bias power supply, and the second end of the second capacitor is grounded. According to the bias circuit, the resistor is additionally arranged and connected with the inductor in series, namely, under the condition that the small inductor is used, the total impedance of the direct current branch is increased, the insertion loss is reduced, and the requirements of small size, high bandwidth and small insertion loss of a bias chip are met. And a second capacitor is led out from the direct current branch to lead out a leaked alternating current signal, so that the alternating current signal is better prevented from being leaked to the direct current bias power supply.

The invention discloses a method and a device for correcting a light-emitting device array image and a storage medium, which are used for converting an irregular light-emitting device array into an array image with a fixed repetition period so as to facilitate defect detection and improve the defect detection efficiency. The method comprises the following steps: acquiring a chip array diagram for shooting a target screen, and acquiring coordinate positions of chips in the target screen and the number of rows and columns of the chips; constructing a chip coordinate matrix according to the coordinate position of the chip; according to the coordinate positions of the chips and preset chip size parameters, the row and column spacing between the chips is obtained through calculation; according to preset chip size parameters, the number of rows and columns of the chips and the row and column spacing between the chips, theoretical dot matrix coordinates are constructed; dividing the chip coordinate matrix into a first area coordinate group; according to the theoretical dot matrix coordinates and the first region coordinate group, performing regional calculation to obtain a region transformation matrix; and processing the first region coordinate group according to the region transformation matrix to obtain a corrected image.

A microelectronic device includes a die with input / output (I / O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I / O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I / O terminals, and a head contacting the column at an opposite end of the column from the I / O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.