568 results about "Chip size" patented technology

The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a resin-based gallium arsenide radio frequency chip fan-out packaging method. Comprising the following steps: using a temporary bonding support plate as a slide glass; coating photolysis temporary bonding glue on the slide glass in a spin coating mode, curing the photolysis temporary bonding glue, and then protecting the temporary bonding glue on the front surface by using a metal protection layer; bonding the back surfaces of the two heterogeneous gallium arsenide radio frequency chips to the front surface of the metal protection layer through a bonding layer; using a wafer-level plastic packaging process to package and wrap the two heterogeneous gallium arsenide radio frequency chips so as to form a first plastic packaging layer; performing laser or mechanical punching on the first plastic package layer to expose the metal protection layer so as to form a first plastic package through hole; and filling the first plastic package through hole to form a filler. According to the invention, the manufacturing cost of the chip is reduced, the miniaturization of the size of the chip is realized, the heat dissipation of the chip can be effectively enhanced by the high-heat-dissipation conductive layer on the back surface, and the performance of a system is improved.

According to the ellipsometer based on the micro-nano deformable structure provided by the invention, the ellipsometer can be reduced to a sub-pixel level by the metasurface based on the micro-nano deformable structure, and when a large amount of the micro-nano deformable structure is integrated in the space, parameters of a measured surface of a whole measured material can be obtained in an imaging form; the limitation that a traditional ellipsometer can only perform single-point measurement is broken through; namely, two-dimensional measurement can be carried out in an imaging mode, the defect of single-point measurement of a traditional ellipsometer is overcome, the on-chip size of the ellipsometer is greatly reduced, and the size of the ellipsometer is reduced to the single-pixel level; the micro ellipsometer can be combined with different optical lens groups to detect the optical property and uniformity of the whole film in an imaging manner, and the defect of single-point detection of a traditional micro ellipsometer is overcome; according to the total variation-based full Stokes polarization vector reconstruction model, constraint is applied to iteration internal data, so that an operation result is more stable and is easy to converge.

The invention discloses a large-size power chip no-pressure low-void-ratio welding method, which comprises the following steps of: determining proper thickness and size of a soldering lug according to the size of a chip and the material of a substrate; then cutting and carrying out plasma cleaning on the soldering lug to remove dirt on the surface of the soldering lug; welding sample assembly is completed through an automatic chip mounter; setting a vacuum welding curve according to the material characteristics of the welding sheet, determining key welding parameters such as formic acid pressure, formic acid reduction temperature, formic acid reduction time, peak temperature, peak temperature holding time, furnace chamber pressure and holding time and the like, and completing chip welding according to the set curve; and finally, measuring the internal void ratio of the welding seam by adopting an X-ray detector. On the basis of the vacuum eutectic welding technology, under the non-pressure welding condition, the air holes in the welding flux layer are discharged by regulating and controlling the environment pressure change in the welding process, and low-void-ratio welding of the large-size chip is achieved.

The utility model relates to the technical field of gallium nitride power devices, in particular to a double-channel enhanced GaN power device, which comprises a substrate, a nucleating layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating medium layer which are sequentially arranged from bottom to top. The device further comprises a first source-drain electrode group, a second source-drain electrode group, a first grid electrode and a second grid electrode. The structure is provided with two channels, two source electrodes, two grid electrodes and two drain electrodes, the on-resistance of the channels is reduced by adding one conducting channel, and the ohmic contact resistance of the source electrodes is reduced by forming ohmic contact between the two source electrodes and the two channels respectively. The ohmic contact resistance of the drain electrodes is reduced by forming ohmic contact between the two drain electrodes and the two channels respectively, so that the on resistance of the whole device is reduced under the condition that the chip area is not increased, and finally the chip size and the chip cost are reduced. In addition, the design of the two grid electrodes can ensure the control capability of the grid electrodes on the two channels.

A method for managing transfer groups at a DMA PMM using a hardware-linked list includes (i) sequentially querying and updating the transfer status of each transfer group in the transfer group queue according to the priorities of the transfer groups, (ii) configuring the transfer group queue based on the results of the query and the priorities of the transfer groups, and (iii) triggering the DMA to transfer the transfer group queue. The method enables priority management for transfer groups used in communication between chips without the need to add hardware modules, thereby avoiding an increase in chip size and manufacturing costs due to the addition of hardware modules. Furthermore, the DMA PMM provided by the present method can be flexibly applied to various different MCUs.

The invention provides a wafer measurement positioning method, electronic equipment and a readable storage medium. The method comprises the following steps: aligning a wafer to be measured with a measurement machine; dividing the wafer to be detected into a plurality of chip areas according to a preset chip size; taking a chip area meeting a preset measurement condition in the plurality of chip areas as a target chip area; for each target chip area, determining position information of a plurality of feature mark points in the target chip area; and for each target chip area, positioning the measurement point in the target chip area according to the position information of the at least one feature mark point in the target chip area. According to the invention, the measurement of all measurement points satisfying conditions on the wafer can be realized, and the accuracy and stability of wafer measurement are effectively improved.

The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

The utility model relates to a near-infrared floating focusing machine vision lens, and belongs to the technical field of imaging optical system design. Comprising a first lens G1, a second lens G2, a third lens G3, a fourth lens G4, a fifth lens G5, a diaphragm STOP, a sixth lens G6, a seventh lens G7, an eighth lens G8, a ninth lens G9, a tenth lens G10, an eleventh lens G11 and a protection lens which are sequentially arranged from an object space to an image space along an optical axis. According to the utility model, eleven full-spherical lenses are used, floating focusing is adopted, and the diaphragm front lens group is controlled to move so as to cooperate with work under different working distances. The lens can be suitable for a chip with the size of 1 '', has a large aperture, and meets the requirements of high illumination, low chromatic aberration, small distortion and the like of a semiconductor detection lens in the field of machine vision detection.

To provide an optical waveguide element having a structure in which a proper tolerance is ensured in bonding, an optical connection loss between heterogeneous waveguides is small, and a chip size can be reduced even in the optical waveguide element obtained by bonding a low refractive index substrate and a TFLN.SOLUTION: The optical waveguide element comprises: a low refractive index substrate 1 composed of a material having a lower refractive index than that of lithium niobate (LN); a thin film 2 composed of LN and having a thickness of 1 μm or less, arranged on a part of the substrate 1, wherein an optical waveguide 10 having a higher refractive index than the substrate 1 and composed of materials other than LN is arranged on the substrate 1, at least a part of the optical waveguide 10 is continuously arranged from on the substrate 1 to on the thin film 2, the thin film 2 is shaped in slope in a thickness direction in a region (transition region) where the optical waveguide 10 crosses over an outer peripheral edge of the thin film 2, and an inclination (tanθ) of an edge is set to be 0.189 or less.SELECTED DRAWING: Figure 3

The invention discloses a processing method for solving the problem of chip stacking of an SLP product, and belongs to the technical field of printed circuit boards. According to the processing method for solving the problem of chip stacking of the SLP product, after an inner-layer core board is manufactured, a pattern is etched firstly, a special blind groove is processed before green oil printing, and then the inner-layer core board is manufactured; and burning out the blind slot with the size of the chip by adopting carbon dioxide laser or UV laser, and finally obtaining the special blind slot with the required size. According to the method, the area and the thickness of the SLP product can be reduced, and the precision and the stability of the product can be improved.

The embodiment of the invention relates to the technical field of electronic equipment, and particularly provides a slot base, a mainboard, a production method of the mainboard and electronic equipment. The slot base comprises a base body, a first pin, a second pin and a solder ball. The base body is provided with a first face and a second face which are oppositely arranged in the first direction. The first pins penetrate through the base body in the first direction, the first ends of the first pins protrude out of the first face, and the second ends of the first pins protrude out of the second face. The second pins are arranged on the base body in a penetrating mode in the first direction, the first ends of the second pins protrude out of the first face, the length of the second pins is smaller than that of the first pins, and the second pins and the first pins are arranged at intervals. The solder ball is arranged on the second surface, and the solder ball is electrically connected with the second end of the second pin. According to the slot base provided by the embodiment of the invention, the problem of circuit board design difficulty caused by increased chip size and more pins of the slot base can be solved, and the number of outgoing line layers of the circuit board is reduced.

The present invention belongs to the technical field of integrated circuit packaging, and particularly relates to a fan-out packaging method for gallium arsenide radio frequency chips based on a resin base. The method comprises the following steps: using a temporary bonding carrier as a carrier; coating a photodecomposed temporary bonding adhesive on the carrier by spin coating and curing, and then using a metal protective layer to protect the temporary bonding adhesive on the front side; bonding the back sides of two heterogeneous gallium arsenide radio frequency chips to the front side of the metal protective layer through an adhesive layer; using a wafer-level plastic packaging process to plastic-package and encapsulate two heterogeneous gallium arsenide radio frequency chips to form a first plastic packaging layer; performing laser or mechanical drilling on the first plastic packaging layer to expose the metal protective layer to form a first plastic packaging through hole; and filling in the first plastic packaging through hole to form a filler. The present invention reduces the chip manufacturing cost and realizes the miniaturization of the chip size. At the same time, the high heat dissipation conductive layer on the back side can effectively enhance the heat dissipation of the chip and improve the performance of the system.

The invention discloses a wafer processing method and device, a chip sorting machine, a storage medium and a program product. The method comprises the following steps: acquiring a scanning map of a target wafer; dividing the scanning map into a plurality of areas according to the chip size in the scanning map; according to a preset rule, based on the neighborhood of the grain-free area, determining a target empty area needing crystal supplement in the grain-free area; and determining a crystal supplementing position in the target empty region and the region with the crystal grains, and supplementing the crystal according to the crystal supplementing position. According to the technical scheme provided by the invention, a certain number of chips are supplemented in the wafer which is originally distributed in a scattered manner, so that the wafer is continuously arranged. And furthermore, through screening of the empty areas, the number of supplemented crystals can be reduced as much as possible on the premise that the requirements of subsequent packaging equipment are met. Therefore, the production efficiency is improved, and the production cost is reduced.

The invention provides a flip LED chip and a manufacturing method thereof. According to the method, a traditional slender flip LED chip is designed and optimized to be of a wide and short structure, the layout of slender strip-shaped P / N electrode bonding pads is adopted, and the distance between the two electrode bonding pads is controlled to be 50-250 micrometers. The specific process comprises the steps of growing an LED epitaxial structure on a patterned substrate, forming an MESA, determining the size of a chip, sequentially preparing a transparent conductive layer, a medium reflecting layer and a metal reflecting layer, and improving the light emitting efficiency; and then depositing a double-layer insulating passivation layer and windowing, and manufacturing a two-stage metal electrode to form a P / N bonding pad. Through the design, the stress distribution of the chip is more uniform, the crystal breaking risk caused by stress concentration in the solid crystal packaging process is greatly reduced, meanwhile, the tin connection short circuit is avoided through the moderate bonding pad distance, and the reliability and the product yield of the LED chip are remarkably improved.

Embodiments of the present disclosure provide a fully decoupled three-axis MEMS gyroscope and an electronic product. The gyroscope comprises: a substrate, and an X / Y proof mass, Z proof masses, driving structures and Z decoupling masses that are fixed on the substrate; the X / Y proof mass is arranged around outer sides of the Z proof masses, the driving structures and the Z decoupling masses; the Z proof masses are oppositely arranged in an x-axis direction; the driving structures are oppositely arranged at outer sides of the Z proof masses in the x-axis direction; and the Z decoupling masses are oppositely arranged at inner sides of the Z proof masses in the x-axis direction. The X / Y proof mass is elastically connected to the driving structures adjacent thereto, the Z proof masses are elastically connected to the driving structures adjacent thereto, and the Z decoupling masses are elastically connected to the Z proof masses adjacent thereto. The gyroscope improves the Coriolis conversion rate of the X / Y proof mass, maximizes the utilization of the chip area, reduces chip size and cost, and reduces coupling errors and quadrature errors, thereby improving sensing accuracy.

The invention provides an FPVA biochip layout method considering reagent type difference in unit multiplexing, which comprises the following steps of: modeling a biochip layout task as a Markov decision process: according to the size of an input FPVA chip, the dependency relationship of each operation in a biochemical reaction sequence diagram, the reagent type contained in each operation and a binding scheduling scheme, determining the FPVA biochip layout task; initializing an FPVA mesh model and defining a state space, an action space and a reward function; wherein the reward function is set according to the total unit multiplexing complexity of the current layout scheme, the legality of the current component layout and the distance between the component and the center point of the FPVA chip; and finally, completing the FPVA biochip layout through the dual deep Q network based on a Markov decision process. By designing a reward function, the unit multiplexing complexity is minimized, and the distance between components containing the same type of reagents is reduced, so that the purposes of minimizing the cross contamination degree of a final layout scheme, the total length of a fluid transportation path and the bioassay completion time are achieved.

The invention relates to an MEMS-CMOS device vertical interconnection integrated packaging preparation method, which comprises the following steps of: processing a TSV (Through Silicon Via) on a first silicon wafer (3), and filling crystalline silicon (2a); respectively processing a CMOS circuit layer and an RDL layer on the first silicon wafer, and processing a germanium bonding point (8) on the other surface of the first silicon wafer; a second SOI silicon wafer (10) and a third SOI silicon wafer (11) are fused and bonded to form a cavity (9), an aluminum / titanium / aluminum bonding point (12) is prepared on the third silicon wafer, an MEMS movable microstructure (13) is prepared on the third silicon wafer, the metal aluminum / titanium / aluminum bonding point and the MEMS movable microstructure are electrically connected, and the aluminum-germanium bonding point of the first silicon wafer and the aluminum-germanium bonding point of the third silicon wafer are subjected to eutectic bonding. According to the invention, the size of an integrated packaging chip of the MEMS device and the CMOS processing circuit is greatly reduced, and meanwhile, the RDL structure can realize wafer-level bonding packaging without considering the types, layout and size of the MEMS device and the CMOS circuit.

The invention discloses a power supply self-adaptive active temperature compensation attenuator which comprises a radio frequency attenuation circuit, a positive voltage temperature compensation driving circuit and a power supply self-adaptive adjusting circuit. The radio frequency attenuation circuit is connected in series in a signal link and comprises a transistor and a resistor; the positive voltage temperature compensation driving circuit comprises a transistor, a diode and a resistor. The driving transistor outputs a voltage playing a temperature compensation role by utilizing the temperature change of the electrical characteristic of the diode, and outputs the voltage to the radio frequency attenuation circuit in a voltage division manner; the power supply self-adaptive adjusting circuit comprises a resistor and a diode, the resistor and the diode adjust the grid voltage of a transistor in the driving circuit when the power supply fluctuates, the output voltage of the whole driving circuit is adjusted, and the influence of power supply fluctuation on the driving circuit is counteracted. Positive voltage is used for working, the structure is novel, the chip size is small, the temperature compensation characteristic is good, and the application range is wide; and the power supply interference resistance is good.

According to the pressure auxiliary tool for nano-silver sintering and the sintering method, on the basis of a nano-silver sintering film material, a technological method of single-chip pre-fixing and multi-chip synchronous sintering is adopted, and integrated sintering of multiple chips on different assembling faces of a high-power module can be achieved through the integrated pressure auxiliary tool. The pressure auxiliary tool is made of a tungsten steel material which is high in structural strength and good in heat conduction performance, pressure heads with multiple heights are manufactured on the end face, and the heights and sizes of the pressure heads are used for being matched with the height difference of chip assembling faces and the sizes of chips. Compared with a mode of applying pressure to a single chip and synchronously applying pressure to a plurality of chips on a single assembly surface in the sintering process, the pressure auxiliary tool and the sintering method can greatly improve the sintering assembly efficiency, and can also meet the sintering requirements of the plurality of chips on different assembly surfaces.

Imaging devices with increased numbers of parallel analog-digital converters with maintained chip size are disclosed. In one example, an imaging device has a stacked chip structure including semiconductor chips of first through third layers. A pixel array is formed on the semiconductor chip of the first layer. An analog circuit of an analog-digital converter is disposed on the semiconductor chip of the second or third layer. A digital circuit of the analog-digital converter is disposed on the other of the semiconductor chip of the second or third layer.

The utility model discloses a burning device with chip spacing adjustment based on image recognition, which comprises a frame, and a burning assembly, a conveying assembly and a material suction assembly which are arranged on the frame, the conveying assembly extends along the length direction of the frame, the burning assembly and the conveying assembly are arranged at an interval along the width direction of the frame, and the material suction assembly is arranged on the frame. The material sucking assembly is arranged on the rack in a sliding mode and can transfer chips between the conveying assembly and the burning assembly, the material sucking assembly is provided with a plurality of sucking pieces used for sucking the chips, the conveying assembly is provided with a photographing assembly, and the photographing assembly is used for photographing the distance between the chips located on the conveying assembly so as to adjust the gaps between the sucking pieces. According to the chip burning method and device, when the photographing assembly photographs the chips on the conveying assembly, the photographed chips can be compared with the sizes of the chips in the database to obtain the corresponding chip spacing, so that the gaps among the multiple suction pieces are adjusted, adjustment can be carried out according to different chip spacing, and the chip burning efficiency is improved.

The utility model relates to the technical field of positioning jigs, and discloses a mounting jig for positioning a chip, which comprises a jig body, the jig body comprises a base and a reinforcing cover, a chip seat is detachably arranged in the base, a first groove is formed in the base, first screw holes are formed in four corners of the chip seat, and the reinforcing cover is arranged in the first screw holes. Second screw holes are formed in the positions, located at the four corners of the first groove, in the base, fixing bolts are arranged at the positions, located at the corresponding first screw holes, of the four corners of the upper end of the chip base in a threaded mode, and a chip groove is formed in the upper end face of the chip base. According to the utility model, the jig is simple to operate and convenient to use, can be positioned and installed according to the specific size and shape of the chip, ensures that the chip can be quickly and accurately positioned and fixed in the installation process, reduces human errors, and improves the overall assembly efficiency, thereby improving the applicability and accuracy of the jig.

The invention discloses an image sensing chip board-level packaging structure and a manufacturing method thereof.The packaging structure comprises a cofferdam type chip unit, the cofferdam type chip unit comprises a transparent substrate, a cofferdam structure and an image sensing chip, the front face of the image sensing chip is provided with a photosensitive area and a bonding pad, the transparent substrate covers the photosensitive area, and the cofferdam structure covers the bonding pad; a cofferdam structure is arranged between the transparent substrate and the image sensing chip, and the cofferdam structure surrounds the photosensitive area to form a closed area; the plastic package body wraps the side surface and the back surface of the cofferdam type chip unit; the first rewiring layer is arranged on one side, close to the front surface of the image sensing chip, of the plastic package body and is electrically connected with a bonding pad of the image sensing chip; the second rewiring layer penetrates through the plastic package body and is electrically connected with the first rewiring layer; and the external interconnection structure is electrically connected with the second rewiring layer. The packaging structure has excellent electrical quality and reliability, the packaging size is larger than the size of a bare chip, and the problem that the heat dissipation capacity is limited due to miniaturization of wafer-level packaging can be solved.

The invention relates to the field of immersed liquid cooling systems, and discloses a performance evaluation device and method for an immersed liquid cooling system, and the performance evaluation device for the immersed liquid cooling system comprises a plate heat exchanger; the cooling liquid circulating unit comprises a liquid cooling case and a cooling liquid pump, the liquid cooling case, the cooling liquid pump and the plate heat exchanger are connected through pipelines, and the pipelines are provided with flow regulating valves, pressure gauges and temperature sensors; by means of the testing device and method, various influence factors such as the chip size, the power density, the cooling liquid flow speed and internal disturbance can be tested, the performance of the immersed liquid cooling system can be comprehensively evaluated, and a scientific basis is provided for system design and optimization. And comprehensive monitoring and intelligent diagnosis of the immersed liquid cooling system can be realized by combining a deep fault diagnosis and health monitoring system, potential problems in the system can be found in time, fault occurrence can be predicted, and maintenance suggestions can be provided.

The utility model belongs to the technical field of chip sealing detection, and particularly relates to a multi-row rotatable suction nozzle module which is applied to chip detection and packaging equipment and is used for sucking chips, and the multi-row rotatable suction nozzle module is adjustable in spacing. The suction nozzle lifting module is used for driving a suction nozzle rotating module to move in the Z-axis direction, and the suction nozzle rotating module is used for driving the multi-suction-nozzle module to rotate around the Z axis; wherein the multi-suction-nozzle module is provided with a plurality of air cylinders and suction nozzles which are independently controlled, multiple or single chips can be sucked at a time, and actions of sucking, moving, steering, storing and the like are achieved; and meanwhile, the distance between the suction nozzles can be automatically adjusted according to different sizes of chips and different storage distances, so that application scenes such as TRAY disc material taking and placing, sorting and placing and taping chip material taking and placing are met, and the chip taking and placing device has the advantages of being compact in structure, diverse in function, convenient to adjust, high in efficiency, wide in compatible range, diverse in application scenes and the like.

The invention relates to the technical field of exosome extraction, and discloses a replaceable exosome extraction chip which comprises an upper cover and a lower cover which are detachably connected, the upper cover is provided with a liquid inlet, and the lower cover is provided with a liquid outlet; a sealing ring, a buffer gasket, a filter membrane and a lower end gasket are sequentially arranged in the lower cover, the buffer gasket is provided with a plurality of buffer holes, and the lower end gasket is provided with a plurality of filter holes. According to the scheme, the exosome extraction chip is small in size and convenient to carry; during extraction, only sample liquid needs to be injected into the extraction chip from the liquid inlet, the exosome can be collected on the filter membrane, the extraction of the exosome is realized, the operation is convenient, and the extraction efficiency of the exosome is effectively improved.

The invention discloses an RTOS inert processor context switching method, and relates to the technical field of electric digital data processing. According to the RTOS inert processor context switching method provided by the invention, task analysis is carried out in a software mode, special hardware does not need to be used for supporting, and the chip size and hardware resource overhead can be reduced. Moreover, the inert context switching logic is added in the context switching function of the real-time operating system to read the content of the second array and realize the dynamic conversion of storage and recovery operations, so that the defect when no hardware support exists can be overcome, and the system performance is improved.

To provide a semiconductor device capable of suppressing deterioration in electric characteristics and reducing a chip size, and a manufacturing method thereof.SOLUTION: According to one embodiment, a semiconductor device comprises a substrate, a first plug, first wiring, second wiring, a second plug, a third plug, and third wiring. The first plug is provided above the substrate, and extends in a first direction crossing an upper surface of the substrate. The first wiring is provided on the first plug, and contains copper. The second wiring is provided below the first plug. The second plug is located in a second direction crossing the first direction with respect to the first plug, and includes an upper end at a height different from an upper end of the first plug and a lower end at a height identical to the height of a lower end of the first plug. The third plug is provided on the second plug, extends in the first direction, and contains tungsten. The third wiring is provided below the second plug.SELECTED DRAWING: Figure 1

The invention provides a chip design method and system based on IO multiplexing performance optimization, a terminal and a medium, RTL codes are automatically generated by calling a script according to a constructed IO multiplexing information table and RTL codes of a high-speed IO output multiplexing module written in advance, and then the generated RTL codes are converted into corresponding circuits by utilizing a logic synthesis tool. The method comprises the following steps: firstly, carrying out IO (Input / Output) visualization on the basis of a chip size and a preliminary layout plan, and adjusting a position relationship between each functional module and an IO unit used by the functional module in the preliminary layout plan to obtain an optimized layout plan; and in the physically realized layout and post-layout stage, the positions of corresponding modules in the circuit are limited based on the optimized layout planning, and the input path and the output path of the functional signal are optimized to obtain a design layout. According to the method, a physical design tool can automatically realize time sequence performance optimization of function multiplexing IO, support is provided for large-scale general chips to realize a high-speed IO protocol, RTL codes can be automatically generated, manpower is reduced, and the condition of wire winding of IO signal wiring is avoided.

A described example includes; a semiconductor die (300) having bond pads (208) on a device side surface, having a backside surface opposite the device side surface and having four sides extending between the device side surface and the backside surface; a layer of light blocking material (215) deposited on the device side surface, the light blocking material also covering the four sides; semiconductor material (225) on the exterior of the light blocking material covering the four sides, the semiconductor material spaced from the semiconductor device die by the light blocking material covering the four sides; a backside coating of light blocking tape (223) covering the backside surface; openings in the layer of light blocking material on the device side surface, the openings exposing under-bump material (207) formed on the bond pads; and terminals (221) that are formed by solder bumps or conductive post connects formed on the under-bump material.