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6009 results about "Ground plane" patented technology

In electrical engineering, a ground plane is an electrically conductive surface, usually connected to electrical ground. The term has two different meanings in separate areas of electrical engineering. In antenna theory, a ground plane is a conducting surface large in comparison to the wavelength, such as the Earth, which is connected to the transmitter's ground wire and serves as a reflecting surface for radio waves. In printed circuit boards, a ground plane is a large area of copper foil on the board which is connected to the power supply ground terminal and serves as a return path for current from different components on the board.

Implantable medical device incorporating integrated circuit notch filters

Implantable medical devices (IMDs) having sense amplifiers for sensing physiologic signals and parameters, RF telemetry capabilities for uplink transmitting patient data and downlink receiving programming and interrogation commands to and from an external programmer or other medical device are disclosed. At least one IC chip and discrete components have a volume and dimensions that are optimally minimized to reduce its volumetric form factor. Miniaturization techniques include forming notch filters of MEMS structures or forming discrete circuit notch filters by one or more of: (1) IC fabricating inductors into one or more IC chips mounted to the RF module substrate; (2) mounting each IC chip into a well of the RF module substrate and using short bonding wires to electrically connect bond pads of the RF module substrate and the IC chip; and (3) surface mounting discrete capacitors over IC chips to reduce space taken up on the RF module substrate. The IC fabricated inductors are preferably fabricated as planar spiral wound conductive traces formed of high conductive metals to reduce trace height and width while maintaining low resistance, thereby reducing parasitic capacitances between adjacent trace side walls and with a ground plane of the IC chip. The spiral winding preferably is square or rectangular, but having truncated turns to eliminate 90° angles that cause point-to-point parasitic capacitances. The planar spiral wound conductive traces are further preferably suspended over the ground plane of the IC chip substrate by micromachining underlying substrate material away to thereby reduce parasitic capacitances.
Owner:MEDTRONIC INC

Implantable medical device incorporating miniaturized circuit module

Implantable medical devices (IMDS) having RF telemetry capabilities for uplink transmitting patient data and downlink receiving programming commands to and from an external programmer having an improved RF module configured to occupy small spaces within the IMD housing to further effect the miniaturization thereof. An RF module formed of an RF module substrate and at least one IC chip and discrete components has a volume and dimensions that are optimally minimized to reduce its volumetric form factor. Miniaturization techniques include: (1) integrating inductors into one or more IC chips mounted to the RF module substrate; (2) mounting each IC chip into a well of the RF module substrate and using short bonding wires to electrically connect bond pads of the RF module substrate and the IC chip; and (3) surface mounting discrete capacitors over IC chips to reduce space taken up on the RF module substrate. The integrated inductors are preferably fabricated as planar spiral wound conductive traces formed of high conductive metals to reduce trace height and width while maintaining low resistance, thereby reducing parasitic capacitances between adjacent trace side walls and with a ground plane of the IC chip. The spiral winding preferably is square or rectangular, but having truncated turns to eliminate 90° angles that cause point-to-point parasitic capacitances. The planar spiral wound conductive traces are further preferably suspended over the ground plane of the RF module substrate by micromachining underlying substrate material away to thereby reduce parasitic capacitances.
Owner:MEDTRONIC INC

Microstrip antenna for RFID device

Microstrip patch antenna (46), feed structure (48), and matching circuit (50) designs for an RFID tag (10). A balanced feed design using balanced feeds coupled by a shorting stub (56) to create a virtual short between the two feeds so as to eliminate the need for physically connecting substrate to the ground plane. A dual feed structure design using a four-terminal IC can be connected to two antennas (46a,46b) resonating at different frequencies so as to provide directional and polarization diversity. A combined near / field-far / field design using a microstrip antenna providing electromagnetic coupling for far-field operation, and a looping matching circuit providing inductive coupling for near-field operation. A dual-antenna design using first and second microstrip antennas providing directional diversity when affixed to a cylindrical or conical object, and a protective superstrate (66). An annual antenna (46c) design for application to the top of a metal cylinder around a stem.
Owner:UNIVERSITY OF KANSAS

Golf club head

A golf club head comprising an outer shell and a strike plate having a strike face. The outer shell and the strike face define a club head volume. A heel / toe axis extends through the center of gravity of the club head. The heel / toe axis is generally parallel to the strike face and generally horizontal relative to a ground plane when the club head is at an address position. The rotational moment of inertia about the heel / toe axis is related to the club head volume by the equation Ixx ≧,46*HV+77, where Ixx is the rotational moment of inertia about the heel / toe axis in units of kg-mm2 and HV is the club head volume in units of cm3.
Owner:TAYLOR MADE GOLF

Ultra-thin body super-steep retrograde well (SSRW) FET devices

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
Owner:GLOBALFOUNDRIES US INC
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