21results about How to "Reduce capacitance" patented technology

This disclosure provides a DC-DC converter and chip, wherein the DC-DC converter includes a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor, and a low-side power transistor. The bootstrap boost circuit provides a first boost voltage to the high-side drive circuit. The high-side drive circuit outputs a first high-side drive voltage to the control electrode of the high-side power transistor based on the first boost voltage. The charge pump boost circuit generates a second boost voltage through a charge pump and outputs a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage. The second boost voltage is greater than the first boost voltage. The first electrode of the high-side power transistor is coupled to the input voltage terminal, and the second electrode is coupled to the first electrode of the low-side power transistor via a switching node. The high-side power transistor is turned on or off according to the first and second high-side drive voltages. One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switching node.

The invention discloses an on-load voltage regulation distribution transformer with series converter chains bearing partial power, which is characterized by comprising a group of three-phase series converter chains and a three-phase industrial frequency transformer, the three-phase series converter chain is used for three-phase voltage regulation and comprises three converter sub-chains and N4 three-phase converter sink chains, and N4 is equal to 0 or 1; the three-phase industrial frequency transformer is used for isolating and reducing voltage and providing an energy transfer port for maintaining energy conservation of the three-phase series converter chain, the three-phase industrial frequency transformer comprises 3N0 + 3N1 + 3N2 + 3N2 + 3N4 primary windings and three secondary windings, and N0 is greater than or equal to 0; the invention solves the problems of short service life of the contact and power supply interruption of the sensitive load, and realizes continuous voltage regulation with lower equipment cost.

An NMOS transistor and its fabrication method are disclosed. The fabrication method includes: forming a first well region in a substrate; forming a gate structure on the surface of the first well region; performing a first ion implantation on the first well region to form a first doped region and a second doped region in the first well region on both sides of the gate structure, wherein the spacing between the first doped region and the gate structure is greater than the spacing between the second doped region and the gate structure; performing a second ion implantation on the first well region after the first ion implantation to form a third doped region and a fourth doped region in the first well region on both sides of the gate structure; forming a source region in the first doped region and a drain region in the second doped region. This invention effectively reduces the gate-source capacitance (Cgs) by adjusting the directionality and dose relationship of the light doping implantation.

This invention provides a method for constructing helical molecules and inorganic silicon nitride composite nanochannels for single-molecule sequencing. After pretreating a silicon nitride nanopore chip to remove surface impurities and dielectric breakdown to form silicon nitride nanopores, the resulting silicon nitride nanopores are assembled in a liquid cell. A buffer solution containing positively charged or neutral helical molecules is added to one side of the flowcell, while a blank buffer solution is added to the other side. Then, under an applied bias voltage, the combined force of electrophoresis and electroosmosis drives the helical molecules to intercalate into the negatively charged silicon nitride nanopores. When the current on both sides of the flowcell suddenly drops significantly, a composite nanochannel is formed, with the helical molecules and silicon nitride channels electrostatically bonded. Increasing and continuously applying the voltage strengthens the embedded helical structure. This invention assembles helical molecules and silicon nitride nanochannels through in-situ voltage-driven assembly, resulting in stable, long-lived, and high signal-to-noise ratio chiral nanochannels.

The embodiment of the invention provides a capacitor module, a driving motor controller and an electric driving system, the capacitor module comprises a third capacitor connected with a first capacitor and a second capacitor in parallel, the capacitance value of the third capacitor is larger than the equivalent capacitance of the first capacitor and the second capacitor, and when a power module works in a two-level mode, the third capacitor serves as a supporting capacitor; in a three-level mode, the first capacitor and the second capacitor serve as supporting capacitors. The third capacitor is connected with the first capacitor and the second capacitor in parallel, so that the sum of the capacitance values of the first capacitor, the second capacitor and the third capacitor can be smaller than the capacitance value of the first capacitor and the capacitance value of the second capacitor under the condition that only the first capacitor and the second capacitor exist under the constant electric driving power of the driving motor controller; therefore, the capacitance value and the volume of the capacitor are reduced. As the third capacitor can be used as a filter capacitor, the ripple voltage of the direct current bus can be controlled, and the capacitance value and the volume of the first capacitor and the second capacitor can be further reduced.

The present application relates to a kind of new near hemispherical probe and its preparation method, the near hemispherical probe can retain the excellent electrical characteristics of three-dimensional spherical structure, the area of collection electrode is small under the same electrode spacing, and the capacitance is low, and charge collection efficiency is almost independent of θ.Hemispherical electrode has good sealing, completely isolates detection sensitive area from substrate, dark current is not affected by wafer thickness, and extremely low noise is conducive to low-energy X-ray or low-energy particle detection.

This invention provides a prototype infrared detector with integrated metalens, its fabrication method, and an optoelectronic instrument. The prototype infrared detector with integrated metalens, its fabrication method, and the optoelectronic instrument of this invention offer an effective and feasible solution for the industrialization of infrared detectors with integrated metalens, and are beneficial to the development of optoelectronic devices. The prototype infrared detector with integrated metalens of this invention has the advantages of miniaturization and high performance, and is expected to be widely used in scenarios such as integrated miniaturized infrared detection and infrared detection in low-light environments.

This invention discloses a low-voltage, high-current electrolytic hydrogen production power supply system and control method based on a SiC and IGBT hybrid half-bridge, belonging to the field of electrolytic hydrogen production technology. The system includes: a hybrid half-bridge power module, used to convert the bus voltage into the total system output voltage and output IGBT branch current and SiC branch current under the control of a drive signal; a drive and isolation module, connected between the digital control and sampling module and the hybrid half-bridge power module, used to generate a drive signal based on a PWM signal and send the drive signal to the hybrid half-bridge power module; and a digital control and sampling module, used to sample key state variables of the system, calculate the PWM signal based on the key state variables, and send the PWM signal to the drive and isolation module. This invention compensates for the ripple of the low-frequency IGBT branch in real time through the high-frequency SiC branch, avoiding the problem of temporary ripple increase in traditional hybrid topologies during transients.

The invention provides a stacked transistor, a preparation method thereof, a device and electronic equipment. The method comprises the following steps: forming a first active structure and a second active structure which are stacked on a substrate; forming a first source-drain epitaxy of the first transistor based on the first active structure; reversing the wafer and thinning the substrate; forming a second source-drain epitaxy of the second transistor based on the second active structure; forming a second source drain metal, a second interlayer dielectric layer, a second gate structure and a second back-end interconnection layer of a second transistor based on the second active structure; a first interlayer dielectric layer and a first gate structure of the first transistor are formed based on the first active structure; forming a source-drain interconnection through hole and first source-drain metal of the first transistor in a source-drain region of the first transistor; the source-drain interconnection through hole penetrates through the first source-drain epitaxy and extends into the second source-drain epitaxy; the second source-drain epitaxy and the first source-drain epitaxy are electrically connected through a source-drain interconnection through hole; and forming a first back-end interconnection layer of the first transistor.

The invention relates to a pixel of a display device, the display device and an electronic device. A pixel of a display device includes: a first transistor having a first gate connected to a first node, a first terminal receiving a first power supply voltage, and a second terminal connected to a second node; a first capacitor connected between the first node and the second node; a second capacitor connected between the first power supply voltage and a second node; a second transistor transmitting a data voltage to the first node; and a third transistor selectively connecting the second node to the anode electrode of the light emitting element based on the first emission signal. In a first mode, during data writing, the third transistor is turned off, and the first transistor generates an emission current independent of a capacitance of the light emitting element. In the second mode, the third transistor is turned on, and the emission current depends on the capacitance of the light emitting element.

The application provides a high-speed, high-efficiency and low-cost semiconductor optical communication device and a preparation method thereof. The high-speed, high-efficiency and low-cost semiconductor optical communication device comprises a first Bragg reflector, first to Nth active layers arranged in sequence along a first direction on one side of the first Bragg reflector, wherein N is an integer greater than or equal to 2; first to N-1th tunnel junctions, wherein any nth-1th tunnel junction is located between an nth-1th active layer and an nth active layer, n is an integer greater than or equal to 2 and less than or equal to N; first to N-1th current limiting layers arranged along the first direction, wherein any nth-1th current limiting layer is located on the side of the nth-1th tunnel junction along a second direction, and the nth-1th current limiting layer has an overlapping projection on the sidewall of the nth-1th tunnel junction along the second direction; and wherein the second direction is perpendicular to the first direction.

This invention discloses a pseudo-resistor circuit, an RC filter circuit, a current mirror circuit, and a chip. The pseudo-resistor circuit includes a first MOSFET and a bias circuit. The bias circuit provides a bias voltage between the gate and source of the first MOSFET to enable the first MOSFET to operate in the subthreshold region, and adjusts the resistance value of the first MOSFET by adjusting this bias voltage. The pseudo-resistor circuit, RC filter circuit, current mirror circuit, and chip of this invention can achieve a high resistance value with a smaller area. This reduces the resistor area and allows for a smaller capacitor value to achieve the same RC time constant, thus reducing the capacitor area. Furthermore, the resistance value of this pseudo-resistor is less affected by process voltage-temperature (PVT), ensuring that the filtering effect of the RC filter does not change significantly with variations in PVT.

This invention discloses a high-speed, high-density ferroelectric memory, its fabrication method, and its applications, belonging to the field of semiconductor memories. The memory consists of an array of multiple memory cells, with substantially orthogonal word lines and bit lines connecting the two sides of the array. The memory cells of this invention employ a stacked structure of a top electrode, a varactor dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode. Electrically, this is equivalent to a ferroelectric capacitor connected in series with a varactor selector. By adjusting the voltage division relationship of the memory cells, the voltage division of the ferroelectric capacitor in the unselected cells is reduced, thus reducing its disturbance. Furthermore, the series capacitors reduce the RC delay of the memory cells, improving memory access speed. Therefore, this invention reduces the disturbance of unselected cells, increases the memory's storage window, reduces the memory's bit error rate, and improves memory access speed without increasing additional area overhead.

A low-capacitance environment-friendly intelligent track traffic signal special flexible cable is characterized by comprising two signal lines, a filling body, a belting layer and a sheath layer, the cable core assembly comprises two groups of signal wire pairs, one group is a working wire pair, the other group is a standby wire pair, functions of lightning protection and stray capacitance elimination and a comprehensive waterproof function are taken into consideration, so that the cable has low capacitance and excellent wear resistance, is applied to occasions such as new construction or quality improvement and reconstruction of urban rails or subway lines, greatly reduces the construction cost of railway signals, and has good application prospects. The cable is simple in structure, considerable in economic value and application value, low in capacitance, excellent in cable water resistance, interference resistance and wear resistance and small in signal attenuation, the safety and reliability of line operation are greatly improved, the railway signal construction cost can be effectively reduced, and the cable has popularization and application value.

The embodiment of the invention provides a display panel and a display device. According to the display panel, in the thickness direction of the display panel, at least part of a second pole plate of a second capacitor is arranged between a first scanning line and a first connecting line, and / or at least part of the second pole plate of the second capacitor is arranged between the first scanning line and a second connecting line; therefore, the second polar plate of the second capacitor can shield the parasitic capacitance between the first scanning line and the first connecting line, and / or the second polar plate of the second capacitor can shield the parasitic capacitance between the first scanning line and the second connecting line, so that the total capacitance of the first node and / or the second node can be reduced; therefore, the proportion of the first capacitor and the second capacitor is increased, the threshold voltage compensation capability is improved, and the risks of screen burn-in and service life deterioration are reduced.

The utility model relates to radio frequency amplifier technical field especially relates to a radio frequency amplifier protection circuit, including triode Q1 and Q2, the triode Q1 and Q2's emitting electrode is coupled and has voltage source VCC in common external, the triode Q1 and Q2's collector is coupled and has current source ISS in common external, the triode Q1's base is coupled with diode D1, diode D1's negative pole is coupled with diode D3, diode D3's positive pole is coupled with the triode Q2's base, the utility model discloses through diode D1 to D6 to the overvoltage protection of input differential pair tube, at this time, if the voltage difference between two input terminals is applied and exceeds the conduction voltage (0.7V) of PN junction, diode D1 or D2 will be turned on, and the input signal flow is made to flow between two input terminals, reaches the purpose of protecting radio frequency amplifier input differential pair tube.

The application discloses a power module and a modular power supply, comprising a multi-winding high-frequency transformer, a power frequency rectifier, a high-frequency converter, a diode rectifier bridge, an LC branch, a direct-current interface circuit and an equalization interface circuit; according to the port composition type, the application is divided into the following three parts: the first part is connected with the primary side high-frequency converter through the LC branch, the primary side high-frequency converter is connected with the power frequency rectifier, and the power frequency rectifier output constitutes an alternating current port; the second part is connected with the secondary side rectifier bridge through the LC branch, the secondary side rectifier bridge is connected with the direct-current interface circuit, and the direct-current interface circuit output constitutes a total direct-current port; the third part is connected with the equalization interface circuit through the LC branch, and an equalization port is constituted. The application greatly reduces the volume and weight of the magnetic element, improves the power density of the equipment, introduces the resonance technology to reduce the switching loss and improve the system efficiency, and is matched with independent AC accessories to construct a three-phase four-wire alternating current port, and provides multiple types and multiple functions of electrical interfaces.

This application discloses a semiconductor structure, manufacturing method, and electronic device. The semiconductor structure includes: a semiconductor substrate; a plurality of protrusions on the semiconductor substrate; and a sidewall stack on both sides of the protrusions. The sidewall stack includes a first sidewall on the sidewall of the protrusion and a second sidewall outside the first sidewall. The upper part of the second sidewall is connected to the upper part of the first sidewall. An air gap exists between the lower part of the second sidewall and the lower part of the first sidewall. At least a portion of the air gap in the protrusions extends below the surface of the semiconductor substrate. The semiconductor structure provided in this application includes a semiconductor substrate and protrusions. The upper part of the second sidewall of the protrusion is located on the upper part of the first sidewall, and an air gap exists between the lower part of the second sidewall and the lower part of the first sidewall. This air gap sidewall structure has a low dielectric constant, which greatly reduces the capacitance of the protrusions.

The application provides a plug connector and a connector assembly. The plug connector comprises an insulating base and a plug conductive terminal. The insulating base is formed with a plug-in slot and a through slot. The through slot is communicated with the plug-in slot. The plug conductive terminal is located in the plug-in slot and connected with the insulating base. The plug conductive terminal is formed with a contact portion located in the plug-in slot. Since the insulating base is formed with the plug-in slot and the through slot, the plug-in slot is communicated with the through slot, the inner cavity of the insulating base is communicated with the peripheral space of the insulating base through the slot position of the through slot, the problem that the elastic deformation of the plug conductive terminal is blocked when the plug connector is plugged with the socket connector is avoided, the capacitance of the contact area between the plug conductive terminal and the socket conductive terminal is effectively reduced, the characteristic impedance of the contact area is greatly improved, and the characteristic impedance of the contact area is ensured to meet the design requirements.

The invention relates to a control method of a power-down holding circuit for high-precision voltage conversion. The power-down holding circuit comprises a direct-current path circuit, a voltage switching circuit and a BOOST circuit, the voltage switching circuit comprises an electronic switch and a voltage sampling circuit which are electrically connected; the direct-current path circuit, the BOOST circuit and the voltage sampling circuit are electrically connected with an input voltage respectively; the input end of the electronic switch is electrically connected with the voltage sampling circuit and the BOOST circuit respectively; the DC path circuit and the output end of the electronic switch are electrically connected with the DC / DC power supply respectively; the BOOST circuit is electrically connected with the electronic switch; the device is reasonable in design, compact in structure and convenient to use.

The invention relates to a gate driver, a display device and an electronic device. The gate driver includes: an input circuit transmitting an input signal to a control circuit based on a first clock signal; a control circuit that controls a voltage of a control node based on an input signal, a first clock signal, a second clock signal, and a voltage control signal; and an output circuit outputting a gate signal based on the voltage of the control node. The control circuit transmits one of the first power supply voltage and the second power supply voltage to a control node, and the output circuit outputs one of the first power supply voltage and the third power supply voltage as a gate signal.