70results about How to "Reduce capacitance" patented technology

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: forming a first sacrificial layer on a first metal layer structure, etching the first sacrificial layer to form a plurality of step-shaped first grooves which are arranged at intervals, and forming a second metal wire and a metal through hole with the width smaller than that of the second metal wire in the first grooves. Next, the first sacrificial layer between the adjacent second metal wires is removed to form a second groove, and the second groove is filled with a dielectric layer material to form a first dielectric layer; and after the first dielectric layer is etched until part of the first sacrificial layer on the side wall of the metal through hole is exposed, the first sacrificial layer on the side wall of the metal through hole is removed, so that a first air gap is formed between the first dielectric layer and the metal through hole, and finally, the second groove is continuously filled with the dielectric layer material, so that the top surface of the first dielectric layer is flush with the top surface of the second metal wire. Because the dielectric constant of air is far low, the formation of the first air gap reduces the capacitance between the metal interconnection structures, improves the RC delay, and improves the semiconductor performance.

The invention discloses a grid-controlled pixel driving circuit which comprises a first transistor, a second transistor and a third transistor, a first source drain electrode of the first transistor is coupled to a data signal line, a second source drain electrode of the first transistor is coupled to a pre-storage capacitor and a grid electrode of the second transistor, and the grid electrode of the first transistor is coupled to a control signal line; a first source drain electrode of the second transistor is coupled to a reference signal line, and a second source drain electrode of the second transistor is coupled to a first source drain electrode of the third transistor; the grid electrode of the third transistor is coupled to the transfer signal line, and the second source drain electrode is coupled to the pixel capacitor and the holding capacitor.

The invention relates to a generator facilitating shaft current measurement and a shaft current testing method thereof.The generator comprises a rotating shaft, the output end of the rotating shaft is sleeved with a bearing, the end face of the output end of the rotating shaft is connected with a rotor through a flange plate, and the side, opposite to the rotating shaft, of the flange plate is connected with a special-shaped grounding ring; the stator is sleeved with a machine base, a stator coil is further arranged between the rotor and the stator, a front end cover is assembled at the front end of the machine base, a rear end cover is assembled at the rear end of the machine base, the rear end cover is connected with the grounding end of a grounding carbon brush, one end of a brush body of the grounding carbon brush is connected with a special-shaped grounding ring, and a first insulator is clamped at the connecting position of the flange plate and the rotating shaft. The two sides of the first insulator are respectively provided with a first grounding block and a second grounding block, and the rotating shaft is sleeved with an AC flexible current probe. The generator is convenient for accurately measuring the shaft current passing through the bearing, improves the accuracy of the measurement result, and is beneficial to avoiding the problem of electrocorrosion.

The invention provides a silicon controlled rectifier detection circuit, an LED driving system and a bleeder current control method, and the circuit comprises a bus voltage detection module which generates a pulse signal corresponding to a jump edge of a bus voltage; the pulse voltage detection module is used for generating a front switching or back switching judgment signal of the silicon controlled rectifier and triggering a reset signal; the counting module is used for counting the period of the bus voltage and resetting the counting result when the reset signal is valid; and the discharge control module generates a first control signal when the counting result is smaller than a preset value, and generates a second control signal when the counting result is larger than or equal to the preset value, the first control signal controls a subsequent circuit to perform discharge current control, and the second control signal controls the subsequent circuit to turn off the discharge current. The front-cut dimmer and the rear-cut dimmer are identified, and the compatibility of the silicon controlled rectifier is improved; misjudgment caused by a large phase angle of the silicon controlled rectifier is avoided; the anti-interference performance is high; the system is simple in design and small in chip area.

The invention discloses a solid-state transformer topology based on MMC lightweight submodules and a frequency mixing modulation method thereof, the topology comprises an input stage, an intermediate stage and an output stage, the input stage comprises a first voltage alternating current port and a first current direct current port, and the first voltage alternating current port is used for connecting a three-phase alternating current; the output stage comprises a second voltage alternating current port and a second current direct current port; the intermediate stage comprises a front intermediate stage and a rear intermediate stage, and the front intermediate stage comprises a three-phase bridge arm; in the same single-phase bridge arm, the number of the sub-modules of the upper bridge arm is the same as that of the sub-modules of the lower bridge arm, and the sub-modules of the upper bridge arm and the sub-modules of the lower bridge arm are connected with the primary side of the same intermediate-stage transformer; and the rear middle stage comprises a plurality of rectifying circuits. By adopting the technical scheme, the high-frequency and low-frequency pulse current received by the sub-module can be reduced, the capacitance value of the capacitor in the sub-module is reduced, and the light weight of the sub-module is realized.

The invention discloses a display panel, a driving method thereof and a display device. The display panel is provided with a display area and comprises a plurality of pixel units located in the display area. Each pixel unit comprises a main pixel and an auxiliary pixel; the opening area of the main pixel is larger than that of the auxiliary pixel; the driving circuit is electrically connected with the pixel units and used for driving the main pixels and the auxiliary pixels in the pixel units to be lightened; a first group of parameters and a second group of parameters are stored in the driving circuit, and the first group of parameters are used for driving the main pixels in the pixel units to be lightened and driving the auxiliary pixels not to be lightened in the initial stage of low-brightness picture display; the second group of parameters are used for driving the main pixels and the auxiliary pixels in the pixel units to be lightened in the subsequent stage of low-brightness picture display; the low-brightness picture is a picture with the display brightness below 2nit. According to the display panel, the defects of smear, temperature drift, greenness, turn-on and the like during switching display of low-brightness pictures can be improved, and the picture quality of the low-brightness pictures is optimized.

This disclosure provides a DC-DC converter and chip, wherein the DC-DC converter includes a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor, and a low-side power transistor. The bootstrap boost circuit provides a first boost voltage to the high-side drive circuit. The high-side drive circuit outputs a first high-side drive voltage to the control electrode of the high-side power transistor based on the first boost voltage. The charge pump boost circuit generates a second boost voltage through a charge pump and outputs a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage. The second boost voltage is greater than the first boost voltage. The first electrode of the high-side power transistor is coupled to the input voltage terminal, and the second electrode is coupled to the first electrode of the low-side power transistor via a switching node. The high-side power transistor is turned on or off according to the first and second high-side drive voltages. One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switching node.

The invention discloses an on-load voltage regulation distribution transformer with series converter chains bearing partial power, which is characterized by comprising a group of three-phase series converter chains and a three-phase industrial frequency transformer, the three-phase series converter chain is used for three-phase voltage regulation and comprises three converter sub-chains and N4 three-phase converter sink chains, and N4 is equal to 0 or 1; the three-phase industrial frequency transformer is used for isolating and reducing voltage and providing an energy transfer port for maintaining energy conservation of the three-phase series converter chain, the three-phase industrial frequency transformer comprises 3N0 + 3N1 + 3N2 + 3N2 + 3N4 primary windings and three secondary windings, and N0 is greater than or equal to 0; the invention solves the problems of short service life of the contact and power supply interruption of the sensitive load, and realizes continuous voltage regulation with lower equipment cost.

A semiconductor structure and a mask layout, the structure comprising: a substrate comprising a substrate and a plurality of channel structures protruding from the substrate, the channel structures extending along a first direction and being arranged in parallel along a second direction, the first direction being perpendicular to the second direction; the gate structures are located on the substrate and stretch across the channel structures, and the gate structures extend in the second direction and are arranged in parallel in the first direction; the source-drain doping layer is located in the channel structure on the two sides of the gate structure; the source-drain interconnection lines are located between the adjacent gate structures, and the source-drain interconnection lines extend in the second direction, stretch across the source-drain doping layers and are electrically connected with the source-drain doping layers; the partition structure extends in the first direction to penetrate through one or more source-drain interconnection lines and partitions the source-drain interconnection lines located on the two sides of the partition structure in the second direction, and the partition structure is provided with protruding parts which extend in the second direction and penetrate through the source-drain interconnection lines at the partition positions of the source-drain interconnection lines. The working frequency of the semiconductor structure can be improved.

The invention discloses a trench isolation structure, a preparation method thereof and a semiconductor device, and the preparation method comprises the steps: providing a semiconductor substrate which comprises a trench; at least the interior of the groove is filled with a sacrificial layer, and the filled sacrificial layer exposes a part of height of the side wall of the groove in the depth direction from the port of the groove to the interior of the groove. A first oxidation film layer is at least formed on the side wall of the groove and above the sacrificial layer in the groove, a first part of the first oxidation film layer is formed on the side wall of the groove, and a gap is formed in the first part; the second portion is formed at the bottom of the gap and on the sacrificial layer. Forming a window on the second part, wherein the window exposes part of the sacrificial layer; and removing the sacrificial layer in the groove based on the window. And filling the gap in the first part with a second oxide film layer until the gap is completely filled with the second oxide film layer. Therefore, the preparation process of the trench isolation structure can be simplified, the preparation difficulty and cost can be reduced, and the performance of the semiconductor device can be improved.

An NMOS transistor and its fabrication method are disclosed. The fabrication method includes: forming a first well region in a substrate; forming a gate structure on the surface of the first well region; performing a first ion implantation on the first well region to form a first doped region and a second doped region in the first well region on both sides of the gate structure, wherein the spacing between the first doped region and the gate structure is greater than the spacing between the second doped region and the gate structure; performing a second ion implantation on the first well region after the first ion implantation to form a third doped region and a fourth doped region in the first well region on both sides of the gate structure; forming a source region in the first doped region and a drain region in the second doped region. This invention effectively reduces the gate-source capacitance (Cgs) by adjusting the directionality and dose relationship of the light doping implantation.

A semiconductor device structure includes a first fin structure, a first source / drain structure, a second source / drain structure, a third source / drain structure, a first word line, and a second word line. The first fin structure is disposed over a semiconductor substrate and includes a first channel region, a second channel region, and a further region. The first source / drain structure, the second source / drain structure, and the third source / drain structure are disposed over the first fin structure. The first word line is disposed between the first source / drain structure and the second source / drain structure and across the first channel region of the first fin structure as viewed from a top view of the semiconductor element structure. The second word line is disposed between the second source / drain structure and the third source / drain structure and across the second channel region of the first fin structure as viewed from the top view. A width of the first channel region is equal to a width of the second channel region, and the width of the first channel region is less than a width of the other region of the first fin structure.

Systems and methods for a detector for medical imaging are provided. The detector for medical imaging comprises a mesh-shaped detector element (302) formed on a flat face of a first semiconductor layer (502). The mesh detector element (302) includes a metal layer (318) including a plurality of longitudinal strips (305), where each longitudinal strip is positioned over a respective second semiconductor layer (404) having an opposite doping polarity to the first semiconductor layer (502), and embedded in the first semiconductor layer (502). Further, each longitudinal strip is separated from an adjacent longitudinal strip by a respective one of the plurality of openings (307) such that the metal layer (318) does not extend continuously over the width of the mesh detector element (302).

A light-receiving element according to an embodiment of the present disclosure includes: a semiconductor substrate (11) including a photoelectric conversion region; a first first electrically-conductive region (13A) provided at an interface of one surface of the semiconductor substrate (11) and coupled to a first electrode (16); a second first electrically-conductive region (13B) provided at the interface of the one surface and around the first first electrically-conductive region (13A) and coupled to a second electrode (17); and a third first electrically-conductive region (13C) provided at the interface of the one surface and around the second first electrically-conductive region (13B) and being in an electrically floating state.

This invention provides a method for constructing helical molecules and inorganic silicon nitride composite nanochannels for single-molecule sequencing. After pretreating a silicon nitride nanopore chip to remove surface impurities and dielectric breakdown to form silicon nitride nanopores, the resulting silicon nitride nanopores are assembled in a liquid cell. A buffer solution containing positively charged or neutral helical molecules is added to one side of the flowcell, while a blank buffer solution is added to the other side. Then, under an applied bias voltage, the combined force of electrophoresis and electroosmosis drives the helical molecules to intercalate into the negatively charged silicon nitride nanopores. When the current on both sides of the flowcell suddenly drops significantly, a composite nanochannel is formed, with the helical molecules and silicon nitride channels electrostatically bonded. Increasing and continuously applying the voltage strengthens the embedded helical structure. This invention assembles helical molecules and silicon nitride nanochannels through in-situ voltage-driven assembly, resulting in stable, long-lived, and high signal-to-noise ratio chiral nanochannels.

The invention discloses an AC / DC converter DC bus capacitor capacitance value reduction system under an unbalanced power grid, which comprises a three-phase power grid, an LCL filter, a DC bus capacitor, a load, a three-phase two-level converter main circuit and a Buck power decoupling circuit, wherein the main circuit is used for power conversion; the Buck decoupling circuit is used for absorbing double frequency pulse power formed by a product of positive sequence voltage and negative sequence current on an alternating current side, so that the capacitance value of a direct current bus capacitor is reduced. The Buck decoupling circuit is added to the DC bus of the AC / DC converter under the unbalanced power grid, the double-frequency power pulsation on the DC side is effectively filtered out, the capacitance value of the DC bus capacitor is reduced, meanwhile, the thin-film capacitor with the small capacitance value and the long service life is used for replacing a traditional electrolytic capacitor, the reliability and stability of the system are improved, and the service life of the system is prolonged. The grid-side current balance positive sequence and the direct-current side voltage stability are realized, and the new energy power generation utilization rate and the overall efficiency of a power system are remarkably improved.

A semiconductor device structure includes a semiconductor substrate, a first fin structure, a first source / drain structure, and a bit line contact. The first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall. The first source / drain structure is disposed over the first fin structure and covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall. The bit line contact is disposed over the first source / drain structure. The bit line contact includes a barrier layer in contact with the first source / drain structure and a conductive layer disposed over the barrier layer.

The utility model provides a power assembly applied to a double-electric-control integrated water channel, which comprises a shell, the shell comprises two electrical chambers arranged side by side, each electrical chamber comprises a cooling partition plate, and the cooling partition plates divide the electrical chambers into an upper-layer power module mounting chamber and a lower-layer capacitor chamber. The capacitor core is arranged in the capacitor chamber, and the power module is arranged in the power module mounting chamber; the power module is fixed on the shell, so that a cooling cavity is formed between the power module and the cooling partition plate, and the cooling cavity is used for accommodating cooling water so as to cool the power module and the capacitor core; the two electrical cavities are separated through a blocking wall, a communicating water channel is arranged on the blocking wall, and the two ends of the communicating water channel are communicated with the cooling cavities of the two electrical cavities respectively.

The utility model belongs to the technical field of semiconductor devices, and discloses a discrete device packaging structure which comprises a heat dissipation support made of a conductive material, a chip and a plastic package body. The bottom of the chip is provided with a bottom electrode, and the top is provided with a top electrode; the heat dissipation support is provided with a first pin, the bottom of the chip is attached to the top of the heat dissipation support, and the bottom electrode is attached to the top of the heat dissipation support. The discrete device packaging structure further comprises metal connecting pieces, the bottoms of the metal connecting pieces and the tops of the top electrodes are attached and connected in a one-to-one correspondence mode, one end of each metal connecting piece extends out of the heat dissipation support to form a second pin, and the top face of the heat dissipation support, the chip and the portions, located on the heat dissipation support, of the metal connecting pieces are subjected to plastic packaging through the plastic packaging body. Therefore, heat dissipation efficiency can be improved, electrical connection reliability can be enhanced, parasitic inductance and capacitance can be reduced, signal transmission rate can be improved, and packaging height can be reduced.

The embodiment of the invention provides a capacitor module, a driving motor controller and an electric driving system, the capacitor module comprises a third capacitor connected with a first capacitor and a second capacitor in parallel, the capacitance value of the third capacitor is larger than the equivalent capacitance of the first capacitor and the second capacitor, and when a power module works in a two-level mode, the third capacitor serves as a supporting capacitor; in a three-level mode, the first capacitor and the second capacitor serve as supporting capacitors. The third capacitor is connected with the first capacitor and the second capacitor in parallel, so that the sum of the capacitance values of the first capacitor, the second capacitor and the third capacitor can be smaller than the capacitance value of the first capacitor and the capacitance value of the second capacitor under the condition that only the first capacitor and the second capacitor exist under the constant electric driving power of the driving motor controller; therefore, the capacitance value and the volume of the capacitor are reduced. As the third capacitor can be used as a filter capacitor, the ripple voltage of the direct current bus can be controlled, and the capacitance value and the volume of the first capacitor and the second capacitor can be further reduced.

The present application relates to a kind of new near hemispherical probe and its preparation method, the near hemispherical probe can retain the excellent electrical characteristics of three-dimensional spherical structure, the area of collection electrode is small under the same electrode spacing, and the capacitance is low, and charge collection efficiency is almost independent of θ.Hemispherical electrode has good sealing, completely isolates detection sensitive area from substrate, dark current is not affected by wafer thickness, and extremely low noise is conducive to low-energy X-ray or low-energy particle detection.

The invention relates to a single-phase split-phase motor starting control circuit and an adaptive capacitor thereof. The circuit comprises a signal acquisition part, a CPU processing part, a power supply part and a driving part, the power supply part is respectively connected with each part and is used for supplying power; the signal acquisition part is connected with the CPU processing part and is used for acquiring current, voltage and phase signals, performing CPU operation based on the acquired signals and generating instruction signals for controlling the driving part; three parallel / series capacitors and corresponding control circuits are adopted, motor operation parameters are collected in real time, a CPU judges the state of the motor according to a preset strategy and controls capacitor switches, all the capacitors are connected in parallel in the starting stage to provide large starting torque, and series-parallel combination is conducted in the stable operation process to reduce the capacitance value and improve the efficiency. And the capacitor is cut off to protect the motor when locked-rotor occurs.

The present disclosure provides a broadband receiver and a frequency calibration method thereof. The broadband receiver includes: a down-conversion mixing module arranged in the down-conversion section of the broadband receiver; it includes: a first multi-phase filter block, which is arranged to convert a pair of differential signals from a low noise amplifier into four orthogonal radio frequency signals with phases increasing by 90 degrees in sequence and pass them to a mixer group; a second multi-phase filter block, which is arranged to convert a pair of differential signals from an oscillator into four orthogonal local oscillator signals with phases increasing by 90 degrees in sequence and pass them to a mixer group; a mixer group, which is arranged to mix four orthogonal radio frequency signals with four orthogonal local oscillator signals to generate an intermediate frequency signal and pass it to the intermediate frequency part of the receiver. The present disclosure also provides a corresponding frequency calibration method. The broadband receiver provided in some embodiments of the present disclosure can reduce power consumption while maintaining a high image rejection ratio after switching the operating frequency.

The invention relates to the technical field of piezoelectric material preparation, and discloses stacked high-voltage-resistant piezoelectric ceramic and a manufacturing method thereof. The stack type high-voltage-resistant piezoelectric ceramic comprises an insulating sheet, a piezoelectric ceramic sheet, an electrode, an electric lead and an insulating layer. The piezoelectric ceramic pieces are stacked between the two insulating pieces, and the positive electrode faces and the negative electrode faces of every two adjacent piezoelectric ceramic pieces are arranged in opposite directions. The electrodes include a positive electrode and a negative electrode. The electrode plates are connected in series through the connecting beams. The electrodes and the piezoelectric ceramic pieces are alternately stacked and bonded. And the two electric leads are respectively connected with the positive electrode and the negative electrode. The insulating layer wraps the insulating sheets, the piezoelectric ceramic sheets and the electrodes and fills the arc-shaped cavities connected with the cross beams. The invention has the advantages of same volume, low electrostatic capacity, better dynamic performance under the condition of preloading force and high voltage resistance, so that the invention can be normally used in special environments such as high voltage, high humidity and the like. The manufacturing process is simple, the efficiency is high, and the product has the characteristics of stability and high pressure resistance.

The invention provides an array substrate and a preparation method thereof, a display panel and a display device. The array substrate comprises a substrate and an oxide thin film transistor arranged on the substrate, the oxide thin film transistor comprises an oxide channel layer, a first gate insulating layer and a first gate layer; wherein the first gate insulating layer is arranged on the side, away from the substrate, of the oxide channel layer, the first gate layer is arranged on the side, away from the substrate, of the first gate insulating layer, and a gap is formed between the first gate layer and the first gate insulating layer; and the orthographic projection of the gap on the oxide channel layer is located in the orthographic projection area of the first gate layer on the oxide channel layer. The array substrate has a large subthreshold swing of a transfer characteristic curve, the uniformity of a display panel is improved, the display panel has a good display effect, and the yield and product competitiveness of the display panel are improved.

Provided in the present embodiment are a bulk acoustic wave resonance device, a filter device and a radio frequency front-end device. The bulk acoustic wave resonance device comprises: a first layer comprising a cavity; a first electrode layer having at least one end located in the cavity; a piezoelectric layer, which is located on the first electrode layer to cover the cavity and comprises a first side and a second side opposite the first side, the first electrode layer being located on the first side; a second electrode layer located on the second side and on the piezoelectric layer, the portion of the second electrode layer that overlaps the first electrode layer being located above the cavity and corresponding to the cavity; and a first composite structure, which is located on the first side, comes into contact with the piezoelectric layer, and is adjacent to the first electrode layer in a horizontal direction, wherein a first end of the first composite structure close to the first electrode layer is located in the cavity, and a second end thereof opposite the first end in the horizonal direction and away from the first electrode layer is embedded into the first layer, and the first composite structure comprises a first edge extension layer and a first support layer that is located between the piezoelectric layer and the first edge extension layer. The bulk acoustic wave resonance device is used to reduce fringe capacitance, increase an electromechanical coupling coefficient, and block leaky waves, thereby increasing a Q value.

This invention relates to the field of TVS fabrication technology, specifically a low-voltage TVS with a deep trench structure, comprising a silicon wafer with a front electrode and a back electrode on two sides. The front electrode includes two independently arranged sub-electrodes, each with a deep trench structure between them. An N-doped region is provided between the sub-electrodes and the silicon wafer, with an isolation layer on the top and outer periphery of the N-doped region. A lead hole is located at the center of the isolation layer, and a metal layer is provided on the lead hole. This invention uses deep trench isolation technology to fabricate the TVS, which can significantly reduce the chip area and lower the PN junction side capacitance. Simultaneously, it uses LPCVD silicon nitride as a passivation layer, which has higher density and stronger protection against metal and sodium ion contamination, greatly improving the reliability of the packaged chip. Furthermore, the reverse leakage current (IR) of this invention is reduced, the PN junction capacitance is lowered, and the temperature coefficient and radiation resistance are improved.

This invention provides a prototype infrared detector with integrated metalens, its fabrication method, and an optoelectronic instrument. The prototype infrared detector with integrated metalens, its fabrication method, and the optoelectronic instrument of this invention offer an effective and feasible solution for the industrialization of infrared detectors with integrated metalens, and are beneficial to the development of optoelectronic devices. The prototype infrared detector with integrated metalens of this invention has the advantages of miniaturization and high performance, and is expected to be widely used in scenarios such as integrated miniaturized infrared detection and infrared detection in low-light environments.

This invention discloses a low-voltage, high-current electrolytic hydrogen production power supply system and control method based on a SiC and IGBT hybrid half-bridge, belonging to the field of electrolytic hydrogen production technology. The system includes: a hybrid half-bridge power module, used to convert the bus voltage into the total system output voltage and output IGBT branch current and SiC branch current under the control of a drive signal; a drive and isolation module, connected between the digital control and sampling module and the hybrid half-bridge power module, used to generate a drive signal based on a PWM signal and send the drive signal to the hybrid half-bridge power module; and a digital control and sampling module, used to sample key state variables of the system, calculate the PWM signal based on the key state variables, and send the PWM signal to the drive and isolation module. This invention compensates for the ripple of the low-frequency IGBT branch in real time through the high-frequency SiC branch, avoiding the problem of temporary ripple increase in traditional hybrid topologies during transients.

The invention provides a stacked transistor, a preparation method thereof, a device and electronic equipment. The method comprises the following steps: forming a first active structure and a second active structure which are stacked on a substrate; forming a first source-drain epitaxy of the first transistor based on the first active structure; reversing the wafer and thinning the substrate; forming a second source-drain epitaxy of the second transistor based on the second active structure; forming a second source drain metal, a second interlayer dielectric layer, a second gate structure and a second back-end interconnection layer of a second transistor based on the second active structure; a first interlayer dielectric layer and a first gate structure of the first transistor are formed based on the first active structure; forming a source-drain interconnection through hole and first source-drain metal of the first transistor in a source-drain region of the first transistor; the source-drain interconnection through hole penetrates through the first source-drain epitaxy and extends into the second source-drain epitaxy; the second source-drain epitaxy and the first source-drain epitaxy are electrically connected through a source-drain interconnection through hole; and forming a first back-end interconnection layer of the first transistor.