3565results about How to "Reduce capacitance" patented technology

A system and integrated circuit chips used in the system utilize a bus in the form of a ring to interconnect nodes of individual components for transfer of data and commands therebetween. An example system described is a memory having one or more re-programmable non-volatile memory cell arrays connected to each other and to a system controller by a ring bus.

A TANK filter is provided for a lead wire of an active medical device (AMD). The TANK filter includes a capacitor in parallel with an inductor. The parallel capacitor and inductor are placed in series with the lead wire of the AMD, wherein values of capacitance and inductance are selected such that the TANK filter is resonant at a selected frequency. The Q of the inductor may be relatively maximized and the Q of the capacitor may be relatively minimized to reduce the overall Q of the TANK filter to attenuate current flow through the lead wire along a range of selected frequencies. In a preferred form, the TANK filter is integrated into a TIP and/or RING electrode for an active implantable medical device.

Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP.

A semiconductor structure is provided that includes a V_t stabilization layer between a gate dielectric and a gate electrode. The V_t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the V_t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

An intensity distribution of an electric field of a high frequency power used for generating plasma is controlled by using an electrode made of a homogeneous material and a moving body. There is provided a plasma processing apparatus for introducing a processing gas into an evacuable processing chamber 100 and generating plasma by a high frequency power and performing a plasma process on a wafer W by the plasma. The plasma processing apparatus includes a dielectric base 105a having a multiple number of fine holes A; a varying member 200 as the moving body provided with a multiple number of rod-shaped members B capable of being inserted into and separated from the fine holes A; and a driving mechanism 215 configured to drive the varying member 200 to allow the rod-shaped members B to be inserted into and separated from the fine holes A.

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a "keyhole" shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. Furthermore, the first transistor provided in the driver circuit portion may include the oxide semiconductor film in which a first film and a second film are stacked, and the second transistor provided in the pixel portion may include the oxide semiconductor film which differs from the first film in the atomic ratio of metal elements.

A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate having source and drain regions commonly connected to the floating diffusion region. The gate has an intrinsic capacitance which, when the gate is activated, is added to the capacitance of the floating diffusion region, providing a low conversion gain readout. When the gate is off, the floating diffusion region capacitance is minimized, providing a high conversion gain readout. The gate may also be selectively switched to mid-level. At mid-level, a mid-level conversion gain, which is between the high and low conversion gains, readout is provided, but the gate still provides some capacitance to prevent the floating diffusion region from saturating.

A mutual capacitance touch screen and a combined mutual capacitance touch screen formed by the combination of mutual capacitance touch screens. A driving layer and a sensor layer are included, wherein the driving layer comprises driving electrodes distributed at intervals in the same plane; the sensor layer comprises sense electrodes distributed at intervals in the same plane; and the places where the sense electrodes are distributed in the sensor layer are just over against the intervals between the driving electrodes in the driving layer so that the driving electrodes and the sense electrodes together fill the touch area of the touch screen. The driving electrodes are not over against the sense electrodes in terms of space positions to increase the proportion of capacitance C_T to mutual capacitance C, wherein the capacitance C_T is formed between the driving electrodes and the top of the sense electrodes; consequently, the effective capacitivity of the mutual capacitance touch screen is effectively increased.

To form a sufficiently large storage capacitor, a liquid crystal display device includes a liquid crystal display panel having a first substrate, a second substrate, and a liquid crystal held between the first substrate and the second substrate, the liquid crystal display panel having multiple pixels arranged in matrix. The first substrate has, in a transmissive display area provided in each of the pixels, a laminated structure containing a first transparent electrode, a first insulating film, a second transparent electrode, a second insulating film, and a third transparent electrode which are laminated in this order. The first transparent electrode and the second transparent electrode are electrically insulated from each other and together form a first storage capacitor through the first insulating film, and the second transparent electrode and the third transparent electrode are electrically insulated from each other and together form a second storage capacitor through the second insulating film.

The present application discloses a semiconductor device formed on a SOI substrate which comprises a buried insulating layer and a semiconductor layer on the buried insulating layer and a method for manufacturing the same, wherein a fin of semiconductive material having two opposing sides perpendicular to a main surface of the SOI substrate is provided in the semiconductor layer, said semiconductor device comprising: a source region and a drain region provided at two ends of the fin respectively; a channel region provided at a central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, wherein the gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the SOI substrate. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

A controller for use with a multi-segment electroluminescent display 1. Control signals C1–CN control a plurality of half H-bridges H and Hc, the terminals of the half H-bridges being connected respectively to ground and to a high voltage DC supply 9. One of said half H-bridges provides a common output Vcommon and the remaining H-bridges provide drive voltages V1–VN for the segments of the display. The H bridges are driven by an oscillator 14 so that an AC voltage is selectively applied to the segments of the display. A power supply 24 provides a predetermined amount of power per unit area of the display. This is controlled by an area summation engine 22 having a segment data input, a segment counter and a memory containing area data corresponding to the segment(s) of the display. Based on the input from the segment data input, the area(s) of the segment(s) that are to be lit are obtained from the memory and summed to provide the total area to be lit. This is fed to the power supply 24, which then feeds the correct amount of power to display 1 via the half H-bridges.

In a pixel circuit 10, TFTs 12 and 13 are turned on while a TFT 14 is turned off, and a voltage (VDD+Vx) which depends on a threshold voltage Vth of a driving TFT 11 is read onto a data line Sj. Moreover, switches 21 and 22 in a source driver circuit are turned on, and a voltage Vx is held at a capacitor 26. Next, the TFT 13 is turned off, states of switches 21 to 24 are switched, and a voltage (Vdata+Vx) is applied to the data line Sj. Further, the TFT 12 is turned off while the TFT 14 is turned on. An amount of an electric current flowing through an organic EL element 15 after the turn-on of the TFT 14 is determined from the voltage (Vdata+Vx) of a gate terminal of the driving TFT 11. Thus, it is possible to efficiently utilize an amplitude of a data voltage and compensate variations in threshold voltage of the driving TFT 11 with high accuracy, without increasing a scale of the pixel circuit 10.