1047results about "Diode" patented technology

A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.

A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprising a body ring structure, forming a source and a body region in the epitaxial layer, forming an interlayer dielectric layer over the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure in the interlayer dielectric layer, forming a source contact connected to the source, and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact underneath the substrate.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is over the device layer. The metallization structure includes a conductive bridge portion electrically connecting two adjacent passive component units.

A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a protection diode. The protection diode includes a substrate, a gate, a first nanosheet layer, and a second nanosheet layer. The first nanosheet layer includes a heavily doped n-type epitaxial disposed over the substrate. Additionally, the first nanosheet layer is in contact with the gate. Further, the second nanosheet layer includes a heavily doped p-type epitaxial disposed over the substrate. Additionally, the second nanosheet layer is in contact with the gate. Further, the first nanosheet layer and the second nanosheet layer surround the gate.

An image sensor includes a first chip that includes a pixel region and a pad region, and a second chip that is in contact with one surface of the first chip and includes circuits that drive the first chip. The first chip includes a first substrate, an interlayer insulating layer disposed between the first substrate and the second chip, first interconnection lines disposed in the interlayer insulating layer, a conductive pad disposed in the pad region between the second chip and the first interconnection lines, and a recess region formed in the pad region that penetrates the first substrate and the interlayer insulating layer and exposes the conductive pad.

A semiconductor device includes a chip that has a first main surface on one side and a second main surface on the other side, an IGBT region provided in an inner portion of the first main surface, an outer peripheral region provided in a peripheral edge portion of the first main surface, a first conductivity type well region formed in a surface layer portion of the first main surface in the outer peripheral region so as to define the IGBT region, an insulating film that covers the well region, a well connection electrode embedded in the insulating film so as to be connected to the well region, and a second conductivity type cathode region formed in a surface layer portion of the second main surface in the outer peripheral region so as to oppose the well connection electrode, and that forms a diode with the well region.

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and / or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Unidirectional hybrid switch. At least one example is a method operating a hybrid switch, the method comprising: sensing a voltage across an upper terminal and a lower terminal of the hybrid switch, the hybrid switch is forward biased when the upper terminal has higher voltage, and the hybrid switch is reverse biased when the lower terminal has higher voltage; when the hybrid switch is forward biased, selectively conducting a forward current from the upper terminal to the lower terminal by sharing the forward current between a FET switch and a BJT switch, the selectively conducting when a control terminal is asserted; and when the hybrid switch is reversed biased, non-selectively conducting a reverse current from the lower terminal to the upper terminal.

Techniques and mechanisms for a DC-DC voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (ESD). In an embodiment, a protection circuit of the DC-DC voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. A voltage divider comprises capacitors which are coupled in series with each other between the first interconnect and the second interconnect. Control circuitry is coupled with the voltage divider, and is further coupled to automatically configure a first operational mode based on an ESD event. During the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. In another embodiment, a resistor-capacitor (RC) circuit automatically transitions the protection circuit from the first mode.

An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. A resistive element is coupled between the conductive contact and first circuitry. Second circuitry is coupled between the resistive element and the conductive contact. The second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. The resistive element is disposed in a first metallization layer of the IC device. A first dielectric layer is adjacent to the first metallization layer. A second metallization layer is adjacent to the first dielectric layer. A height of the first dielectric layer and the second metallization layer is a first distance. A zone overlaps the resistive element, and extends a second distance away from the resistive element. The zone is free of conductive material and the second distance is greater than the first distance.

A photodetection device according to one embodiment of the present disclosure includes: a semiconductor substrate having a first surface and a second surface that are opposed to each other and including a plurality of pixels arranged in an array in an in-plane direction; a first trench extending between the first surface and the second surface in an approximate middle of each of the plurality of pixels; a first semiconductor layer of a first conductivity type, the first semiconductor layer being provided in each of the plurality of pixels and extending between the first surface and the second surface; and a second semiconductor layer of a second conductivity type that is opposite to the first conductivity type, the second semiconductor layer being provided in each of the plurality of pixels and extending between the first surface and the second surface. When a reverse bias voltage is applied, a high electric field region is formed between the first semiconductor layer and the second semiconductor layer throughout between the first surface and the second surface.

The embodiment of the invention provides a radio frequency power supply and semiconductor process equipment, and the power supply comprises a power supply voltage control sub-module which is connected with a switching power supply module and is used for controlling the DC output voltage of the switching power supply module; the radio frequency control sub-module is connected with the radio frequency module and is used for controlling the power and the frequency of the radio frequency signal output by the radio frequency module; the power sampling sub-module is used for being connected with the radio frequency module and collecting a power feedback value of a radio frequency signal output by the radio frequency module; and the processor sub-module is connected with the power supply voltage control sub-module, the radio frequency control sub-module and the power sampling sub-module, and is used for outputting a control signal to the power supply voltage control sub-module and the radio frequency control sub-module based on the power feedback value and the frequency of the radio frequency signal, so that the radio frequency module outputs the required radio frequency signal. The embodiment of the invention can improve the output efficiency of the radio frequency module.

The invention provides an intelligent electronic switch, a chip and a device integrated with a diode function, and the intelligent electronic switch is provided with a mode selection end, a substrate switching circuit and a control circuit. The substrate switching circuit comprises a first switch and a second switch, the first switch is connected between the drain end and the substrate end of the power switch, and the second switch is connected between the substrate end and the source end of the power switch. When the mode selection end receives a first signal, the first switch is controlled to be switched off, the second switch is controlled to be switched on, and the switching state of the power switch is controlled based on a switching control signal received by the input end, so that the function of a high-side switch is realized; and the switching state of the power switch is controlled according to the voltage of the power supply end and the voltage of the load output end, so that the function of the diode is realized. The intelligent electronic switch can realize high-side application and diode application at the same time, and the application range of the intelligent electronic switch is expanded.

Image sensor structures are provided. In some embodiments, an image sensor structure is provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate and extending from the top surface to the bottom surface of the substrate. The image sensor structure further includes a first isolation structure extending from the top surface of the substrate to a middle portion of the substrate and a second isolation structure formed extending from the bottom surface of the substrate to the middle portion of the substrate and in contact with the first isolation structure. The image sensor structure further includes a gate structure overlapping the light-sensing region, the first isolation structure, and the second isolation structure and a cap layer overlapping the gate structure, the light-sensing region, the first isolation structure, and the second isolation structure in a top view.

A decrease in image quality is suppressed. A solid-state imaging apparatus according to an embodiment includes: a photoelectric conversion unit (PD) including a material having a smaller band gap energy than silicon; and a circuit board joined to the photoelectric conversion unit, the circuit board including: a pixel signal generation circuit that generates a pixel signal having a voltage value corresponding to a charge generated in the photoelectric conversion unit; and a thermometer circuit that detects a temperature of the circuit board.

An array substrate is disclosed. The array substrate includes a semiconductor layer integrated with a PIN photoelectric diode and an active area. The PIN photoelectric diode includes a P-type semiconductor area, an N-type semiconductor area, and an I-type semiconductor area defined between the P-type semiconductor area and the N-type semiconductor area. A gate electric current is introduced at a location corresponding to the I-type semiconductor area, so as to enhance light sensitivity.

The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.

A solid-state imaging apparatus includes a pixel circuit and a negative feedback circuit. The pixel circuit includes: a photodiode; a charge storage that holds a signal charge generated by the photodiode; an amplification transistor that outputs a pixel signal corresponding to the signal charge in the charge storage; a first reset transistor that resets the charge storage; a first storage capacitive element for holding a signal charge; and a first transistor that controls the connection between the charge storage and the first storage capacitive element. The negative feedback circuit negatively feeds back a feedback signal corresponding to a reset output of the amplification transistor to the charge storage via the first reset transistor.

In an ESD protection circuit using a nanosheet device, a first device structure constituting one of the anode and the cathode is opposed to a second device structure constituting the other in the Y direction, and to a third device structure constituting the other in the X direction. The first device structure includes a pad group of a first conductivity type, and the second and third device structures each include a pad group of a second conductivity type. The length of a range in the X direction in which the pad group of the first device structure is opposed to the pad group of the second device structure in the Y direction is greater than the length of a range in the Y direction in which it is opposed to the pad group of the third device structure in the X direction.

A gate-all-around transistor with hybrid conduction mechanism, including a GAA MOSFET, a second source region, and a second drain region. The GAA MOSFET includes a substrate, a first source region, and a first drain region. The first source region, the first drain region and the second drain region are doped with first ions, the second source region is doped with second ions. The second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region. The height of the second source region and the second drain region are not less than the height of the substrate between the first source region and the first drain region. It can realize the hybrid conduction of the gate channel diffusion drift current and the bottom channel band tunneling current to obtain better ultra-steep switching characteristics.

Provided is a power conversion device capable of observing a chip temperature with high accuracy without increasing a cost of the power conversion device mounted with a current sense element for observing a main current of a power device. A main control MOSFET 11, a current MOSFET 12, and a diode 13 connected to a source electrode 8 of the main control MOSFET 11 and a source electrode 9 of the current MOSFET 12 are mounted in a chip of a power device, a temperature measurement circuit 3 is connected to the source electrode 9 of the current MOSFET 12, and when the main control MOSFET 11 is in an off state, a forward current (If) is caused to flow through the diode 13, and an anode potential is observed to measure the chip temperature.

A memory structure includes insulating layers, gate layers, a first doping layer, second doping layers, third doping layers, a columnar channel, a first dielectric layer, second dielectric layers, and a third dielectric layer. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The second doping layers are in direct contact with the first doping layer to form tunnel diodes, in which the second doping layers and the insulating layers are alternately stacked. The third doping layers surround the columnar channel and are connected to the second doping layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the third doping layers and the gate layers. The third dielectric layer is between the columnar channel and the third doping layers.

A display device according to one or more embodiments includes a display device including a substrate including a display area and a non-display area, pixels in the display area above the substrate, an electrostatic discharge circuit in the non-display area above the substrate, a first line in the non-display area above the substrate, and configured to receive a first voltage, a second line in the non-display area above the substrate, and configured to receive a second voltage that is lower than the first voltage, a first connection line connected between the first line and the electrostatic discharge circuit under the first line on the substrate, and a second connection line connected between the second line and the electrostatic discharge circuit under the second line on the substrate.

An IGBT includes, in a single chip, an active region configured to conduct a forward load current between first and second load terminals at different sides of a semiconductor body. The active region is separated into at least first and second IGBT regions. At least 90% of the first IGBT region is configured to conduct, based on a first control signal, the forward load current. At least 90% of the second IGBT region is configured to conduct, based on a second control signal, the forward load current. A first MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the first IGBT region divided by a total lateral area of first IGBT region. A second MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the second IGBT region divided by a total lateral area of the second IGBT region. The second MOS-channel-conductivity-to-area-ratio amounts to less than 80% of the first MOS-channel-conductivity-to-area-ratio.

A semiconductor device having first and second conductivity regimes is provided. The device comprises a substrate body, a source formed along a first sidewall of the substrate body, and a drain formed along a second sidewall of the substrate body. The device comprises first and second delta layers disposed on the substrate body and separated by a gap. The first delta layer is in contact with the source and the second delta layer is in contact with the drain. The device comprises a cap disposed over the first and second delta layers. The device has the first conductivity regime responsive to a first voltage between the drain and the source and has the second conductivity regime responsive to a second voltage between the drain and the source.

A semiconductor device includes a substrate doped with first conductivity-type impurities, a first well doped with second conductivity-type impurities different from the first conductivity-type impurities, first active regions in the first well, the first active regions being doped with the first conductivity-type impurities and connected to a first pad through a first interconnection, second active regions outside the first well, the second active regions being doped with the second conductivity-type impurities and connected to a second pad through a second interconnection, third active regions around the first active regions in the first well and doped with the second conductivity-type impurities, and fourth active regions around the second active regions outside the first well and doped with the first conductivity-type impurities, wherein at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnection.

A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.

A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.

The invention discloses a radio frequency switch circuit with a cross feedback structure, a chip and electronic equipment. According to the radio frequency switch circuit, through the innovative cross feedback structure, the excellent technical effect is achieved, and particularly, the radio frequency switch circuit has outstanding performance in the aspects of high power bearing capacity and high harmonic processing capacity. Body end connecting diodes of the main circuit and the branch circuit are completely separated from source ends and drain ends of switching transistors in respective circuits, so that internal connection is fundamentally avoided, a nonlinear effect caused by parasitic diodes can be effectively reduced, and harmonic distortion is reduced. Therefore, the radio frequency switch circuit not only has high power bearing capacity, but also can bear large voltage fluctuation and maintain definition and accuracy of communication signals; the radio frequency switch circuit also has high harmonic wave processing capability, can effectively reduce harmonic wave interference caused by high-power signals, and meets strict requirements of a wireless communication system on the radio frequency switch circuit.