The invention provides a low-on-resistance
trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing
metal on the lower side surface of a
silicon carbide substrate, and forming a drain
metal layer; epitaxially growing on the upper side surface of the
silicon carbide substrate to form a drift layer; performing
ion implantation to form a low-resistance region; forming a
barrier layer,
etching, performing
ion implantation, and forming a P + well region, a P-type well region and an N-type source region; a
barrier layer is formed again, and the insulating medium is etched and deposited; forming a
barrier layer again,
etching and depositing
metal, and forming a suspension gate; forming a barrier layer again,
etching the barrier layer, and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the barrier layer is re-formed, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the P-type well region, metal is deposited, a source
electrode metal layer is formed, the barrier layer is removed, preparation is completed, gate-drain
capacitance is reduced, the switching speed of the device is increased, and switching loss is reduced.