143results about How to "Reduce gate-to-drain capacitance" patented technology

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (CGD) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.

This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.

A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.

This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by etching a bottom surface of the top portion of the trench then silicon etching to open a bottom portion of the trench with a slightly smaller width than the top portion of the trench. The method further includes a step of growing a thick oxide layer along sidewalls of the bottom portion of the trench thus forming a bird-beak shaped layer at an interface point between the top portion and bottom portion of the trench.