46 results about "Surface field" patented technology

The embodiment of the invention relates to a high-electron-mobility transistor and a preparation method thereof, and the high-electron-mobility transistor comprises a substrate; the heterojunction structure is located on the substrate and comprises a channel layer and a barrier layer which are sequentially stacked in the direction away from the substrate, and a two-dimensional electron gas channel is formed in the area, close to the barrier layer, of at least part of the channel layer; the source electrode and the drain electrode are distributed on the heterojunction structure at intervals; a gate layer on the heterojunction structure and between the source electrode and the drain electrode; the RESURF structure layer is located on the heterojunction structure and comprises a first structure part adjacent to the gate layer in the direction parallel to the plane where the substrate is located and a second structure part extending from the first structure part to the direction away from the gate layer; the thickness of the part, located between the first structure part and the channel layer, of the barrier layer is smaller than that of the part, located between the second structure part and the channel layer; therefore, the RESURF structure plays a better role in the device.

The invention relates to the technical field of SHJ battery microcrystal coating, in particular to a linear continuous coating method for improving the N-surface field passivation effect of a heterojunction battery, which comprises the following steps of: S1, presetting the temperature of a PECVD (Plasma Enhanced Chemical Vapor Deposition) cavity to 200-260 DEG C, and feeding an N-type monocrystalline silicon wafer into the PECVD cavity; s2, the phase angle of a pair of independent power supplies in the HPT power supply and the passivation power supply is set to be 0-180 degrees; s3, starting a first HPT power supply; s4, starting a first passivation power supply, and obtaining an N1 layer on the surface of the N-type monocrystalline silicon wafer; then repeating the steps to obtain an N2 layer and an N3 layer in sequence; step S9, the N-type monocrystalline silicon wafer with the passivated N layer is sent out of the PECVD cavity; according to the invention, an electromagnetic field is formed by using a power supply with a phase angle of 0-180 degrees, the deposition area is controlled while the coating rate is accelerated, and meanwhile, due to the fact that the deposition area is controlled by the electromagnetic field, the effect of N-layer gradient doping in a single cavity is realized.

The present application discloses a back junction solar cell and a preparation method therefor. The back junction solar cell comprises: a P-type silicon substrate; a tunneling oxide layer, an N-type doped silicon layer and a first passivation anti-reflection layer which are sequentially arranged on a first main surface of the P-type silicon substrate in a stacked manner from inside to outside; a back electrode which penetrates through the first passivation anti-reflection layer to be electrically connected with the N-type doped silicon layer; a P+ local front surface field formed by Group III elements and a front electrode formed by Group III elements arranged on a second main surface of the P-type silicon substrate, wherein the front electrode is connected to the local front surface field, and the position of the local front surface field corresponds to the position of the front electrode; a second passivation anti-reflection layer formed on the second main surface of the P-type silicon substrate in a region where the front electrode is not arranged and on the front and lateral sides of the front electrode.

A transistor device includes a semiconductor substrate having a first major surface and one or more transistor cells. Each transistor cell may include a columnar trench in the semiconductor substrate. The columnar trench includes a field dielectric, base, and a side wall. The side wall may extend from the base to the first major surface. The field dielectric may line the base and side wall of the columnar trench. A first thickness of the field dielectric at a first distance from the base is smaller than a second thickness of the field dielectric at a second distance from the base. The first distance is greater than the second distance. A columnar field plate with a cavity may be arranged in the columnar trench. A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance.

The present application relates to a kind of elliptical chamfer variable-diameter cathode lead structure inhibiting backflow diode and inhibiting diode backflow method, belong to vacuum electron technology field, can effectively reduce the surface field intensity of cathode lead, inhibit field electron emission and delay the ion movement of zero field region to cathode lead.It includes cathode, cathode lead, anode in inhibiting backflow diode.The cathode lead is variable-diameter structure, non-variable-diameter part D is located at both ends, variable-diameter part E is located in the middle, variable-diameter part E is the same throughout radius, chamfer part F adopts elliptical chamfer structure.Non-variable-diameter part D radius is the same with cathode radius, and variable-diameter part E radius is less than cathode radius.The inhibiting diode backflow method includes: reducing the position radius of cathode lead, realizes the optimal cathode lead surface electric field;Both sides of the position radius reduction are smoothly transitioned back to original size, so that the surface electrostatic field of cathode lead position possibly bombarded by anode ion is further reduced.

Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.

The invention relates to a transistor device with a metal backside field plate. Using various techniques, a metal backside field plate is formed at the end of the process. In one example, a GaN layer is grown, the HEMT is fabricated, and the substrate is thinned. A through-hole is formed through the thinned substrate and GaN epitaxy, reaching the underside of the source electrode, and then a metal back surface field plate is deposited. In another example, a recess for the backside field plate is formed completely through the thickness of the substrate, a via is formed through GaN to the source electrode, and then a metal backside field plate is deposited in the recess.

A panel including at least one solar cell having a cell comprised of gallium arsenide (GaAs) or indium gallium arsenide (InGaAs) with a back surface field (BSF) comprised of aluminum gallium arsenide (AlGaAs) or indium aluminum gallium arsenide (InAlGaAs) p-type doped for enhanced operation of the solar cell at temperatures less than −50° C. In one example, the back surface field comprises AlxGa1-xAs or In0.01AlxGa1-xAs, wherein x is less than about 0.8, for example, 0.2. The back surface field may be p-type doped with zinc (Zn) or carbon (C).

This invention provides a fully isolated LDMOS structure and its fabrication method. A P-type buried layer is formed below the N-type drift region, and an STI layer is formed in the N-type drift region between the N-type drain region and the P-type body region. This facilitates the high voltage withstand capability of the device through the vertical P-type buried layer and the surface STI field plate. Furthermore, the distance between the N-type drift region and the N-type isolation ring is increased laterally, forming a P-type well region between them. The P-type buried layer and the P-type well region achieve isolation of the drain voltage, avoiding latch-up effects and other reliability issues caused by electron injection into the substrate. In addition, the P-type epitaxial layer is formed in stages, which allows for precise control of the depth, doping concentration, and implantation energy of the P-type buried layer. By adjusting the lateral layout size and the dosage and energy of the vertical ion implantation, a fully isolated LDMOS structure in the medium-high voltage range of 60V~100V can be achieved.

The present application provides a method, medium and electronic device for automatic calibration of a phased array based on an aperture field. The calibration method comprises: obtaining configuration information, the configuration information comprising a target amplitude, a target phase and a channel coordinate of a sub-array of the phased array mid-frequency point, each channel of the sub-array comprising a number of the frequency points; obtaining a first amplitude to be calibrated and a first phase to be calibrated of the frequency point, the first amplitude to be calibrated and the first phase to be calibrated are related to the sub-array channel coordinates; obtaining a phase shift code and an attenuation code of the frequency point based on a preset attenuation step, the first amplitude to be calibrated, the target amplitude, a preset phase shift step, the first phase to be calibrated and the target phase. The calibration method can realize automatic calibration of the amplitude and phase of the mid-frequency point of the phased array, thereby improving the calibration efficiency of the amplitude and phase of the frequency point, and improving the applicability in the calibration scenario of the phased array.

The present invention relates to a laterally diffused metal oxide semiconductor device and a method for manufacturing the same, comprising: a substrate; a body region of a first conductivity type formed in the substrate; a drift region of a second conductivity type formed in the substrate and adjacent to the body region; a field plate structure formed on the drift region, wherein the lower surface of the field plate structure at one end close to the body region is flush with the upper surface of the substrate and has an upwardly extending inclined surface, the lower surface of the field plate structure at one end away from the body region is lower than the upper surface of the substrate, and the thickness of the field plate structure gradually increases from the end close to the body region to the end away from the body region to a preset value; and a drain region of the second conductivity type formed on the upper surface of the drift region and in contact with the end of the field plate structure away from the body region. While not increasing the length of the field plate structure where the lower surface is lower than the upper surface of the substrate, a field plate structure with gradually increasing thickness is formed at the position of the JEFET region, thereby improving the reliability of the device.

The invention provides a low-sidelobe waveguide slot antenna design method, which comprises the following steps of: firstly, obtaining antenna theoretical aperture field distribution according to the number of antenna slots and target sidelobe level, and secondly, determining a slot conductance function, namely a relationship between slot parameters and normalized conductance; and on the basis of fully considering mutual coupling between different slot units of the array and an array edge effect, through multiple times of iterative design, antenna aperture field distribution approaches theoretical aperture field distribution, and a directional diagram sidelobe level reaches a target, so that the design of the low-sidelobe waveguide slot array antenna is realized. The antenna can be in the form of a waveguide slot traveling wave array, a standing wave array and the like, and the slotted unit can be a waveguide wide-edge slotted unit or a waveguide narrow-edge slotted unit; the method is especially suitable for the design of an electrically large waveguide slot array antenna, the design time can be saved, and the design efficiency can be improved; the method can also be expanded to antenna array design with any aperture field distribution.

The invention discloses a dielectric material surface charge quantitative measurement method and system based on a KPFM-AM mode, and relates to the fields of friction catalysis technologies, friction nano-generators and the like. According to the method, the incidence relation between the surface potential and the surface charge density is deduced by deeply analyzing the vibration characteristics of the probe driven by the electric field force. On the basis, a series of finite element simulation is carried out by using COMSOL software, and the actual measurement process of the KPFM is simulated: on one hand, the applicability of a theoretical formula in an infinite uniform charged surface scene is verified, and on the other hand, the influence rule of a limited surface or a surface with non-uniform charge distribution on a surface potential measurement result is explored. Meanwhile, simulation analysis is conducted on the surface potential distribution of the point charges, and a fitting formula based on a Lorentz function is provided and used for accurate calculation of the surface potential distribution. Finally, on the basis of the theory and simulation results, a special program capable of inversely calculating the surface charge distribution according to the surface potential distribution is developed, and an important theoretical support and a practical tool are provided for efficient and accurate characterization of dielectric material surface electrical properties.

The invention provides a microwave feed-in device which is used for sending microwaves to microwave equipment. Because the field intensity of the inner surface of the processing cavity is relatively strong, the dielectric window is moved away from the inner surface of the processing cavity, so that breakdown damage on the dielectric window is avoided. Particularly, when the microwave equipment is in a no-load state, the dielectric window sheet is arranged at the lowest position of an electric field of the feed-in waveguide, so that the dielectric window sheet is effectively protected; a hole structure is arranged between the dielectric window sheet and the inner surface of the processing cavity, so that impurities and water deposited on the dielectric window sheet can be conveniently cleaned; the hole structure is formed by the two metal strips, so that the cost is reduced, and the dielectric window sheet and the hole structure can be conveniently replaced outside the processing cavity; a matching circuit is formed by a matching structure which is very short in the axis direction of the feed-in waveguide, impedance matching of a microwave source is achieved, and the energy efficiency of microwave equipment is improved. The invention can be used in various microwave processing equipment, especially in a bottom-fed microwave tunnel furnace, and is used for heating, drying, sintering and the like of various materials.

The invention discloses a switch cabinet insulation failure probability evaluation method and system and a switch cabinet, and the method comprises the steps: building a three-dimensional finite element electric field simulation model based on the whole switch cabinet, and obtaining the highest surface field intensity of different positions in the switch cabinet through simulation; respectively acquiring field intensity margin coefficients corresponding to different positions according to the control field intensity in the switch cabinet; the field intensity margin coefficients of different positions are corrected by combining the operating age limit of an insulating part in the switch cabinet, and the corrected field intensity margin coefficients are obtained; according to the size of the field intensity margin coefficients of different positions in the switch cabinet after correction, arrays representing different risk states are constructed; applying an insulation failure probability equation set to respectively obtain insulation failure probabilities corresponding to the field intensity margin coefficients contained in different arrays; and obtaining the insulation failure probability of the whole switch cabinet according to the insulation failure probabilities corresponding to the field intensity margin coefficients in the different arrays. The method overcomes the defect that an existing method does not consider the aging characteristic of the insulating part.

This invention provides a non-contact device and method for assessing the surface characteristics of insulating materials, comprising: a housing, an equalizing element, and a ground electrode; the housing contains insulating oil to simulate the internal operating environment of power equipment; the equalizing element and the ground electrode are immersed in the insulating oil and are arranged vertically opposite each other, forming a surface discharge region between them; the equalizing element has a cavity containing a high-voltage lead, the lower end of which has a hanging part for suspending the insulating sample to be tested, such that the main body of the insulating sample is located on the central axis between the equalizing element and the ground electrode, and the lower end of the insulating sample is in contact with the ground electrode. This invention enables the surface discharge to develop stably along the surface of the insulating sample, effectively suppressing preferential breakdown of oil gaps, thereby simulating low surface field strength conditions under high voltage conditions, accurately and reliably reflecting the surface discharge characteristics of the insulating sample, and significantly improving the authenticity and repeatability of the test results.

A transistor device comprising a semiconductor substrate with a first primary surface and one or more transistor cells. Each transistor cell may include a columnar trench formed in the semiconductor substrate. The columnar trench comprises a field dielectric, a base, and a side wall. The side wall may extend from the base to the first primary surface. The field dielectric may line the base and the side wall of the columnar trench. The first thickness of the field dielectric at a first distance from the base is less than the second thickness of the field dielectric at a second distance from the base. The first distance is greater than the second distance. A columnar field plate may be arranged in the columnar trench. The first perimeter of the columnar field plate at the first distance is greater than the second perimeter of the columnar field plate at the second distance.The columnar field plate encompasses a cavity.

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a super junction terminal structure and a manufacturing method. By introducing the surface field limiting rings and the field plates and adopting a special design scheme for the distribution of the field limiting rings and the field plates, the area utilization rate of a terminal region can be effectively improved, and the influence of super junction charge imbalance on the super junction columns is weakened while the high breakdown voltage level is maintained; the terminal can effectively inhibit the adverse effect caused by the charge effect of the passivation layer, and the reliability of the terminal is greatly improved.

The utility model provides a terminal structure and a semiconductor device, and the terminal structure comprises a substrate which is provided with a first surface and a second surface which are opposite to each other; the field limiting rings are located in the substrate at intervals, each field limiting ring is provided with a third surface located on the side, close to the second surface, of the first surface, the field limiting rings and the second surface are located on the same side of the first surface, and each of the field limiting rings and the second surface is provided with a first orthographic projection located in the first surface; part of the field plate is located on the second surface and makes contact with the field limiting ring, the field plate is provided with a second orthographic projection on the first surface, and the second orthographic projection covers at least one first orthographic projection. The first orthographic projection is located in the second orthographic projection, so that the electric field of at least one field limiting ring can be shielded, the width of the field limiting ring with the shielded electric field can be wider without the influence of the electric field, and the voltage endurance capability is further improved. With the terminal structure, the problem of insufficient voltage endurance capability of the SiC MOSFET in the prior art is solved.

Disclosed are XLPE sheath for reducing the surface field intensity of IGBT in high altitude area and a preparation method thereof. In the method, a predetermined mass of LDPE raw material is weighed; the LDPE raw material and 2wt% of crosslinking agent DCP are added into a bottle, and the granules are placed into a mold padded with polyester film and sent into a flat vulcanizing machine to obtain a sheet-shaped LDPE sample; the sheet-shaped LDPE sample is vulcanized for 10 minutes to complete the crosslinking process; after cooling, the sheet-shaped LDPE sample is placed into a 70 DEG C constant-temperature oven for degassing for 24h to obtain a finished XLPE film; the finished XLPE film is cut and placed into an oven at 120 DEG C to complete softening, and is adhered to the weak insulation position of the IGBT; after cooling, the finished XLPE protective layer is obtained. The thickness of the XLPE film protective layer is quantitatively changed by regulating the mold size, and the coverage area of the XLPE protective layer on the outer surface of the IGBT is flexibly controlled.

In a solar cell, the back surface of a substrate thereof is provided with alternately distributed emitter zones and back surface field zones. An emitter is formed in each emitter zone, and the emitters are made of boron-doped monocrystalline silicon. A back surface field is formed in each back surface field zone; the back surface fields comprise tunneling oxide layers and polycrystalline silicon layers in stacked distribution, the polycrystalline silicon layers being made of phosphorus-doped polycrystalline silicon, and the tunneling oxide layers being located between a polycrystalline silicon layer and a polycrystalline silicon layer. Positive electrodes are electrically connected to the emitters, and negative electrodes are electrically connected to the back surface fields. In the described solar cell, the light-receiving area of the front surface can be expanded and the recombination rate of electron-hole pairs can be reduced, thereby effectively improving the photoelectric conversion efficiency of the solar cell.

The invention relates to a semiconductor device. A transistor device includes: a semiconductor substrate having a first main surface; and one or more transistor cells. Each transistor cell may include a columnar trench formed in a semiconductor substrate. The columnar trench includes a field dielectric, a substrate, and sidewalls. A sidewall may extend from the base to the first major surface. A field dielectric may lay over the substrate and sidewalls of the columnar trench. A first thickness of the field dielectric at a first distance from the substrate is less than a second thickness of the field dielectric at a second distance from the substrate. The first distance is greater than the second distance. A columnar field plate may be disposed in the columnar trench. A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance. The columnar field plate includes a cavity.

The invention discloses a compact range dead zone amplitude and phase testing method based on a reference target method, and belongs to the technical field of microwave measurement. According to the method, a mathematical relationship between a target scattering field and a target surface induction current is established, a conductor rod is used as a reference target, and one-dimensional transverse distribution of any target is represented by rotating the conductor rod around the center of the reference target. According to the compact range quiet zone amplitude and phase testing method based on the reference target method, radar cross sections RCS of a reference target under different azimuth angles are measured, compact range quiet zone amplitude and phase distribution is obtained through data processing inversion, and dependence on a complex and time-consuming probe scanning device is not needed. Wherein the reference target is a metal rod or a cylinder of which the length is greater than the range of the quiet zone, and the surface field distribution of the reference target and the RCS essentially form a Fourier transform relationship. The method effectively simplifies the test process of the quiet zone, improves the test efficiency, and is suitable for rapid and accurate evaluation of the performance of the compact range quiet zone.

This application discloses a semiconductor device and its manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes an active region and a termination region; the termination region surrounds the active region; the termination region includes a semiconductor body configured with a first conductivity type; it also includes a first region configured with a second conductivity type and located on a first surface; the first surface has a plurality of trenches arranged at intervals; the vertical projection of the plurality of trenches on the first surface lies within the vertical projection of the first region on the first surface; it also includes an isolation layer disposed within the trenches; the semiconductor body further includes a plurality of field limiting rings configured with a second conductivity type and located on the first surface; a field oxide layer located on the first surface; a field plate layer located on the side of the field oxide layer away from the first surface; a gate electrode located on the side of the field plate layer away from the field oxide layer; a source electrode; and a drain electrode. The technical solution of this application embodiment can improve the avalanche tolerance of the semiconductor device and enhance its performance.

The invention relates to a pre-twisted spacer corona discharge degree estimation method and system. The method comprises the following steps: acquiring parameters of the number of pre-twisted wires, the diameter of the pre-twisted wires and the diameter of a split conductor; obtaining the ratio of the average maximum electric field intensity of the surface of the pre-twisted spacer to the average maximum electric field intensity of the surface of the split conductor; obtaining the average maximum electric field intensity on the surface of the split conductor; obtaining the average maximum electric field intensity of the surface of the pre-twisted spacer; calculating the ratio of the average maximum electric field intensity to the corona onset electric field intensity on the surface of the pre-twisted spacer to obtain the corona discharge degree of the pre-twisted spacer; according to the estimation formula of the average maximum field intensity on the surface of the pre-twisted spacer, the field intensity on the surface of the pre-twisted spacer can be reduced by means of increasing the number and diameter of the pre-twisted wires and the like, so that the corona discharge level is reduced, and the electromagnetic environment problem caused by the corona discharge level is controlled.

To improve the characteristics of a semiconductor device including a power MOSFET.SOLUTION: In a lateral reduced surface field (RESURF) semiconductor device 100, a drift region 12 is configured to have a dopant concentration that varies multiple times such that, in the region extending from under a gate electrode 24 to a drain region 16b, there are a low dopant region having a dopant concentration that is completely depleted when a first voltage lower than a rated operating voltage is applied, and a high dopant region having a dopant concentration that is not depleted when the first voltage is applied.SELECTED DRAWING: Figure 1

The present invention discloses a three-phase three-pillar insulator for a three-phase common-box compact GIS / GIL, comprising an insulator belly and a conductor coating area and legs arranged on the insulator belly, the conductor coating area and the legs are alternately distributed in the circumferential direction of the insulator belly, a metal insert is arranged in the leg, the conductor coating area has an axial width greater than the axial thickness of the insulator belly, the conductor coating area and the insulator belly have a smooth transition through a first chamfer, the width of the legs is greater than the axial thickness of the insulator belly, the legs and the insulator belly have a smooth transition through a second chamfer, and the portion of the insulator belly between the legs and the conductor coating area has a smooth transition through a first arc segment, and the first arc segment is a concave arc segment. The surface composite field intensity, tangential field intensity and metal insert surface field intensity of the three-phase three-pillar insulator of the present invention can be greatly reduced, meeting the control value requirements in the project, thereby improving the stability of the insulator under long-term operation.

[Task] Providing a pressure sensing field that enables the reduction of costs required for a flexible printed circuit (FPC) and achieves uniformity of a pressure force sensing signal in the plane, even when a field size is large. [Solution] A pressure sensing field 1 of the present invention includes a surface field 2 and a strain sensor 3, which is arranged in a strip shape along one side of the surface field 2 on a rear surface of the surface field 2. The strain sensor 3 includes sensitive units R1, R2, and R3 at an intermediate section and both end sections in a longitudinal direction. The adjacent sensitive units, i.e., sensitive units R1 and R2 and sensitive units R2 and R3, are connected in series by a wiring line 31.

The present invention is directed to devices and systems for rapidly producing high resolution images of magnetic fields in a sample. The devices and systems employ diamond chips with color centers that fluoresce in the presence of magnetic fields. The high resolution is due to the use of one of three excitation methods. The first method employs modulation of an acoustic surface wave, which increases / decreases the sensitivity of the color centers to magnetic fields. The second and third methods employ arrays of magnetic field coils and electrode pairs, respectively, which again increase / decrease the sensitivity of the color centers to magnetic fields. The color centers are preferably nitrogen vacancies in the diamond chips.