382 results about "Surface field" patented technology

One embodiment of the present invention provides a back junction solar cell. The solar cell includes a base layer, a quantum-tunneling-barrier (QTB) layer situated below the base layer facing away from incident light, an emitter layer situated below the QTB layer, a front surface field (FSF) layer situated above the base layer, a front-side electrode situated above the FSF layer, and a back-side electrode situated below the emitter layer.

Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can be completely suppressed in LDD-HEMTs with no significant degradation in gains and cutoff frequencies.

Formation of a solar cell device from upgraded metallurgical grade silicon which has received at least one defect engineering process and including a low contact resistance electrical path. An anti-reflective coating is formed on an emitter layer and back contacts are formed on a back surface of the bulk silicon substrate. This photovoltaic device may be fired to form a back surface field at a temperature sufficiently low to avoid reversal of previous defect engineering processes. The process further forms openings in the anti-reflective coating and a low contact resistance metal layer, such as nickel layer, over the openings in the anti-reflective coating. The process may anneal the low contact resistance metal layer to form n-doped portion and complete an electrically conduct path to the n-doped layer. This low temperature metallization (e.g., <700° C.) supports the use of UMG silicon for the solar device formation without the risk of reversing earlier defect engineering processes.

An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (C_GD) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.

Process for incorporating a back surface field into a silicon solar cell by depositing a layer of aluminium on the rear surface of the cell, sintering the aluminium at a temperature between 700 and 1000° C., exposing the cell to an atmosphere of a compound of Group V element and diffusing at a temperature of between 950 and 1000°C. so as to dope exposed p-type silicon surfaces with the Group V element. The step of exposing the cell to an atmosphere of a compound of a Group V element is carried separately from the step of sintering the aluminium layer, and subsequent to the step of depositing a layer of aluminium on the rear surface of the cell.

The invention provides a method for preparing an N-type crystalline silicon solar cell with aluminum-based local emitters on the back side. The method comprises the following steps: firstly, selecting N-type silicon wafers to carry out the surface-textured etching process; further forming a front surface field through phosphorous diffusion; depositing a passivating film on the front surface after the phosphorosilicate glass is formed during the removal of diffused phosphorous; carrying out the back-side chemical polishing process on the silicon wafers to remove the N+ layer formed on the back side during the phosphorous diffusion; then, sequentially printing an aluminum layer or a silver-aluminum layer through the passivating film deposited on the back side, local holes or grooves on the back side and screens on the back side; then, printing silver paste on the front surface; and finally, carrying out the one-step sintering process to form a local P+ layer on the back side and allowing the P+ layer to coming into ohmic contact with the electrodes on the front and back surfaces. By using the N-type substrate, forming local aluminum-based P-N junctions on the back side and further using the back-side chemical polishing process to remove the edge junctions, the invention can substitute for the conventional stacking-type plasma etching process, simplify the technological procedures and further bring a series of performance improvement to cells.

The invention discloses a manufacture method of a selective front surface field N-type solar cell, which is characterized in that a back surface p-n junction is formed by utilizing an aluminum-silicon alloying process and a high-temperature boron diffusion process, a front surface lightly doped N-type layer is formed by high-temperature phosphorous diffusion, a front surface local heavily doped N-type region is formed by laser doping, and a front electrode is manufactured on the heavily doped N-type region by utilizing a chemical plating method or an electroplating method. Compared with the traditional manufacture process, the invention has the advantages of simple process and low cost and does not need secondary contraposition.

A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial layer formed on the conductive buried layer; a first conductive well formed within the conductive epitaxial layer; a second conductive well formed within the second conductive epitaxial layer, on both sides of the first conductive well; a second conductive drift region formed in predetermined portions on the first and the second conductive well; and a lateral double diffused MOS transistor formed in the second conductive drift region. The breakdown voltage of the power device is controlled according to a distance between the first conductive well and the second conductive buried layer.

A system that transitions from freeform camera motion to surface following motion as a surface of an object is approached by clipping the vectors for closest point and look-at point. When the surface is reached and while following the surface the user can designate an up model that sets an up vector to conform the view to a users expectations while the system operates using a local up vector for computations. A restricted surface field of view along with an obstacle field of view can be used by the system to allow the view to traverse cavities and maintain a specified surface following distance from an obstacle, from a wall and from a floor.

A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having a same dopant conductivity as the substrate. Methods are also disclosed.

A semiconductor device is formed on a low cost substrate 312 onto which is deposited a metal film 314 that serves as an intermediate bonding layer with a transferred film 324 of semiconducting material from a bulk semiconductor substrate 322. The metal film forms an intermetallic compound such as a silicide 316 and functions as a bonding agent between the low cost substrate and the semiconducting substrate, as a back surface field for reflection of minority carriers, and as a textured optical reflector of photons. The silicide also forms a low resistivity back-side ohmic contact with the semiconductor layer. This results in a low cost, flexible, high efficiency, thin film solar cell device.

In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type is formed over the substrate. A body region of the first conductivity type is formed in the drift region. A source region of the second conductivity is formed in the body region. A gate extends over a surface portion of the body region and overlaps each of the source region and the body region such that the surface portion of the body region forms a channel region of the transistor. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the source region a first predetermined distance. A first buried layer of the first conductivity type extends into the substrate and the drift region. The first buried layer laterally extends between the source and drain regions.

Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage.