24 results about "Surface field" patented technology

The present application discloses a back junction solar cell and a preparation method therefor. The back junction solar cell comprises: a P-type silicon substrate; a tunneling oxide layer, an N-type doped silicon layer and a first passivation anti-reflection layer which are sequentially arranged on a first main surface of the P-type silicon substrate in a stacked manner from inside to outside; a back electrode which penetrates through the first passivation anti-reflection layer to be electrically connected with the N-type doped silicon layer; a P+ local front surface field formed by Group III elements and a front electrode formed by Group III elements arranged on a second main surface of the P-type silicon substrate, wherein the front electrode is connected to the local front surface field, and the position of the local front surface field corresponds to the position of the front electrode; a second passivation anti-reflection layer formed on the second main surface of the P-type silicon substrate in a region where the front electrode is not arranged and on the front and lateral sides of the front electrode.

The present application relates to a kind of elliptical chamfer variable-diameter cathode lead structure inhibiting backflow diode and inhibiting diode backflow method, belong to vacuum electron technology field, can effectively reduce the surface field intensity of cathode lead, inhibit field electron emission and delay the ion movement of zero field region to cathode lead.It includes cathode, cathode lead, anode in inhibiting backflow diode.The cathode lead is variable-diameter structure, non-variable-diameter part D is located at both ends, variable-diameter part E is located in the middle, variable-diameter part E is the same throughout radius, chamfer part F adopts elliptical chamfer structure.Non-variable-diameter part D radius is the same with cathode radius, and variable-diameter part E radius is less than cathode radius.The inhibiting diode backflow method includes: reducing the position radius of cathode lead, realizes the optimal cathode lead surface electric field;Both sides of the position radius reduction are smoothly transitioned back to original size, so that the surface electrostatic field of cathode lead position possibly bombarded by anode ion is further reduced.

Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.

The invention relates to a transistor device with a metal backside field plate. Using various techniques, a metal backside field plate is formed at the end of the process. In one example, a GaN layer is grown, the HEMT is fabricated, and the substrate is thinned. A through-hole is formed through the thinned substrate and GaN epitaxy, reaching the underside of the source electrode, and then a metal back surface field plate is deposited. In another example, a recess for the backside field plate is formed completely through the thickness of the substrate, a via is formed through GaN to the source electrode, and then a metal backside field plate is deposited in the recess.

A panel including at least one solar cell having a cell comprised of gallium arsenide (GaAs) or indium gallium arsenide (InGaAs) with a back surface field (BSF) comprised of aluminum gallium arsenide (AlGaAs) or indium aluminum gallium arsenide (InAlGaAs) p-type doped for enhanced operation of the solar cell at temperatures less than −50° C. In one example, the back surface field comprises AlxGa1-xAs or In0.01AlxGa1-xAs, wherein x is less than about 0.8, for example, 0.2. The back surface field may be p-type doped with zinc (Zn) or carbon (C).

This invention provides a fully isolated LDMOS structure and its fabrication method. A P-type buried layer is formed below the N-type drift region, and an STI layer is formed in the N-type drift region between the N-type drain region and the P-type body region. This facilitates the high voltage withstand capability of the device through the vertical P-type buried layer and the surface STI field plate. Furthermore, the distance between the N-type drift region and the N-type isolation ring is increased laterally, forming a P-type well region between them. The P-type buried layer and the P-type well region achieve isolation of the drain voltage, avoiding latch-up effects and other reliability issues caused by electron injection into the substrate. In addition, the P-type epitaxial layer is formed in stages, which allows for precise control of the depth, doping concentration, and implantation energy of the P-type buried layer. By adjusting the lateral layout size and the dosage and energy of the vertical ion implantation, a fully isolated LDMOS structure in the medium-high voltage range of 60V~100V can be achieved.

The invention discloses a dielectric material surface charge quantitative measurement method and system based on a KPFM-AM mode, and relates to the fields of friction catalysis technologies, friction nano-generators and the like. According to the method, the incidence relation between the surface potential and the surface charge density is deduced by deeply analyzing the vibration characteristics of the probe driven by the electric field force. On the basis, a series of finite element simulation is carried out by using COMSOL software, and the actual measurement process of the KPFM is simulated: on one hand, the applicability of a theoretical formula in an infinite uniform charged surface scene is verified, and on the other hand, the influence rule of a limited surface or a surface with non-uniform charge distribution on a surface potential measurement result is explored. Meanwhile, simulation analysis is conducted on the surface potential distribution of the point charges, and a fitting formula based on a Lorentz function is provided and used for accurate calculation of the surface potential distribution. Finally, on the basis of the theory and simulation results, a special program capable of inversely calculating the surface charge distribution according to the surface potential distribution is developed, and an important theoretical support and a practical tool are provided for efficient and accurate characterization of dielectric material surface electrical properties.

The invention provides a microwave feed-in device which is used for sending microwaves to microwave equipment. Because the field intensity of the inner surface of the processing cavity is relatively strong, the dielectric window is moved away from the inner surface of the processing cavity, so that breakdown damage on the dielectric window is avoided. Particularly, when the microwave equipment is in a no-load state, the dielectric window sheet is arranged at the lowest position of an electric field of the feed-in waveguide, so that the dielectric window sheet is effectively protected; a hole structure is arranged between the dielectric window sheet and the inner surface of the processing cavity, so that impurities and water deposited on the dielectric window sheet can be conveniently cleaned; the hole structure is formed by the two metal strips, so that the cost is reduced, and the dielectric window sheet and the hole structure can be conveniently replaced outside the processing cavity; a matching circuit is formed by a matching structure which is very short in the axis direction of the feed-in waveguide, impedance matching of a microwave source is achieved, and the energy efficiency of microwave equipment is improved. The invention can be used in various microwave processing equipment, especially in a bottom-fed microwave tunnel furnace, and is used for heating, drying, sintering and the like of various materials.

This invention provides a non-contact device and method for assessing the surface characteristics of insulating materials, comprising: a housing, an equalizing element, and a ground electrode; the housing contains insulating oil to simulate the internal operating environment of power equipment; the equalizing element and the ground electrode are immersed in the insulating oil and are arranged vertically opposite each other, forming a surface discharge region between them; the equalizing element has a cavity containing a high-voltage lead, the lower end of which has a hanging part for suspending the insulating sample to be tested, such that the main body of the insulating sample is located on the central axis between the equalizing element and the ground electrode, and the lower end of the insulating sample is in contact with the ground electrode. This invention enables the surface discharge to develop stably along the surface of the insulating sample, effectively suppressing preferential breakdown of oil gaps, thereby simulating low surface field strength conditions under high voltage conditions, accurately and reliably reflecting the surface discharge characteristics of the insulating sample, and significantly improving the authenticity and repeatability of the test results.

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a super junction terminal structure and a manufacturing method. By introducing the surface field limiting rings and the field plates and adopting a special design scheme for the distribution of the field limiting rings and the field plates, the area utilization rate of a terminal region can be effectively improved, and the influence of super junction charge imbalance on the super junction columns is weakened while the high breakdown voltage level is maintained; the terminal can effectively inhibit the adverse effect caused by the charge effect of the passivation layer, and the reliability of the terminal is greatly improved.

Disclosed are XLPE sheath for reducing the surface field intensity of IGBT in high altitude area and a preparation method thereof. In the method, a predetermined mass of LDPE raw material is weighed; the LDPE raw material and 2wt% of crosslinking agent DCP are added into a bottle, and the granules are placed into a mold padded with polyester film and sent into a flat vulcanizing machine to obtain a sheet-shaped LDPE sample; the sheet-shaped LDPE sample is vulcanized for 10 minutes to complete the crosslinking process; after cooling, the sheet-shaped LDPE sample is placed into a 70 DEG C constant-temperature oven for degassing for 24h to obtain a finished XLPE film; the finished XLPE film is cut and placed into an oven at 120 DEG C to complete softening, and is adhered to the weak insulation position of the IGBT; after cooling, the finished XLPE protective layer is obtained. The thickness of the XLPE film protective layer is quantitatively changed by regulating the mold size, and the coverage area of the XLPE protective layer on the outer surface of the IGBT is flexibly controlled.

In a solar cell, the back surface of a substrate thereof is provided with alternately distributed emitter zones and back surface field zones. An emitter is formed in each emitter zone, and the emitters are made of boron-doped monocrystalline silicon. A back surface field is formed in each back surface field zone; the back surface fields comprise tunneling oxide layers and polycrystalline silicon layers in stacked distribution, the polycrystalline silicon layers being made of phosphorus-doped polycrystalline silicon, and the tunneling oxide layers being located between a polycrystalline silicon layer and a polycrystalline silicon layer. Positive electrodes are electrically connected to the emitters, and negative electrodes are electrically connected to the back surface fields. In the described solar cell, the light-receiving area of the front surface can be expanded and the recombination rate of electron-hole pairs can be reduced, thereby effectively improving the photoelectric conversion efficiency of the solar cell.

The invention discloses a compact range dead zone amplitude and phase testing method based on a reference target method, and belongs to the technical field of microwave measurement. According to the method, a mathematical relationship between a target scattering field and a target surface induction current is established, a conductor rod is used as a reference target, and one-dimensional transverse distribution of any target is represented by rotating the conductor rod around the center of the reference target. According to the compact range quiet zone amplitude and phase testing method based on the reference target method, radar cross sections RCS of a reference target under different azimuth angles are measured, compact range quiet zone amplitude and phase distribution is obtained through data processing inversion, and dependence on a complex and time-consuming probe scanning device is not needed. Wherein the reference target is a metal rod or a cylinder of which the length is greater than the range of the quiet zone, and the surface field distribution of the reference target and the RCS essentially form a Fourier transform relationship. The method effectively simplifies the test process of the quiet zone, improves the test efficiency, and is suitable for rapid and accurate evaluation of the performance of the compact range quiet zone.

This application discloses a semiconductor device and its manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes an active region and a termination region; the termination region surrounds the active region; the termination region includes a semiconductor body configured with a first conductivity type; it also includes a first region configured with a second conductivity type and located on a first surface; the first surface has a plurality of trenches arranged at intervals; the vertical projection of the plurality of trenches on the first surface lies within the vertical projection of the first region on the first surface; it also includes an isolation layer disposed within the trenches; the semiconductor body further includes a plurality of field limiting rings configured with a second conductivity type and located on the first surface; a field oxide layer located on the first surface; a field plate layer located on the side of the field oxide layer away from the first surface; a gate electrode located on the side of the field plate layer away from the field oxide layer; a source electrode; and a drain electrode. The technical solution of this application embodiment can improve the avalanche tolerance of the semiconductor device and enhance its performance.

The invention discloses a structured light ToF point cloud stream data-oriented real-time registration and noise suppression system, which belongs to the technical field of industrial visual inspection and comprises a point cloud preprocessing module, a cavity convolution down-sampling feature extraction module, an improved SSD feature enhancement network, a registration and difference detection module and a CUDA (Compute Unified Device Architecture) platform. Through the above mode, the spatial feature extraction capability can be improved by adopting a cavity convolution down-sampling strategy, the point cloud multi-scale information expression can be enhanced by adopting a pyramid feature fusion network, and millisecond-level point cloud registration and change detection can be realized by adopting a three-dimensional point cloud registration system for point cloud differential analysis accelerated by a GPU (Graphics Processing Unit). The processing speed can be improved by about 40% while the precision is ensured, and the applicability in an industrial high-reflective surface scene is remarkably enhanced.

The invention relates to the technical field of microwaves, in particular to a low-surface-field double-fed microwave pulse compressor and a design method thereof.The low-surface-field double-fed microwave pulse compressor comprises a resonant cavity and a low-surface-field double-circular polarizer, and the resonant cavity is used for working in a high-order resonant mode to store microwave energy; the two low-surface-field dual-circular polarizers are connected to the two sides of the resonant cavity in a chambering coupling mode respectively, and each low-surface-field dual-circular polarizer is provided with an input port used for inputting microwave pulses and an output port used for outputting compressed microwave pulses; the resonant cavity works in a high-order resonant mode, so that the resonant cavity can be connected with an external waveguide in a reaming coupling mode, and the geometric structure of the dual-circular polarizer is optimized to comprehensively reduce the surface electric field of key components; and a double-feed structure is adopted in a system architecture layer, and power feed-in is carried out on a single resonant cavity from two sides by using two low-surface-field dual circular polarizers.

The invention discloses a planar gate power device and a preparation method thereof, and relates to the technical field of semiconductors, and the planar gate power device comprises an active region and an edge terminal region surrounding the active region; the device also comprises a substrate. The epitaxial layer is located on the upper surface of the substrate, a terminal protection ring is arranged in the epitaxial layer, and the terminal protection ring is located in the edge terminal area and surrounds the active area; a JFET injection region is also arranged in the epitaxial layer, and the JFET injection region is located in the active region; the field oxide layer is located on the upper surface of the epitaxial layer, the field oxide layer comprises two parts, the field oxide layer located in the edge terminal region is of a whole-surface structure, the field oxide layer located in the active region is of a plurality of strip-shaped structures arranged at intervals, and the strip-shaped structures extend in the gate width direction. The performance of the semiconductor device can be improved.

This invention discloses a method and system for quantitative measurement of surface charge on dielectric materials based on the KPFM-AM mode, relating to tribocatalysis technology, triboelectric nanogenerators, and other fields. By deeply analyzing the probe vibration characteristics driven by an electric field, this invention derives the correlation between surface potential and surface charge density. Based on this, a series of finite element simulations are conducted using COMSOL software to simulate the actual KPFM measurement process: on the one hand, verifying the applicability of the theoretical formula in the scenario of an infinitely large uniformly charged surface; on the other hand, exploring the influence of finite-sized or non-uniformly charged surfaces on the surface potential measurement results. Simultaneously, simulation analysis is performed on the surface potential distribution of point charges, and a fitting formula based on the Lorentz function is proposed for accurate calculation of the surface potential distribution. Finally, based on the above theory and simulation results, a dedicated program is developed that can inversely calculate the surface charge distribution from the surface potential distribution, providing important theoretical support and practical tools for the efficient and accurate characterization of the surface electrical properties of dielectric materials.

The invention discloses a full-back-contact selective doping solar cell and a preparation method thereof, and belongs to the field of solar cells, the solar cell comprises an N-type substrate silicon wafer, the front surface of the N-type substrate silicon wafer comprises a front surface field, aluminum oxide and an antireflection film which are stacked in sequence, the back face of the N-type substrate silicon wafer comprises a tunneling oxide layer, a doped polycrystalline silicon layer, aluminum oxide and a passivation layer which are stacked in sequence, the doped polycrystalline silicon layer comprises intrinsic polycrystalline silicon, a P region, an N region, a p + electrode region and an n + electrode region, and the P region and the N region are located on the same plane. The P / N regions are located on the same plane through single-time intrinsic polycrystalline silicon deposition, then a transverse P-N junction is formed in the transverse gradient region, a built-in electric field can be formed by doping concentration changes in the gradient region, and the electric field can effectively separate electron-hole pairs generated by photoproduction or signals and drive the electron-hole pairs to the N-type contact region and the P-type contact region respectively, so that the photoelectric conversion efficiency is improved. Therefore, the carrier collection efficiency is improved.

The application relates to the technical field of sample concentration content detection, in particular to a surface field enhancement auxiliary container. The container comprises a container main body, a containing cavity is formed in the container main body, an electric connection end is arranged on the outer side of the container main body and extends into the containing cavity, a metal plating layer is arranged on the inner wall surface of the containing cavity, a spiral thread structure is formed on the metal plating layer, and the metal plating layer is electrically connected with the electric connection end. During detection, the power supply is connected, the metal plating layer surface accumulates charges due to the tip discharge effect, the charges are dynamically moved due to the skin effect, the size of the original electrostatic field is increased, a secondary field is enhanced for the sample small particles and molecules in the vicinity, the amplification of the weak signal details is increased, the metal surface thread structure is further increased in the effective action area on the basis of the original thread structure, and the signal is amplified by about 3 orders of magnitude on the basis of the traditional field enhancement effect.

Various embodiments of the present disclosure are directed towards an integrated chip including a well region in a substrate and comprising a first dopant type. A dielectric layer is over the well region. A conductive structure is over the dielectric layer. A first doped region and a second doped region are in the substrate and comprise the first dopant type. The conductive structure is spaced laterally between the first and second doped regions. A depletion enhancement region is in the substrate and is below the well region. The depletion enhancement region comprises a second dopant type different from the first dopant type and buts a bottom of the well region.

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a plurality of transition regions, a field oxide layer, and a gate structure. The substrate comprises a laminated substrate and an epitaxial layer. The transition regions are located in the epitaxial layer, and a surface of the transition regions away from the substrate is a first surface. The first surface is a side surface of the epitaxial layer away from the substrate. The field oxide layer is located on the first surface. The field oxide layer comprises a plurality of spaced field oxide portions. The plurality of transition regions in contact with the same field oxide portion are distributed at intervals. The gate structure is located on the first surface between two field oxide portions and on a surface of the partial field oxide layer away from the epitaxial layer. Part of the gate structure is in contact with the transition region. The transition region has a first doping type, the epitaxial layer has a second doping type, and the first doping type and the second doping type are opposite. The application solves the problems of short service life and low reliability of the semiconductor device caused by the overshoot phenomenon in the prior art.