203 results about "Tunnel barrier" patented technology

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

The invention relates to a semiconductor structure, a preparation method thereof and a magnetic tunnel junction sensor. The semiconductor structure comprises a substrate, and a buffer layer, a solid magnetic layer, a tunnel barrier layer, a free layer and a protective layer which are located on the substrate. The solid magnetic layer comprises an antiferromagnetic pinning layer and a reference layer which are stacked, the antiferromagnetic pinning layer is located on the top surface of the buffer layer, and the magnetization direction of the reference layer is pinned by the antiferromagnetic pinning layer; the tunnel barrier layer is located on the top surface of the reference layer; the free layer is located on the top surface of the tunnel barrier layer, the thickness of the free layer in the direction perpendicular to the substrate continuously and smoothly changes in the preset direction, the thickness value distribution of the free layer conforms to a preset gradient function, and a preset included angle is formed between the preset direction and the pinned magnetization direction of the reference layer; the protective layer is on the top surface of the free layer. Multi-range or continuous wide-range detection can be realized in a single-chip semiconductor device, and high sensitivity is realized.

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

A magnetic memory device includes a spin-orbit interaction active core having a number of layers stacked along a longitudinal axis and a magnetic junction extending around the longitudinal axis and substantially surrounding at least a portion of the spin-orbit interaction active core. The magnetic junction includes a free layer, a reference layer, and a tunnel barrier layer between the free layer and the reference layer.

A magnetic memory device may include a pinned magnetic pattern and a free magnetic pattern which are stacked on a substrate, a tunnel barrier pattern between the pinned magnetic pattern and the free magnetic pattern, a capping pattern on the free magnetic pattern, and a non-magnetic pattern between the free magnetic pattern and the capping pattern. The free magnetic pattern may be between the tunnel barrier pattern and the capping pattern. The non-magnetic pattern may include a first non-magnetic metal and boron, and the capping pattern includes a second non-magnetic metal. A boride formation energy of the second non-magnetic metal may be higher than a boride formation energy of the first non-magnetic metal.

A magnetoresistive random-access memory cell includes a first magnetic layer having a first lattice constant; a second magnetic layer having a second lattice constant; and a tunnel barrier between the first and second magnetic layers. The tunnel barrier includes at least one oxide layer with an oxide layer lattice constant. The oxide layer lattice constant has a mismatch smaller than six percent with at least one of the first and second lattice constants.

The invention discloses a quantum dot-based multi-axis electric field regulation entangled light source, which adopts a p-i-n diode structure, and sequentially comprises a GaAs layer, an n-type doped layer, an n-type doped layer, an n-type doped layer, an n-type doped layer, an n-type doped layer, an n-type doped layer, an n-type doped layer and An Al < 0.15 > Ga < 0.85 > As layer and an Al < 0.33 > Ga < 0.67 > As layer are sequentially arranged above the n-type doped layer and jointly serve as a tunnel potential barrier to isolate the quantum dots from the n-type doped layer; the GaAs quantum dot layer is used for growing GaAs quantum dots in the Al < 0.33 > Ga < 0.67 > As layer by adopting a liquid drop etching method; an Al < 0.33 > Ga < 0.67 > As layer covers the quantum dots to serve as a blocking potential barrier, and carrier leakage is inhibited; and the top is a p-type doped layer. The wavelength-adjustable quantum dot entangled light source with high entanglement fidelity is realized, and the requirement of a quantum repeater in a quantum network can be met.

Embodiments of present invention provide a magnetoresistive random-access-memory (MRAM) device. The MRAM device includes a reference layer; a tunnel barrier layer next to the reference layer; and a free layer next to the tunnel barrier layer, where the free layer includes a crystalline AIMnGe layer in a C38 structure formed on a magnetic seed layer, and the magnetic seed layer is a crystallized MnCo2Si layer or a crystallized MnCo2Ge layer having a cubic Heusler structure with a (001) texture. A method of forming the MRAM device is also provided.

A magnetoresistive memory cell includes a first electrode; a second electrode; and a layer stack located between the first electrode and the second electrode and comprising, from one end to another, a first reference layer, a first tunnel barrier layer, a free layer, a second tunnel barrier layer, and a second reference layer. A first one of the first reference layer and the second reference layer comprises a positive spin polarization material. A second one of the first reference layer and the second reference layer comprises a negative spin polarization material. A magnetization direction of the second reference layer is parallel to a magnetization direction of the first reference layer.

A method of manufacturing a magnetoresistive stack / structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Method for forming a magnetoresistive element by forming a sense layer having a free sense magnetization, a reference layer having a fixed reference magnetization, wherein the reference layer is formed by deposition in a Krypton atmosphere, a tunnel barrier layer between the reference layer and the sense layer, and a hard layer having a fixed reference magnetization layer opposite to that of the reference layer. The magnetoresistive element may be configured to measure an external magnetic field oriented substantially perpendicular to the plane of the reference layer. The reference magnetizations of the reference and hard layers may be oriented substantially perpendicularly to the plane of the reference and hard layers. The sense magnetization may have a vortex configuration in the absence of an external magnetic field.

The invention discloses a quantum dot device and a preparation method thereof.The quantum dot device comprises a substrate, a semiconductor layer, a barrier regulation and control part and a control electrode, the semiconductor layer is formed on one side of the substrate and comprises a source region, a drain region and a channel region located between the source region and the drain region, and the channel region comprises a channel body and a containing space; the channel body comprises at least one quantum dot region, and two sides of the quantum dot region are respectively provided with an accommodating space; the potential barrier regulation and control part is located in the accommodating space, and the potential barrier regulation and control part is used for regulating the tunneling potential barrier of the channel region; the control electrodes are located on the sides, away from the substrate, of the quantum dot areas and correspond to the quantum dot areas one to one. According to the quantum dot device provided by the invention, the potential barrier adjusting part is arranged in the semiconductor layer, so that the tunneling potential barrier in the channel region can be adjusted and controlled, the tunneling potential barrier can be increased or decreased, and the quantum dot device with ideal working current is obtained.

A semiconductor device includes a first substrate, a transistor, an interconnection structure, a first bonding pad, a magnetic tunnel junction (MTJ) structure, a conductive line and a second substrate. The transistor is formed on the first substrate. The interconnection structure is formed on the first substrate and electrically connected to the transistor. The first bonding pad is formed on and electrically connected to the interconnection structure. The MTJ structure is disposed on and electrically connected to the first bonding pad, wherein the MTJ structure comprises a free layer, a tunnel barrier layer, a synthetic antiferromagnet layer sequentially stacked up over the first bonding pad. The conductive line is disposed on the MTJ structure. The second substrate is disposed on the conductive line.

According to one aspect of the inventive concept, there is provided a MTJ device comprising a layer stack, comprising a SOT layer and a first free layer, a second free layer, a reference layer and a tunnel barrier layer arranged between the second free layer and the reference layer, and a spacer layer arranged as an interface layer between the first free layer and the second free layer, wherein the SOT layer is adapted to switch a magnetization direction of the first free layer by SOT, and wherein the first free layer is adapted to generate a magnetic stray field acting on the second free layer such that a magnetization direction of the second free layer is responsive to the magnetization direction of the first free layer.

A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

A semiconductor device comprising a variable resistance memory layer, wherein the memory layer includes a magnetic tunnel junction structure including a free layer having a changeable magnetization direction, a fixed layer having a fixed magnetization direction, a tunnel barrier layer disposed between the free layer and the fixed layer, and a magnetic oxide layer disposed on a sidewall of the free layer.

A magnetic memory device includes a substrate, a base insulating film on the substrate, a magnetic tunnel junction element including first and second magnetic patterns and a tunnel barrier pattern therebetween on the base insulating film, an upper electrode pattern on an upper face of the magnetic tunnel junction element, a capping structure including a first to third capping films sequentially stacked on a side face of the magnetic tunnel junction element, and a conductive line on both the upper electrode pattern and the capping structure and connected to the upper electrode pattern. An uppermost end of the second capping film is higher than an uppermost end of the first capping film, an uppermost end of the third capping film is lower than the uppermost end of the first capping film, and the second capping film includes a material different from respective materials of the first and third capping films.

Provided is a magnetic storage element comprising a first stack composed of: a storage layer formed from a ferromagnetic body; a first fixed layer formed from a ferromagnetic body; a first spacer layer that is sandwiched by the storage layer and the first fixed layer, and that causes antiferromagnetic exchange coupling between the storage layer and the first fixed layer; and a tunnel barrier layer that is provided to the opposite-side surface of the storage layer from the first spacer layer and that is formed of a non-magnetic body. The first stack is sandwiched by a first electrode and a second electrode.

The present disclosure provides a magnetoresistive random access memory (MRAM), including a magnetic tunnel junction (MTJ) and a transistor structure. The magnetic tunnel junction includes a magnetic fixed layer, a tunnel barrier layer, a magnetic free layer and at least one magnetic enhancement layer. The tunnel barrier layer is stacked with the magnetic fixed layer. The magnetic free layer is stacked with the tunnel barrier layer. The at least one magnetic enhancement layer is disposed corresponding to at least one of the magnetic free layers or the magnetic fixed layers. The transistor structure is electrically connected to the magnetic tunnel junction.

The present invention provides a tunnel magnetoresistor, a method for manufacturing the same, and a tunnel magnetic device. The tunnel magnetoresistor comprises: a pinned layer; a free layer disposed opposite the pinned layer, the free layer being a superparamagnetic layer with a thickness less than or equal to a critical thickness; a tunnel barrier layer located between the pinned layer and the free layer; and an underlying conductive structure located on the side of the free layer facing away from the tunnel barrier layer. The free layer in the tunnel magnetoresistor is a superparamagnetic layer with a thickness less than or equal to the critical thickness. During magnetization, the magnetic moments of the single-domain particles constituting the superparamagnetic layer can be oriented in the same direction to achieve magnetic saturation, resulting in a high magnetic susceptibility. Therefore, the tunnel magnetoresistor provided by the present invention has a large saturation field and high linearity.

A semiconductor device including a magnetic tunnel junction (MTJ) stack having a bottom electrode, where the bottom electrode includes a first bottom electrode pad and a bottom electrode pillar. A MTJ stack including vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, where the top electrode includes a tapered side surface having a width at an upper surface of the top electrode greater than a width at a lower surface of the top electrode, and the bottom electrode includes a first bottom electrode pad and a bottom electrode pillar. A MTJ stack, the MTJ stack having a bottom electrode, where the bottom electrode includes a bottom electrode pillar on a first bottom electrode pad on a second bottom electrode pad on a third bottom electrode pad.

One aspect of the invention relates to a method of manufacturing a magnetic device (4) comprising a dielectric layer (3) having a via, so-called "via", comprising: forming a tunnel junction (41) on the dielectric layer (3), the tunnel junction comprising a first magnetic layer intended to form said "free layer" (411); and a second magnetic layer intended to form the "reference layer" (412), an insulator layer intended to form a "tunnel barrier" (413); a free layer (411) or a reference layer (412) is located in the via and surrounded by the dielectric layer (3).

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a dielectric layer on top of a bottom contact; creating an opening in the dielectric layer, the opening has a slant top edge; filling a bottom portion of the opening to form a bottom electrode; filling a top portion of the opening with a first ferromagnetic material to form a first ferromagnetic layer; forming a stack of blanket layers, including a blanket tunnel barrier layer, a blanket second ferromagnetic layer, and a blanket top electrode layer, on top of the first ferromagnetic layer; patterning the stack of blanket layers into a top portion of a magnetic tunnel junction stack that includes a tunnel barrier layer, a second ferromagnetic layer, and a top electrode; and forming a top contact in contact with the top electrode. A structure formed thereby is also provided.

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a variable resistance memory layer, in which the memory layer includes a magnetic tunnel junction structure including a free layer having a variable magnetization direction, a fixed layer having a fixed magnetization direction, and a tunnel barrier layer disposed between the free layer and the fixed layer; and a magnetic oxide layer disposed on a sidewall of the free layer.

MRAM device structures and techniques for fabrication thereof with improved dielectric gapfill and individually configurable bottom and top encapsulation layers are provided. In one aspect, an MRAM device includes: memory cell pillars having a diamond shaped profile; and an interlayer dielectric fully filling gaps between the memory cell pillars. For instance, each of the memory cell pillars can include a reference layer, a free layer, a tunnel barrier between the reference layer and the free layer, a first encapsulation layer alongside the reference layer, and a second encapsulation layer alongside the free layer; and an interlayer dielectric fully filling gaps between the memory cell pillars. Optionally, the first encapsulation layer can include an oxide dielectric material, and the second encapsulation layer can include a nitride dielectric material. A method of fabricating the present MRAM devices is also provided.

In the magnetoresistance effect element according to one aspect, the metal oxide constituting the metal oxide layer has the ratio of oxygen higher than the total ratio of metal when the composition is expressed in the stoichiometric composition; and the resistivity of the metal oxide layer is higher than that of the tunnel barrier layer.

A magnetoresistive random-access memory cell includes a templating layer, including a binary alloy having an alternating layer lattice structure, and a half metallic Heusler multilayer structure including a plurality of layers of two different Heusler compounds, at least one of which is half metallic. The half metallic Heusler multilayer structure is located outward of the templating layer and exhibits perpendicular magnetic anisotropy (PMA). A tunnel barrier is outward of the half metallic Heusler multilayer structure, and a magnetic layer is outward of the tunnel barrier.

A Josephson junction device includes a substrate, a base electrode layer, a top electrode layer, a tunnel barrier layer between the base electrode layer and the top electrode layer, and a dopant layer.

The device includes a semiconductor-superconductor hybrid structure having a semiconductor component and a superconductor component, the superconductor component having a layer of aluminum, at least one conductive lead in tunneling communication with the semiconductor-superconductor hybrid structure, and a tunnel barrier disposed between the semiconductor-superconductor hybrid structure and the at least one conductive lead. The conductive lead is disposed on the superconductor component such that the superconductor component shields the semiconductor component from the conductive lead. The tunnel barrier is disposed between the superconductor component and the at least one conductive lead. Methods of manufacturing and operating the device are also provided.