121 results about "Tunnel barrier" patented technology

The invention relates to a semiconductor structure, a preparation method thereof and a magnetic tunnel junction sensor. The semiconductor structure comprises a substrate, and a buffer layer, a solid magnetic layer, a tunnel barrier layer, a free layer and a protective layer which are located on the substrate. The solid magnetic layer comprises an antiferromagnetic pinning layer and a reference layer which are stacked, the antiferromagnetic pinning layer is located on the top surface of the buffer layer, and the magnetization direction of the reference layer is pinned by the antiferromagnetic pinning layer; the tunnel barrier layer is located on the top surface of the reference layer; the free layer is located on the top surface of the tunnel barrier layer, the thickness of the free layer in the direction perpendicular to the substrate continuously and smoothly changes in the preset direction, the thickness value distribution of the free layer conforms to a preset gradient function, and a preset included angle is formed between the preset direction and the pinned magnetization direction of the reference layer; the protective layer is on the top surface of the free layer. Multi-range or continuous wide-range detection can be realized in a single-chip semiconductor device, and high sensitivity is realized.

A magnetic memory device includes a spin-orbit interaction active core having a number of layers stacked along a longitudinal axis and a magnetic junction extending around the longitudinal axis and substantially surrounding at least a portion of the spin-orbit interaction active core. The magnetic junction includes a free layer, a reference layer, and a tunnel barrier layer between the free layer and the reference layer.

A magnetic memory device may include a pinned magnetic pattern and a free magnetic pattern which are stacked on a substrate, a tunnel barrier pattern between the pinned magnetic pattern and the free magnetic pattern, a capping pattern on the free magnetic pattern, and a non-magnetic pattern between the free magnetic pattern and the capping pattern. The free magnetic pattern may be between the tunnel barrier pattern and the capping pattern. The non-magnetic pattern may include a first non-magnetic metal and boron, and the capping pattern includes a second non-magnetic metal. A boride formation energy of the second non-magnetic metal may be higher than a boride formation energy of the first non-magnetic metal.

Method for forming a magnetoresistive element by forming a sense layer having a free sense magnetization, a reference layer having a fixed reference magnetization, wherein the reference layer is formed by deposition in a Krypton atmosphere, a tunnel barrier layer between the reference layer and the sense layer, and a hard layer having a fixed reference magnetization layer opposite to that of the reference layer. The magnetoresistive element may be configured to measure an external magnetic field oriented substantially perpendicular to the plane of the reference layer. The reference magnetizations of the reference and hard layers may be oriented substantially perpendicularly to the plane of the reference and hard layers. The sense magnetization may have a vortex configuration in the absence of an external magnetic field.

A semiconductor device includes a first substrate, a transistor, an interconnection structure, a first bonding pad, a magnetic tunnel junction (MTJ) structure, a conductive line and a second substrate. The transistor is formed on the first substrate. The interconnection structure is formed on the first substrate and electrically connected to the transistor. The first bonding pad is formed on and electrically connected to the interconnection structure. The MTJ structure is disposed on and electrically connected to the first bonding pad, wherein the MTJ structure comprises a free layer, a tunnel barrier layer, a synthetic antiferromagnet layer sequentially stacked up over the first bonding pad. The conductive line is disposed on the MTJ structure. The second substrate is disposed on the conductive line.

According to one aspect of the inventive concept, there is provided a MTJ device comprising a layer stack, comprising a SOT layer and a first free layer, a second free layer, a reference layer and a tunnel barrier layer arranged between the second free layer and the reference layer, and a spacer layer arranged as an interface layer between the first free layer and the second free layer, wherein the SOT layer is adapted to switch a magnetization direction of the first free layer by SOT, and wherein the first free layer is adapted to generate a magnetic stray field acting on the second free layer such that a magnetization direction of the second free layer is responsive to the magnetization direction of the first free layer.

A semiconductor device comprising a variable resistance memory layer, wherein the memory layer includes a magnetic tunnel junction structure including a free layer having a changeable magnetization direction, a fixed layer having a fixed magnetization direction, a tunnel barrier layer disposed between the free layer and the fixed layer, and a magnetic oxide layer disposed on a sidewall of the free layer.

A magnetic memory device includes a substrate, a base insulating film on the substrate, a magnetic tunnel junction element including first and second magnetic patterns and a tunnel barrier pattern therebetween on the base insulating film, an upper electrode pattern on an upper face of the magnetic tunnel junction element, a capping structure including a first to third capping films sequentially stacked on a side face of the magnetic tunnel junction element, and a conductive line on both the upper electrode pattern and the capping structure and connected to the upper electrode pattern. An uppermost end of the second capping film is higher than an uppermost end of the first capping film, an uppermost end of the third capping film is lower than the uppermost end of the first capping film, and the second capping film includes a material different from respective materials of the first and third capping films.

Provided is a magnetic storage element comprising a first stack composed of: a storage layer formed from a ferromagnetic body; a first fixed layer formed from a ferromagnetic body; a first spacer layer that is sandwiched by the storage layer and the first fixed layer, and that causes antiferromagnetic exchange coupling between the storage layer and the first fixed layer; and a tunnel barrier layer that is provided to the opposite-side surface of the storage layer from the first spacer layer and that is formed of a non-magnetic body. The first stack is sandwiched by a first electrode and a second electrode.

The present disclosure provides a magnetoresistive random access memory (MRAM), including a magnetic tunnel junction (MTJ) and a transistor structure. The magnetic tunnel junction includes a magnetic fixed layer, a tunnel barrier layer, a magnetic free layer and at least one magnetic enhancement layer. The tunnel barrier layer is stacked with the magnetic fixed layer. The magnetic free layer is stacked with the tunnel barrier layer. The at least one magnetic enhancement layer is disposed corresponding to at least one of the magnetic free layers or the magnetic fixed layers. The transistor structure is electrically connected to the magnetic tunnel junction.

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a dielectric layer on top of a bottom contact; creating an opening in the dielectric layer, the opening has a slant top edge; filling a bottom portion of the opening to form a bottom electrode; filling a top portion of the opening with a first ferromagnetic material to form a first ferromagnetic layer; forming a stack of blanket layers, including a blanket tunnel barrier layer, a blanket second ferromagnetic layer, and a blanket top electrode layer, on top of the first ferromagnetic layer; patterning the stack of blanket layers into a top portion of a magnetic tunnel junction stack that includes a tunnel barrier layer, a second ferromagnetic layer, and a top electrode; and forming a top contact in contact with the top electrode. A structure formed thereby is also provided.

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a variable resistance memory layer, in which the memory layer includes a magnetic tunnel junction structure including a free layer having a variable magnetization direction, a fixed layer having a fixed magnetization direction, and a tunnel barrier layer disposed between the free layer and the fixed layer; and a magnetic oxide layer disposed on a sidewall of the free layer.

MRAM device structures and techniques for fabrication thereof with improved dielectric gapfill and individually configurable bottom and top encapsulation layers are provided. In one aspect, an MRAM device includes: memory cell pillars having a diamond shaped profile; and an interlayer dielectric fully filling gaps between the memory cell pillars. For instance, each of the memory cell pillars can include a reference layer, a free layer, a tunnel barrier between the reference layer and the free layer, a first encapsulation layer alongside the reference layer, and a second encapsulation layer alongside the free layer; and an interlayer dielectric fully filling gaps between the memory cell pillars. Optionally, the first encapsulation layer can include an oxide dielectric material, and the second encapsulation layer can include a nitride dielectric material. A method of fabricating the present MRAM devices is also provided.

A magnetoresistive random-access memory cell includes a templating layer, including a binary alloy having an alternating layer lattice structure, and a half metallic Heusler multilayer structure including a plurality of layers of two different Heusler compounds, at least one of which is half metallic. The half metallic Heusler multilayer structure is located outward of the templating layer and exhibits perpendicular magnetic anisotropy (PMA). A tunnel barrier is outward of the half metallic Heusler multilayer structure, and a magnetic layer is outward of the tunnel barrier.

The device includes a semiconductor-superconductor hybrid structure having a semiconductor component and a superconductor component, the superconductor component having a layer of aluminum, at least one conductive lead in tunneling communication with the semiconductor-superconductor hybrid structure, and a tunnel barrier disposed between the semiconductor-superconductor hybrid structure and the at least one conductive lead. The conductive lead is disposed on the superconductor component such that the superconductor component shields the semiconductor component from the conductive lead. The tunnel barrier is disposed between the superconductor component and the at least one conductive lead. Methods of manufacturing and operating the device are also provided.

A magnetic tunnel junction (MTJ) stack with a hammerhead profile, including vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, where the bottom electrode and the reference layer each include a first width, and the top electrode, the free layer and the tunneling barrier, each include a second width greater than the first width. Forming vertically aligned layers of a bottom electrode and a reference layer on the bottom electrode, of a magnetic tunnel junction (MTJ), where the bottom electrode, the reference layer and the hard mask, each include a first width, and separately forming vertically aligned layers of a tunneling barrier, a free layer and a top electrode on the free layer, where the tunneling barrier, the free layer and the top electrode each include a second width, where the second width is greater than the first width.

The invention discloses electronic equipment and a magnetic memory. The magnetic memory includes: a substrate; the plurality of magnetic tunnel junctions are arranged on one side of the substrate and are distributed at intervals; in the direction away from the substrate, each magnetic tunnel junction comprises a reference layer, a tunnel barrier layer and a free layer which are arranged in sequence; wherein in the plurality of magnetic tunnel junctions, two magnetic tunnel junctions are adjacent to one magnetic tunnel junction, and the distances between the magnetic tunnel junction and the two adjacent magnetic tunnel junctions are different.

Magnetic storage devices, methods of manufacturing the same, and storage devices including the same are provided. A magnetic storage device includes a spin-orbit torque (SOT) generation layer configured to generate a SOT, a spin current transfer layer on a lower surface of the SOT generation layer, and a tunneling magnetoresistive layer on a lower surface of the spin current transfer layer and including a free layer, a tunnel barrier layer, and a pinned layer. The spin current transfer layer is configured to transfer the spin current generated from the SOT generation layer to the free layer.

Embodiments of present invention provide a magnetic tunnel junction (MTJ) structure. The MTJ structure includes a MTJ stack, the MTJ stack including a tunnel barrier layer on a reference layer and a f

This invention discloses a magnetoresistive memory device comprising a magnetic tunnel junction, which includes a free layer, a reference layer, an insulating tunnel barrier layer located between the free layer and the reference layer, a vertically spaced magnetically anisotropic (PMA) ferromagnetic layer, and a conductive non-magnetic interlayer exchange coupling layer located between the free layer and the PMA ferromagnetic layer. This magnetoresistive memory device is a hybrid magnetoresistive memory device, programmed through a combination of spin torque transfer effect and voltage-controlled exchange coupling effect.

A magnetic sensor element is disclosed, comprising a magnetic tunnel junction (MTJ) comprising a reference layer, a tunnel barrier layer, a sense layer having a sense magnetization freely orientable in the presence of the external magnetic field. The reference layer has a reference magnetization and comprises a reference SAF structure and an in-plane sensitivity axis. A SOT electrode configured to pass a SOT current adapted to switch the first reference magnetization in two opposed directions along the sensitivity axis by a spin orbit torque interaction. Also disclosed is a sensing device comprising at least one sensing branch including at least one magnetic sensor element and a sensing operation using the sensing device for sensing an external magnetic field. The magnetic sensor element allows for sensing the external magnetic field with low 1 / f noise.

The present disclosure concerns a magnetoresistive sensor (MR) element, comprising a reference layer having a reference magnetization; a sense layer having a sense magnetization comprising a vortex configuration stable under the presence of an external magnetic field, the sense magnetization being reversibly movable in a direction out-of-plane relative to the reference magnetization when the external magnetic field varies in a direction out-of-plane; and a tunnel barrier layer between the reference layer and the sense layer. The MR element further comprises a dipolar assisting layer, configured to generate a dipolar stray field oriented substantially out-of-plane, such that the dipolar stray field is added to the out-of-plane external magnetic field, resulting in an effective magnetic field that is larger than and proportional to the external magnetic field. The present disclosure further concerns a magnetic sensor device comprising the MR element.

A semiconductor device includes a plurality of first line structures extending in a first direction, each of the plurality of first line structures including a first pinned layer exhibiting a magnetization in a fixed magnetization direction; a plurality of second line structures spaced apart from the first line structures and extending in a second direction intersecting the first direction; a plurality of first free layers each exhibiting a magnetization with a magnetization direction that is changeable, the first free layers respectively overlapping intersection regions of the first line structures and the second line structures between the first line structures and the second line structures; and a first tunnel barrier layer interposed between the first line structure and the first free layer.

A semiconductor device including a channel pattern and an electrode disposed over the channel pattern. An information storage pattern is disposed between the channel pattern and the electrode. The information storage pattern may include a charge trap layer; a blocking layer between the charge trap layer and the electrode; a first tunnel barrier layer between the charge trap layer and the channel pattern; and a first quantum wall between the charge trap layer and the first tunnel barrier layer. The first tunnel barrier layer may include a material with a higher energy barrier than the charge trap layer. The first quantum wall may include a material with a lower energy barrier than the first tunnel barrier layer.

A magnetoresistive device includes a magnetically fixed region and a magnetically free region positioned on opposite sides of a tunnel barrier region. One or more transition regions, including at least a first transition region and second transition region, is positioned between the magnetically fixed region and the tunnel barrier region. The first transition region includes a non-ferromagnetic transition metal and the second transition region includes an alloy including iron and boron.

The invention relates to the technical field of electronic devices, in particular to an anti-fatigue multi-iron device based on interlayer slippage and a simulation construction method and application thereof. The anti-fatigue multi-iron device comprises a left electrode area, a right electrode area and a center scattering area connected with electrodes at the two ends; the central scattering region comprises a ferroelectric layer and an antiferromagnetic layer, the ferroelectric layer and the antiferromagnetic layer are stacked through Van der Waals force, the ferroelectric layer is of a multi-layer structure, the ferroelectric layer of the central scattering region generates a switchable planar polarization field through interlayer slippage, the magnetic spin direction of the antiferromagnetic layer is turned over, and the magnetic spin direction of the antiferromagnetic layer is turned over. Switching between different magnetic phase states of the magnetic material is achieved, and meanwhile interface defects and wall pinning effects are not generated. The internal planar polarization field of the sliding ferroelectric material enables different anti-ferromagnetic magnetic phases of the sliding ferroelectric material to be switched back and forth, the tunneling barrier height is changed, the tunneling resistance effect is generated, the four-state or even more-state storage capacity can be achieved through coupling among multiple physical fields, and the storage density and energy efficiency are remarkably improved.

A method of forming a memory device with a laterally-recessed free layer includes forming a bottom electrode above an electrically conductive structure embedded within an interconnect dielectric material. A magnetic tunnel junction stack is formed above the bottom electrode. Forming the magnetic tunnel junction stack includes forming a magnetic reference layer above the bottom electrode, forming a tunnel barrier layer above the magnetic reference layer, and forming a magnetic free layer above the tunnel barrier layer. Opposed lateral portions of the magnetic free layer are recessed, and sidewall spacers are formed on the recessed opposed lateral portions of the magnetic free layer for confining an active region of the memory device formed by the magnetic free layer and the tunnel barrier layer.

This invention relates to the field of magnetic electronic devices, and more particularly to a magnetic tunnel junction, its fabrication method, and its applications. The magnetic tunnel junction includes: a lower electrode layer, a tunneling barrier layer, and an upper electrode layer; the tunneling barrier layer is disposed between the upper and lower electrode layers; wherein the tunneling barrier layer includes a self-supporting hafnium zirconium oxide film; the thickness of the self-supporting hafnium zirconium oxide film is 1-3 nm. The fabrication of this magnetic tunnel junction includes: firstly, growing an ultrathin LSMO / HZO bilayer structure on a substrate using PLD; utilizing LSMO as a sacrificial layer that can be selectively removed by a mixed solution of HCl and KI to release HZO in a self-supporting form; then, attaching the HZO to an FGT electrode to finally form the magnetic tunnel junction. The magnetic tunnel junction provided by this invention exhibits a tunneling magnetoresistance ratio (TMR) of approximately 140% at 2 K, indicating that the combination of this ultrathin ferroelectric barrier and the two-dimensional ferromagnetic electrode can achieve significant spin-polarized tunneling.

A magnetoresistive random-access memory cell includes a templating layer. The templating layer includes a binary alloy having an alternating layer lattice structure. The cell further includes a half metallic Heusler layer including a half metallic Heusler material having a tetragonal lattice structure. The half metallic Heusler layer is located outward of the templating layer, and has a Heusler in-plane lattice constant that is different from an in-plane lattice constant in a cubic form of the half metallic Heusler material. A tunnel barrier is located outward of the half metallic Heusler layer, and a magnetic layer is located outward of the tunnel barrier.

A memory transistor has a tunneling dielectric layer and a charge trapping layer between a channel region and a gate electrode, wherein the charge trapping layer has a conduction band step below a low point of a tunneling barrier in the tunneling dielectric layer such that electrons tunnel directly into the charge trapping layer when a write voltage is applied. The conduction band step of the charge trapping layer is between -1.0 electron volts and 2.3 electron volts. The memory transistor can include a barrier layer between the tunneling dielectric layer and the charge trapping layer, the barrier layer having a conduction band step that is less than the conduction band step of the charge trapping layer.