23 results about "Tunnel barrier" patented technology

A semiconductor device includes a first substrate, a transistor, an interconnection structure, a first bonding pad, a magnetic tunnel junction (MTJ) structure, a conductive line and a second substrate. The transistor is formed on the first substrate. The interconnection structure is formed on the first substrate and electrically connected to the transistor. The first bonding pad is formed on and electrically connected to the interconnection structure. The MTJ structure is disposed on and electrically connected to the first bonding pad, wherein the MTJ structure comprises a free layer, a tunnel barrier layer, a synthetic antiferromagnet layer sequentially stacked up over the first bonding pad. The conductive line is disposed on the MTJ structure. The second substrate is disposed on the conductive line.

Magnetic storage devices, methods of manufacturing the same, and storage devices including the same are provided. A magnetic storage device includes a spin-orbit torque (SOT) generation layer configured to generate a SOT, a spin current transfer layer on a lower surface of the SOT generation layer, and a tunneling magnetoresistive layer on a lower surface of the spin current transfer layer and including a free layer, a tunnel barrier layer, and a pinned layer. The spin current transfer layer is configured to transfer the spin current generated from the SOT generation layer to the free layer.

This invention relates to the field of magnetic electronic devices, and more particularly to a magnetic tunnel junction, its fabrication method, and its applications. The magnetic tunnel junction includes: a lower electrode layer, a tunneling barrier layer, and an upper electrode layer; the tunneling barrier layer is disposed between the upper and lower electrode layers; wherein the tunneling barrier layer includes a self-supporting hafnium zirconium oxide film; the thickness of the self-supporting hafnium zirconium oxide film is 1-3 nm. The fabrication of this magnetic tunnel junction includes: firstly, growing an ultrathin LSMO / HZO bilayer structure on a substrate using PLD; utilizing LSMO as a sacrificial layer that can be selectively removed by a mixed solution of HCl and KI to release HZO in a self-supporting form; then, attaching the HZO to an FGT electrode to finally form the magnetic tunnel junction. The magnetic tunnel junction provided by this invention exhibits a tunneling magnetoresistance ratio (TMR) of approximately 140% at 2 K, indicating that the combination of this ultrathin ferroelectric barrier and the two-dimensional ferromagnetic electrode can achieve significant spin-polarized tunneling.

A magnetoresistive random-access memory cell includes a templating layer. The templating layer includes a binary alloy having an alternating layer lattice structure. The cell further includes a half metallic Heusler layer including a half metallic Heusler material having a tetragonal lattice structure. The half metallic Heusler layer is located outward of the templating layer, and has a Heusler in-plane lattice constant that is different from an in-plane lattice constant in a cubic form of the half metallic Heusler material. A tunnel barrier is located outward of the half metallic Heusler layer, and a magnetic layer is located outward of the tunnel barrier.

A magnetic memory device includes a pinned magnetic pattern, a tunnel barrier pattern, a free magnetic pattern, a diffusion barrier pattern, a non-magnetic pattern and a capping pattern, which are sequentially stacked on a substrate. The diffusion barrier pattern includes a first non-magnetic metal and oxygen. The non-magnetic pattern includes a second non-magnetic metal and oxygen. An oxide formation energy of the first non-magnetic metal is lower than an oxide formation energy of the second non-magnetic metal.

A chiral tunnel magnetic junction memory cell includes a chiral reference layer and a free magnetic layer formed from a magnetic alloy. The free magnetic layer has magnetization substantially perpendicular to the free magnetic layer. A tunnel barrier is located between the chiral reference layer and the free magnetic layer. An array of such cells, methods for manufacturing such cells / arrays, and a design structure encoding such cells / array are also provided.

Provided are a semiconductor device, and a method for fabricating the same. The semiconductor device in accordance with an embodiment of the present disclosure includes: a substrate; and a memory layer formed over the substrate, wherein the memory layer includes a magnetic tunnel junction (MTJ) pattern, including a plurality of magnetic layer patterns and a tunnel barrier layer pattern, and wherein sidewalls of the magnetic layer patterns and the tunnel barrier layer pattern are aligned perpendicularly to a plane of the substrate.

A semiconductor device including a magnetic tunnel junction (MTJ) stack, a dielectric encapsulation layer surrounding vertical side surfaces of the MTJ stack, a metal encapsulation layer surrounding an upper horizontal surface and a portion of a vertical side surface of the dielectric encapsulation layer, and a dielectric surrounding a remaining portion of the vertical side surface of the dielectric encapsulation layer. A method including method includes forming a magnetic tunnel junction (MTJ) stack, forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack, and forming a metal encapsulation layer surrounding an upper horizontal surface and a portion of a vertical side surface of the dielectric encapsulation layer.

To prevent a decrease in magnetic anisotropy modulation efficiency while improving crystallinity of a magnetic layer in a magnetic memory element. A magnetic memory element includes a storage layer having a variable magnetization direction and a voltage-controlled magnetic anisotropy effect, a reference layer having an invariable magnetization direction, a tunnel barrier layer disposed between the storage layer and the reference layer, and an underlayer disposed below the storage layer. The storage layer included in the magnetic memory element is configured to have a B content of 10 at % or less. The underlayer included in the magnetic memory element is configured to have an orientation different from that of the tunnel barrier layer or to be in an amorphous state.

A magnetic memory device includes a pinned layer pattern, a free layer pattern on the pinned layer pattern, a tunnel barrier layer pattern between the pinned layer pattern and the free layer pattern, and an oxide layer pattern which is spaced apart from the tunnel barrier layer pattern with the free layer pattern interposed therebetween, and includes tantalum (Ta) oxide, in which the free layer pattern includes a first sub-free layer and a second sub-free layer which are stacked in sequence, a thickness of the second sub-free layer is smaller than that of the first sub-free layer, and the second sub-free layer includes a material having a higher boron affinity than the first sub-free layer.

A method for etching an MTJ structure comprising: providing a bottom electrode layer (12) on a substrate (10); applying a seed layer (16, 16a) to the bottom electrode layer (12); structuring the seed layer (16, 16a) and bottom electrode layer (12); applying a dielectric layer over the structured seed layer and the structured bottom electrode layer and planarizing the dielectric layer (14), exposing the structured seed layer (16, 16a), wherein the planarized dielectric layer (14) laterally surrounds the structured seed layer (16, 16a) and the structured bottom electrode layer (12), the dielectric layer (14) extending continuously along a side wall of the seed layer (16, 16a), a top surface of the bottom electrode layer (12), and a side wall of the bottom electrode layer (12);subsequently applying a stack (30) of MTJ layers comprising a defined layer (18), a tunnel barrier layer (20) and a free layer (22) onto the structured seed layer (16a), wherein the structured seed layer (16a) promotes the growth of large crystal grains in the stack (30) of MTJ layers; and structuring the stack (30) of MTJ layers to form an MTJ device, wherein the seed layer (16, 16a) is structured such that it has a width smaller than the width of the MTJ device.

A neuromorphic computing array includes horizontal lines and vertical lines, with the vertical lines intersecting the horizontal lines at cell locations. Magnetic tunnel junction cells are located at the cell locations. Each cell is electrically connected to a corresponding horizontal line and a corresponding vertical line. Each cell includes a substrate (1401), a seed layer (1403) covering the substrate, and a nitride layer (1403A) covering the seed layer (optionally, the nitride layer has a thickness greater than 5 angstroms). Each cell also includes a template layer (1403B) located outside the nitride layer, the template layer comprising a binary alloy having an alternating layered lattice structure and having a thickness greater than 50 angstroms. Each cell also includes a first magnetic layer (1405) covering the template layer, a tunnel barrier (1409) located outside the first magnetic layer, and a second magnetic layer (1411) located outside the tunnel barrier. The first magnetic layer (1405) comprises a Hessler alloy and exhibits perpendicular magnetic anisotropy (PMA).

A quantum device includes an actuator including a graphene material and having a proximal end mounted to an actuator anchor; an electrode disposed on a distal end of the actuator; a quantum dot, configured to localize a single electron, the quantum dot and the electrode disposed within a common vacuum to define a tunneling gap; and a quantum dot anchor, including the graphene material, disposed in a same plane as the quantum dot relative to the electrode. The quantum device may include a modulator configured to emit electromagnetic signaling within a particular frequency range. The graphene material is tuned to increase a Casimir force between the electrode and the quantum dot anchor in response to the electromagnetic signaling. The increased Casimir force causes the actuator to deform to bring the electrode within an electron tunneling range of the quantum dot, or lowers a tunneling barrier on a static electrode.

A non-volatile magnetoresistive random-access memory device is provided. The device comprises a three-terminal spin-orbit torque magnetic tunnel junction (MTJ) with perpendicular anisotropy. The MTJ comprises a fixed ferromagnetic layer, a free ferromagnetic layer, a tunnel barrier between the fixed and free ferromagnetic layers, and a heavy metal layer under the free ferromagnetic layer. A read access transistor is connected to a first terminal of the fixed magnetic layer. A write access transistor is connected to a second terminal of the heavy metal layer. A ground voltage is connected to a third terminal of the heavy metal layer. A read bit line is connected to the read access transistor, and a read word line is connected to the gate of the read access transistor. A write bit line is connected to the write access transistor, and a write word line is connected to the gate of the write access transistor.

The application discloses a low-voltage and low-leakage organic field effect transistor array and a preparation method and application thereof, and belongs to the technical field of organic electronics. The low-voltage and low-leakage organic field effect transistor array cooperatively suppresses leakage current in two directions of vertical and horizontal directions. A high-k-low-k double-layer composite dielectric layer is constructed, wherein the high-k dielectric layer realizes low-voltage gate control, and the low-k dielectric layer serves as a tunneling barrier to suppress vertical gate leakage; meanwhile, a patterned photoetching semiconductor layer is constructed, so that a semiconductor region is located inside a channel, and a horizontal parasitic leakage path is cut off.

A method of operating a magnetic memory device includes: (i) applying a first current to a free layer of a magnetic tunnel junction structure, which includes a magnetic translation unit (MTU) extending between a first magnetic pad and a second magnetic pad, and a tunnel barrier layer and a pinned layer stacked on the MTU, so that a multi-domain is established within the MTU, (ii) applying a magnetic field to the free layer so that the magnetization direction of the MTU switches to become anti-parallel to the magnetization directions of the first magnetic pad and the second magnetic pad, (iii) applying a second current to the free layer so that a portion of the multi-domain penetrates into the first magnetic pad, and (iv) applying another magnetic field to the free layer so that the magnetization direction of the first magnetic pad switches.

This invention discloses a magnetic storage unit and a magnetic memory. The magnetic storage unit includes an upper electrode, a pinning layer, a coupling layer, a fixed magnetic layer, a tunneling barrier layer, a free magnetic layer, and a lower electrode. These components are stacked sequentially. The coupling layer enables antiferromagnetic coupling between the fixed magnetic layer and the pinning layer. The pinning layer eliminates stray fields from the fixed magnetic layer to the free magnetic layer, and a material-doped region is provided within the pinning layer. By providing the pinning layer, the stray field from the fixed magnetic layer to the free magnetic layer can be eliminated. The material-doped region within the pinning layer ensures that the stray field experienced by the free magnetic layer remains very small under temperature changes.

A magnetic tunnel junction (MTJ) stack structure includes a reference layer, a tunnel barrier, and a free layer that includes multiple separate materials including a first material that exhibits greater than 100% tunnel magnetoresistance when paired with the tunnel barrier, and an ordered alloy material coupled to the first material. At least one part of the free layer is a ferromagnetic material.

This invention provides an LED epitaxial structure and its fabrication method, comprising a substrate and an N-type semiconductor layer, a stress relief layer, a tunneling barrier layer, a quantum dot structure, and a P-type semiconductor layer sequentially stacked on the surface of the substrate; wherein, the stress relief layer is used to release stress and trap charge carriers, and includes alternating stacked quantum wells and quantum barriers; and the stress relief layer has a quantum confinement Stark effect to reduce radiative recombination of charge carriers in the stress relief layer, thereby promoting the entry of charge carriers into the quantum dot structure through the tunneling barrier layer, thereby improving the radiative recombination of charge carriers in the quantum dot structure.

A Josephson junction device includes a substrate, a base electrode layer, a top electrode layer, a tunnel barrier layer between the base electrode layer and the top electrode layer, and a dopant layer.

A magnetic tunnel junction device includes a pinned magnetic layer, a free magnetic layer, and a tunnel barrier layer between the pinned and free magnetic layers. The free magnetic layer includes a first free layer, a second free layer spaced apart from the tunnel barrier layer with the first free layer therebetween, and a spacer layer between the first free layer and the second free layer. The first free layer and the second free layer are antiferromagnetically coupled to each other by the spacer layer, and each of the first free layer and the second free layer has a magnetization direction substantially perpendicular to an interface between the free magnetic layer and the tunnel barrier layer. A thermal stability of the free magnetic layer is in a range of 0 to 15.

A method for producing a semiconductor device, the method includes forming a first ferromagnetic (FM) layer using a first process type. A tunnel barrier (TB) layer having a monocrystalline structure is formed over the first FM layer and using a second process type different from the first process type. A second FM layer is formed over the TB layer using the first process type.