988 results about "Tunnel barrier" patented technology

Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source / drain regions separated by a channel region in a substrate, a control gate, and a gate stack between the control gate and the channel region. The gate stack includes a first insulator region in contact with the channel region, a floating charge-storage region in contact with the first insulator region, and a second insulator region in contact with the floating charge-storage region and the control gate. The gate stack includes selected material, in conjunction with control gate metallurgy, for providing desired asymmetric energy barriers that are adapted to primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and to retain a programmed charge in the floating charge-storage region. Other aspects are provided herein.

A method for providing a magnetic recording transducer is described. The method includes providing a pinned layer for a magnetic element. In one aspect, a portion of a tunneling barrier layer for the magnetic element is provided. The magnetic recording transducer annealed is after the portion of the tunneling barrier layer is provided. The annealing is at a temperature higher than room temperature. A remaining portion of the tunneling barrier layer is provided after the annealing. In another aspect, the magnetic transducer is transferred to a high vacuum annealing apparatus before annealing the magnetic transducer. In this aspect, the magnetic transducer may be annealed before any portion of the tunneling barrier is provided or after at least a portion of the tunneling barrier is provided. The annealing is performed in the high vacuum annealing apparatus. A free layer for the magnetic element is also provided.

A memory using a tunnel barrier is disclosed. A memory element includes a tunneling barrier and two conductive materials. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is irreversibly formed for one time programmable memory. The tunneling barrier can be formed by mobile ions combining with complementary ions. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity, multiple states can be created in the memory cell.

An MTJ in an MRAM array or in a TMR read head is comprised of a capping layer with a lower inter-diffusion barrier layer, an intermediate oxygen gettering layer, and an upper metal layer that contacts a top conductor. The composite capping layer is especially useful with a moderate spin polarization free layer such as a NiFe layer with a Fe content of about 17.5 to 20 atomic %. The capping layer preferably has a Ru / Ta / Ru configuration in which the lower Ru layer is about 10 to 30 Angstroms thick and the Ta layer is about 30 Angstroms thick. As a result, a high dR / R of about 40% is achieved with low magnetostriction less than about 1.0 E−6 in an MTJ in an MRAM array. Best results are obtained with an AlOx tunnel barrier layer formed by an in-situ ROX process on an 8 to 10 Angstrom thick Al layer.