13239results about "Read-only memories" patented technology

A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.

The described aspects and implementations enable efficient calibration of a sensing system of a vehicle. In one implementation, disclosed is a method and a system to perform the method, the system including the sensing system configured to obtain a plurality of images associated with a corresponding time of a plurality of times. The system further includes a data processing system operatively coupled to the sensing system and configured to generate a plurality of sets of feature tensors (FTs) associated with one or more objects of the environment depicted in a respective image. The data processing system is further to obtain a combined FT and process the combined FT using a neural network to identify one or more tracks characterizing motion of a respective object.

Technology for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. The memory system determines one or more read parameters for the selected tier based on the programmed / erased states of the other tiers in the block. For example, the memory system may select read reference levels for the selected tier based on the programmed / erased states of the other tiers. In an aspect, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES).

A processing device sets a first flag that indicates whether a first critical security parameter (CSP) file exists. The first CSP file includes a first set of CSPs for a memory device. The processing device sets a second flag that indicates whether the first CSP file is valid. The processing device sets a third flag that indicates whether a second CSP file exists. The second CSP file includes a second set of CSPs for the memory device. The processing device sets a fourth flag that indicates whether the second critical security parameter file is valid. The processing device selects one of the first or second CSP file as an active CSP file based on an evaluation of the first, second, third, and fourth flags.

The invention discloses an optimization method and device for reading performance of a flash memory in a controller and a storage medium, and belongs to the technical field of flash memories.The method comprises the steps that a preset characteristic quantity, the number of erasing and writing reading times and data retention time are input into a current prediction model to obtain a reading voltage offset interval; the method for predicting the threshold voltage distribution of the flash memory according to the use condition of the flash memory is more real-time; on the basis of reading the voltage offset interval, performing read retry operation; during read retry operation, only one offset value of read voltage is adjusted to change in each page, and other voltage offset values in the same page change along with the change of the offset value of the read voltage; through the correlation of different read voltage deviation values of the same page, the number of times of re-reading is greatly reduced, the re-reading time is shortened, the reading performance is improved, the current prediction model is further updated and stored by utilizing threshold voltage distribution data determined by the read re-try operation, and the updated prediction model is used for the next read operation, so that the prediction accuracy is improved.

A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.

A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

A method includes forming a first gate structure across a first active region on a substrate within a memory region, wherein the first gate structure is of a first transistor being of a first conductivity type; forming a second gate structure across a second active region on the substrate within a peripheral region, wherein the second gate structure is of a second transistor being of a second conductivity type, the second conductivity type is opposite to the first conductivity type; forming a first gate contact over the first gate structure, the first gate contact overlapping with the first active region; forming a second gate contact over the second gate structure, the second gate contact non-overlapping with the second active region.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

A memory device and a method of operating the memory device include setting a read voltage to be applied to a selected word line among word lines connected to a memory block and setting a first pass voltage to be applied to an adjacent word line adjacent to the selected word line among the word lines. The method also includes applying the first pass voltage to the adjacent word line and applying the read voltage to the selected word line. The first pass voltage is set higher than a reference pass voltage when the read voltage is lower than a reference voltage. The first pass voltage is set lower than the reference pass voltage when the read voltage is higher than the reference voltage.

A memory device includes a memory cell array having stacked first and second memory decks; and a peripheral circuit coupled to the memory cell array and configured to: when performing a program operation on a selected memory cell layer in the first memory deck, apply a voltage to a word line layer corresponding to the selected memory cell layer and apply a first voltage to a word line layer corresponding to an unselected memory cell layer in the first memory deck; apply a second voltage to the word line layer corresponding to the plurality of memory cell layers in the second memory deck; and apply a third voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck. The first voltage exceeds the second voltage, which exceeds the third voltage.

A memory system, an operation method thereof and a readable storage medium are provided according to examples of this disclosure. The memory system including: a memory device including a plurality of memory blocks, each of which including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; a memory controller coupled to the memory device and configured to: acquire a read retry voltage with both a first-type read retry table and a second-type read retry table; control the memory device to perform a read retry operation with the read retry voltage.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

The invention provides a programmable fuse trimming circuit, a programmable fuse trimming method and a fuse array circuit, the programmable fuse trimming circuit comprises a plurality of fuse unit modules and an end bit fuse module, and each fuse unit module comprises a fuse; the fuse programming control circuit receives an external input signal through a chip pin, controls a circuit working mode according to the external input signal, and reads fuse state information from the fuse unit module in a fuse state reading mode; performing pre-trimming on a fuse wire in the fuse wire unit module in the pre-trimming mode; and in the formal trimming mode, performing trimming operation on the fuse in the corresponding fuse unit module, and burning out the fuse in the fuse module at the end position after the fuse trimming operation is finished. After the to-be-trimmed fuse is determined by programmable read fuse and pre-trimming, formal trimming is performed according to the externally input trimming code, the end-bit fuse is burnt out after the trimming is finished, and a chip circuit cannot be trimmed again, so that the phenomenon of false burning is effectively prevented, and the burning time and cost are reduced.

A method of operating a memory device includes applying a first read voltage to a first word line WLn corresponding to target memory cells, applying a first pass voltage to a second word line WLn−1 corresponding to memory cells adjacent to the target memory cells, and applying a second pass voltage to a third word line WLn+1 corresponding to memory cells adjacent to the target memory cells. The second pass voltage is higher than the first pass voltage.

The invention relates to the technical field of data storage, and provides an optimal reading voltage determination method and device, a terminal and a storage medium, and the method comprises the steps: constructing an original threshold voltage curve corresponding to a target reading voltage grade according to the error bit number of the storage medium under each threshold voltage; obtaining error bit numbers of storage units corresponding to two storage states adjacent to the target read voltage level under each threshold voltage, and constructing a first threshold voltage curve and a second threshold voltage curve; and according to the first threshold voltage curve, the second threshold voltage curve and the original threshold voltage curve, determining an optimal reading voltage under the target reading voltage grade. According to the method and the device, the storage units are divided into different storage states, when the optimal read voltage under the target read voltage level is determined, only the error bit number of the two storage states adjacent to the target read voltage level needs to be considered, and the influence of implicated overturning and noise brought by other storage units is eliminated, so that the optimal read voltage is determined more accurately.

A non-volatile 3D memory search architecture provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. The architecture uses two word lines per unit of information of the searches and two memory devices per unit of stored feature to search against. The architecture uses respective bit lines of the non-volatile 3D memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the non-volatile 3D memory array are usable to store respective data values, e.g., corresponding to elements to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The architecture has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.

A memory system includes a plurality of memory cells each storing a first bit and a second bit and a control circuit. The control circuit is reads out first data, first partial data, and second partial data, each corresponding to the first bit, from the plurality of memory cells, read out second data, third partial data, and fourth partial data, each corresponding to the second bit, from the plurality of memory cells, generate first compressed data based on an OR operation of the first partial data and the third partial data, generate second compressed data based on an OR operation of the second partial data and the fourth partial data, and transmit the first data, the second data, the first compressed data, and the second compressed data to an external memory controller.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.

To provide a memory system and a memory device with high reliability.SOLUTION: A memory system of the embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine a first voltage based on information regarding a gradient of a distribution of threshold voltages of each of the plurality of memory cells, and to perform tracking operations. The memory controller causes the memory device to perform a plurality of read operations using a plurality of read levels for the plurality of memory cells in the tracking operation. The memory controller acquires the number of ON cells in each of the plurality of read operations. The memory controller sets a first potential difference of the plurality of read levels in a voltage range lower than the first voltage and a second potential difference of the plurality of read levels in a voltage range higher than the first voltage to be different from each other.SELECTED DRAWING: Figure 12

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.

A memory device (1) comprising a semiconductor pillar (40) and at least one memory cell (50) associated with the pillar (40), wherein each of the at least one memory cells (50) comprises a charge trap (60) and a transistor (2), wherein. for each of the at least one memory cells (50): the charge trap (60) of the memory cell (50) is configured to control a threshold voltage of the transistor (2) of the memory cell (50) by a stored charge; and the transistor (2) of the memory cell (50) comprises a source pillar segment (10), a drain pillar segment (14) and a body pillar segment (12), wherein at least one p-doped pillar segment (10, 12, 14) of the transistor (2) comprises a plurality of semiconductor layers (20), wherein layers of the plurality of semiconductor layers (20) are made of AIGaN or GaN, and wherein the plurality of semiconductor layers (20) is configured such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof.

Technology for zoned read parameters. The read parameters may include read reference levels and / or offsets applied to base read reference levels. The memory system may assign memory cells located in a region (e.g., block) into zones based on a ranking of a target read level for each set of memory cells in the region. The memory system may assign word lines in a block into zones based on a ranking of a target read voltage and / or target read voltage offset for each word line. The memory system may read each particular set of memory cells (e.g., word line in the block) using a representative read voltage for the zone into which the particular word line is assigned.