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31596results about "Read-only memories" patented technology

Method of managing fails in a non-volatile memory device and relative memory device

A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

Method for fabricating programmable memory array structures incorporating series-connected transistor strings

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

Programmable sub-surface aggregating metallization structure and method of making same

A programmable sub-surface aggregating metallization sructure ("PSAM") includes an ion conductor such as a chalcogenide-glass which includes metal ions and at least two electrodes disposed at opposing surfaces of the ion conductor. Preferably, the ion conductor includes a chalcogenide material with Group IB or Group IIB metals. One of the two electrodes is preferably configured as a cathode and the other as an anode. When a voltage is applied between the anode and cathode, a metal dendrite grows from the cathode through the ion conductor towards the anode. The growth rate of the dendrite may be stopped by removing the voltage or the dendrite may be retracted back towards the cathode by reversing the voltage polarity at the anode and cathode. When a voltage is applied for a sufficient length of time, a continuous metal dendrite grows through the ion conductor and connects the electrodes, thereby shorting the device. The continuous metal dendrite then can be broken by applying another voltage. The break in the metal dendrite can be reclosed by applying yet another voltage. Changes in the length of the dendrite or the presence of a break in the dendrite affect the resistance, capacitance, and impedance of the PSAM.
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