4877results about "Read-only memories" patented technology

An example system includes a memory device and a processing device operatively coupled to the memory device. The processing device is configured to: produce a first data item by performing, using a first boost voltage level, a first read strobe with respect to a set of memory cells storing encoded data item; apply an offset to the first boost voltage level to produce a second boost voltage level; produce a second data item by performing, using the second boost voltage level, a second read strobe with respect to the set of memory cells; and produce, based on the first data item and the second data item, decoded data item corresponding to the encoded data item.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

The present application relates to the technical field of storage, and provides a method and apparatus for determining an optimal read voltage parameter of a flash memory, and a flash memory device. The method comprises: on the basis of a linear relationship model between a read retry voltage offset value and a bit flip count, acquiring a new read retry voltage offset value corresponding to a minimized predicted bit flip count of the flash memory; determining whether data can be successfully read under the new read retry voltage offset value; if yes, adding the new read retry voltage offset value to the header of a read retry offset table to form a new read retry offset table; and on the basis of the new read retry offset table, updating the linear relationship model by means of an adaptive learning model. By means of the efficient and adaptive voltage parameter determination method, the present application can improve the success rate of data recovery and reduce performance loss.

The invention discloses a management system and method of a storage array, a dynamic fusing memory and a device, and relates to the technical field of electronics, data are isolated by setting storage areas of different storage arrays, and then the data are stored in different operation modes. And the main controller controls the switching fusing module to open the storage area corresponding to the operation mode and close the other storage areas, so that authority control and physical isolation are realized according to the hierarchical architecture corresponding to the operation mode based on a multi-stage dynamic partition and hardware authority arbitration multi-dimensional verification mechanism such as the address range of the storage area. The problem of unreasonable resource allocation of a high-safety area and a low-safety area in the related technology is solved.

The invention discloses a dynamic self-adaptive NAND Flash reading method and system based on artificial intelligence, a medium and equipment, and relates to the technical field of solid-state storage, the method comprises the following steps: S1, initiating a reading request, reading page data by using default voltage, decoding the page data through an LDPC algorithm, constructing a feature vector and performing preprocessing, inputting the voltage into a pre-trained neural network model, and carrying out voltage prediction; s2, carrying out fine sampling on the predicted voltage, reconstructing accurate threshold voltage distribution, and calculating a log-likelihood ratio; s3, designing a shared bottom layer backbone network, enabling a neural network model to have independent output branches, predicting the voltage, and evaluating the long-term health state of the block; and S4, designing an online transfer learning mechanism, and enabling the neural network model to quickly adapt to a new environment by using a small amount of new data. According to the method, the delay is greatly reduced, the power consumption is remarkably saved, data loss is prevented through early warning of bad blocks, and the write amplification factor is reduced to 1.26 through dynamic read interference suppression.

The invention provides a memory, an operation method of the memory and a memory system, and relates to the technical field of semiconductor chips. The memory comprises a memory array and a peripheral circuit coupled to the memory array, the memory array comprises memory blocks, and the memory blocks are coupled to the peripheral circuit through word lines. Wherein the storage block comprises a programmed storage unit and an unprogrammed storage unit, and the programmed storage unit comprises a first storage unit and a second storage unit. The peripheral circuit is configured to: perform a program operation on a third memory cell in the memory block, and apply a first voltage to a first word line coupled to the first memory cell at a first stage of a channel preparation stage of the program operation; and applying a second voltage to a second word line coupled to the second memory cell. Wherein the first word line is located between a third word line coupled with the third storage unit and the second word line, and the first voltage is larger than the second voltage.

The embodiments of the present disclosure disclose a memory and system, a programming method, the method comprising: applying an Nth pulse to a selected memory cell with a target state of an i-th state; after applying the Nth pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, obtaining a first sub-result and an Nth second sub-result; the first sub-result indicating whether the threshold voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicating whether the threshold voltage of the selected memory cell is less than a target threshold voltage of the i-th state; determining, according to the Nth second sub-result, a memory cell that needs to be applied with an N+1th pulse among the memory cells with the target state of the i-th state; the difference between the N+1th pulse and the Nth pulse being greater than or equal to the difference between the target threshold voltage and the preset voltage; applying the N+1th pulse to the memory cell that needs to be applied with the N+1th pulse; after applying the N+1th pulse, when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, determining that the programming of the i-th state is passed.

A semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. Each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: determining whether a workload change associated with a segment of the memory device satisfies a first threshold criterion for triggering an offset bin update; responsive to determining that the workload change satisfies the first threshold criterion, performing a calibration measurement of a center of a voltage valley for each state of each cell in the segment of the memory device; repeating the calibration measurement until a result of the calibration measurement is less than or equal to a threshold value; and updating a threshold voltage offset bin associated with the segment of the memory device based on the result of the calibration measurement.

Methods, systems, and devices for enhanced error handling in memory systems are described. A memory system may enter a read error handling procedure to recover data from a memory cell. For example, the memory system may perform multiple read operations at respective first read levels to identify a voltage valley associated with the data in the memory cell. Based on identifying the voltage valley, the memory system may read the data from the memory cell according to a second read level, where the second read level may be based on one of the first read levels, a first learning rate parameter, and a first momentum parameter. The memory system may determine whether to exit the error handling procedure or continue with the error handling procedure based on whether the data was successfully decoded in response to the read operation at the second read level.

A memory circuit includes an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting with local word line structures with global word lines arranged orthogonal to the array of NOR memory strings and aligned with a set of local word line structures provided across multiple stacks of NOR memory strings. The memory circuit includes a word line select transistor associated with each local word line structure to isolate each local word line structure from the associated global word line. The word line select transistor, when activated, selectively couples a selected local word line structure to the associated global word line. Remaining local word line structures associated with the same global word line remain disconnected and therefore not selected. In this manner, parasitic capacitance on the global word line is reduced and unintended disturb to other unselected memory transistors is also reduced.

A data storage device can generate a recommended read threshold value using a model that was trained under a plurality of conditions. However, such a model may result in an undesirable bit error rate or programming latency. If that should occur, the data storage device can use a different model trained under a condition similar to a current condition of the data storage device. In addition to avoiding an undesirable bit error rate or programming latency, this can result in improved throughput, improved quality of service, and reduced power consumption.

Technology for programing NAND memory. A memory system has control circuitry that applies a low voltage (e.g., VSS) to SGS lines in one or more unselected blocks that neighbor a block that has been selected for programming. This low voltage keeps source select transistors off, which cuts off the NAND channels in the neighbor unselected block(s) from the source line. The control circuit may float the SGS lines in other unselected blocks, which allows the source line voltage to ramp up quickly to provide for a faster programming operation.

A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

A memory device includes a memory cell array configured to store data, a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array, and a scan register circuit configured to receive a pass / fail result of data from the page buffer circuit and store the pass / fail result in a plurality of scan registers. The scan register circuit obtains information about the scan register where the fail result is stored through a scan operation, and uses the information about the scan register where the fail result is stored to determine the number of fail bits and / or a position index indicating the position of the fail bits according to the operation mode.

A memory device includes a memory cell array, a page buffer circuit including first to Nth page buffers, each page buffer including a sensing node, and a control logic configured to control page buffer operations, wherein the control logic is further configured to control the page buffer operations such that, in a first page buffer operation on a first page buffer included in a first group, a precharge period and a discharge period for a first sensing node of the first page buffer are performed, in a fifth page buffer operation on a fifth page buffer included in a second group, a precharge period and a discharge period for a fifth sensing node of the fifth page buffer are performed, and in a sensing period of the fifth page buffer operation, sensing operations on the first and fifth sensing nodes are performed together.

The application discloses a memory management method and device, a storage system and a computer readable medium, and relates to the technical field of mobile terminals. The method comprises the following steps: determining a target pre-erasing mode in an automatic mode and an active mode. In the automatic mode, the memory automatically performs a pre-erasing operation on the memory. In the active mode, the memory performs a pre-erasing operation based on an instruction sent by the host. A pre-erasing operation is performed on the memory based on the target pre-erasing mode. Therefore, for the automatic pre-erasing mode and the host-triggered pre-erasing mode, one of the two modes can be freely selected to perform a pre-erasing operation in the automatic mode and the active mode, so that the pre-erasing operation is more reasonable.

A method for dynamically estimating interference compensation thresholds of a page of memory includes performing a mock read on a target row using a mock read threshold, performing a read operation on an interference source and reading an interference state of the interference source, computing a histogram and a corresponding threshold based on the mock read threshold and the interference state of the interference source, and estimating a read threshold to dynamically compensate the interference state of the target row based on the histogram.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

Methods, systems, and devices for techniques for non-volatile initialization, such as not-and (NAND) initialization, are described. One or more dies of a memory system may perform an automatically-triggered initialization procedure prior to one or more controllers of the memory system completing a wakeup procedure. For example, the memory system may transition from an idle state to an awake. Accordingly, the one or more dies may perform an initialization procedure in response to a first voltage source, a second voltage source, or both, satisfying respective thresholds, such as by reaching a ready state. After, or in conjunction with, the initialization procedure, the one or more controllers may perform the wakeup procedure in response to the transition of the memory system from the idle state to the awake state, such that the wakeup procedure is performed after a start of, or simultaneously with, the initialization procedure at the one or more dies.

An example page buffer circuit includes a plurality of page buffer circuits and a plurality of cache latches connected with the plurality of page buffer circuits through a combined sensing node. Each of the plurality of page buffer circuits includes a main latch connected with a corresponding sensing node. The main latch includes a first transistor connected with a corresponding sensing node and configured to be driven by a monitoring signal, a first latch circuit configured to latch data, and a second transistor connected with the first transistor and configured to be driven by a voltage level of a node latching data in the first latch circuit, and a parasitic capacitor corresponding to a parasitic capacitance caused by a junction of the first transistor and the second transistor is connected between the first transistor and the second transistor.

The invention provides a memory management method and a storage device. The method comprises the following steps: before executing a complete data reading operation in response to a reading instruction of a target page, acquiring slowly-changed metadata and quickly-changed metadata of the target page; obtaining a first voltage adjustment parameter according to the slow change metadata; acquiring a second voltage adjustment parameter according to the quick change metadata; according to the first voltage adjustment parameter and the second voltage adjustment parameter, adjusting the reading voltage of the target page from a preset reading voltage to a target reading voltage; according to the target reading voltage, the complete data reading operation is executed on the target page, and the complete data reading operation is executed under the condition that historical reading failure does not occur for the target page. Therefore, the data reading efficiency of the storage device can be improved.

Methods, systems, and apparatuses include receiving, by a memory subsystem, a read command from a host device to read data from a memory portion of the memory subsystem. It is determined that the memory portion includes a partial block. A memory bin is determined for the memory portion in response to determining that the memory portion includes the partial block. A position is determined for the memory portion. A voltage offset is applied to a read voltage for the memory portion using the memory bin and the position.

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

A programming method includes applying a program voltage to a first word line coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; and during a stage of applying the program voltage to the first word line, applying a turn-on voltage to a first select line and a second select line sequentially, wherein the first select line is coupled to a select transistor of the first memory cell slice, and the second select line is coupled to a select transistor of the second memory cell slice.

The embodiment of the invention provides a manufacturing method of a semiconductor device, the semiconductor device and a memory system. The method comprises the following steps: forming an initial stack structure comprising dielectric layers and sacrificial layers which are alternately stacked; a plurality of first holes, at least one second hole and a plurality of third holes penetrating through the initial stacking structure are formed, the first holes and the second holes are arranged in a collinear mode in the first direction, the third holes are arranged in a collinear mode in the first direction, the first holes are located in the array area, and the third holes are located in the connecting area; the first direction is perpendicular to the stacking direction of the initial stacking structure; the initial stacking structure is etched through a plurality of first holes, at least one second hole and a plurality of third holes, so that the first holes are communicated with one another to form a first grid line gap structure, the third holes are communicated with one another to form a second grid line gap structure, and the initial stacking structure is reserved between the first grid line gap structure and the etched at least one second hole; and forming an isolation structure using the at least one second hole.

A memory device, can include: a control circuit configured to operate the memory device in one of an active mode, a standby mode, and a sleep mode, where the memory device is configured to receive a command from a host device when in the standby mode; a voltage regulator having an output that provides a supply voltage for accessing contents of memory cells in the memory device, where the voltage regulator is off during the sleep mode and the standby mode, and the voltage regulator is on during the active mode; and a storage element configured to maintain the supply voltage to allow the voltage regulator to be turned off during the standby mode, and at least until the voltage regulator turns on in the active mode and supports the supply voltage.

The invention discloses a dynamic error correction system and method for an OTP (One Time Programmable) memory, a computer and a storage medium, and the system comprises a cross-clock synchronization module which is used for synchronizing asynchronous data of an OTP interface to a system clock domain and generating a control signal according to a data format; the double-buffer-area module is used for alternately writing data and reading a control signal by utilizing two independent buffer areas, and correcting and outputting the written data; the CRC decoder module is used for carrying out error detection on the synchronous data; the error position searching module is used for positioning an error position candidate item of each channel; the error position matching module is used for finding out a uniquely matched error position; and the read control module is used for judging whether data reading needs to be paused or not and starting error correction operation, and sending a control signal to the double-buffer module. According to the invention, a modular architecture design is taken as a core, and a complete processing flow from data receiving, error detection, error positioning to error correction output is constructed.

A method of operating a nonvolatile memory device is provided. The method includes: performing a program operation on a selected word-line of a plurality of cell strings during a program execution period of a program loop by applying a program voltage to the selected word-line; and performing a program verification operation during a program verification period of the program loop by applying a program verification voltage to the selected word-line and by applying a first verification pass voltage to a first zone of unselected word-lines among and a second verification pass voltage to a second zone of the unselected word-lines. A voltage level of the second verification pass voltage is lower than a voltage level of the first verification pass voltage.

Disclosed are storage devices and operation methods thereof. A method includes performing a normal read operation on a memory block of the memory device to read first user data, performing an error correction operation on the first user data, and performing a special read operation on the memory block to read second user data when an error of the first user data fails to be corrected. The memory block includes cell strings, and the cell strings share ground selection lines. In the normal read operation, the memory device applies a first voltage to at least one ground selection line of the ground selection lines and applies a second voltage higher than the first voltage to remaining ground selection lines. In the special read operation, the memory device applies the second voltage or a third voltage higher than the second voltage to the ground selection lines.