8361results about "Read-only memories" patented technology

A method of operating a memory device includes applying a first read voltage to a first word line WLn corresponding to target memory cells, applying a first pass voltage to a second word line WLn−1 corresponding to memory cells adjacent to the target memory cells, and applying a second pass voltage to a third word line WLn+1 corresponding to memory cells adjacent to the target memory cells. The second pass voltage is higher than the first pass voltage.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

Technology for zoned read parameters. The read parameters may include read reference levels and / or offsets applied to base read reference levels. The memory system may assign memory cells located in a region (e.g., block) into zones based on a ranking of a target read level for each set of memory cells in the region. The memory system may assign word lines in a block into zones based on a ranking of a target read voltage and / or target read voltage offset for each word line. The memory system may read each particular set of memory cells (e.g., word line in the block) using a representative read voltage for the zone into which the particular word line is assigned.

An example system includes a memory device and a processing device operatively coupled to the memory device. The processing device is configured to: produce a first data item by performing, using a first boost voltage level, a first read strobe with respect to a set of memory cells storing encoded data item; apply an offset to the first boost voltage level to produce a second boost voltage level; produce a second data item by performing, using the second boost voltage level, a second read strobe with respect to the set of memory cells; and produce, based on the first data item and the second data item, decoded data item corresponding to the encoded data item.

The invention discloses a flash memory data decoding method and device, electronic equipment and a readable storage medium, and relates to the technical field of data decoding, and the method comprises the following steps: obtaining a current data reading result of a storage unit through a current left offset reference voltage, a non-offset reference voltage and a right offset reference voltage in current reading voltages; if decoding of the current data reading result fails, the current left offset reference voltage is immediately and dynamically adjusted based on a preset offset, so that the adjusted first left offset reference voltage is smaller than the current right offset reference voltage to generate a first reading voltage; therefore, when the characteristic changes such as threshold voltage drift occur in the long-term use of the flash memory storage unit, the fixed reference voltage is not continuously used, the read voltage is flexibly adjusted, the decoding failure caused by insufficient voltage adaptation is avoided, and the decoding success probability is improved.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

The invention provides a method and system for optimizing reading reference voltage of a three-dimensional NAND flash memory, and relates to the technical field of semiconductor memorizes.The method comprises the steps that the erasing frequency and the data retention time of the three-dimensional NAND flash memory are obtained; if the data retention time is not clear, inversely deducing the time through a sampling adjustment method, inputting the inversely deduced data retention time and erasing times into an optimal read reference voltage prediction model, and outputting an average optimal offset value of each read reference voltage; if so, substituting the two parameters into an optimal read reference voltage prediction model to output an average optimal offset value of each read reference voltage; and finally, compensating the average optimal offset value of each read reference voltage by using the interlayer difference table, and outputting all optimal read reference voltages of each layer. According to the method and the device, the accuracy of reading reference voltage optimization strategy prediction can be improved, the time overhead is reduced, and the reading performance is improved.

The invention discloses an NAND flash memory reading voltage axis dynamic prediction method and device and a storage medium, and the method comprises the steps: selecting sample data covering different types of NAND flash memories, and carrying out the training, and obtaining a GRUM model; taking PE times, RET time and VTH distribution in the sample data as the input of a GRUM model, and taking the output of the GRUM model as an optimal reading voltage axis prediction value; maintaining a weight matrix of the trained GRUM model as a base weight; taking the normalized PE times and VTH distribution as input features, taking the dimensionality-reduced weight adjustment amount as output, and constructing and training a polynomial regression model; and loading the target weight to the GRUM model to predict the optimal reading voltage of the NAND flash memory to be processed. According to the method, the output dimension of a subsequent polynomial regression model is reduced, calculation and storage burdens are reduced, meanwhile, invalid weight files are removed, and the resource utilization efficiency is further improved.

A memory apparatus includes memory cells configured to store a threshold voltage and disposed in memory holes each defining a channel. The memory apparatus also includes a control means configured to apply a first erase voltage to the channel of each of the memory holes including the memory cells in a first loop of an erase operation. The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage. The control means slows erasing of ones of the memory cells in a second loop of the erase operation in response to the threshold voltage of the ones of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

A data storage device includes a bad block management system. The bad block management system detects a grown bad block of the data storage device. When a grown bad block is detected, the bad block management system initiates a manual block write process on the wordlines associated with the grown bad block. The manual block write process includes programming the wordlines of the grown bad block in a particular state and with a voltage that closes a leakage path between a bit line associated with the grown bad block and a ground line or a ground path associated with the grown bad block.

The present application relates to the technical field of storage, and provides a method and apparatus for determining an optimal read voltage parameter of a flash memory, and a flash memory device. The method comprises: on the basis of a linear relationship model between a read retry voltage offset value and a bit flip count, acquiring a new read retry voltage offset value corresponding to a minimized predicted bit flip count of the flash memory; determining whether data can be successfully read under the new read retry voltage offset value; if yes, adding the new read retry voltage offset value to the header of a read retry offset table to form a new read retry offset table; and on the basis of the new read retry offset table, updating the linear relationship model by means of an adaptive learning model. By means of the efficient and adaptive voltage parameter determination method, the present application can improve the success rate of data recovery and reduce performance loss.

A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements.

Embodiments of the present application provide a memory device, a memory system, a memory controller, and an operation method. The memory device comprises: storage units each having multiple storage bits, wherein a preset number of storage units form a codeword, and the multiple storage bits respectively correspond to multiple pages, at least some pages correspond to multiple levels, the multiple levels include a first level and a second level, and a read voltage of the second level is less than that of the first level; and a peripheral circuit of the memory device, configured to: acquire a predicted valley voltage of the first level on the basis of a corresponding first result under a target read voltage of the first level, wherein the first result comprises the number of flipped bits of at least one codeword in two read results; acquire a predicted valley voltage of the second level on the basis of the predicted valley voltage of the first level; and use the predicted valley voltage of the first level and the predicted valley voltage of the second level to perform a first read operation on the at least one codeword.

A data storage device has an inference engine that can infer a read threshold based on a non-linear function of inputs that reflect current memory and data conditions. The read threshold can be used in reading a wordline in the memory. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and also improve latency, throughput, power consumption, and quality of service.

The invention discloses a management system and method of a storage array, a dynamic fusing memory and a device, and relates to the technical field of electronics, data are isolated by setting storage areas of different storage arrays, and then the data are stored in different operation modes. And the main controller controls the switching fusing module to open the storage area corresponding to the operation mode and close the other storage areas, so that authority control and physical isolation are realized according to the hierarchical architecture corresponding to the operation mode based on a multi-stage dynamic partition and hardware authority arbitration multi-dimensional verification mechanism such as the address range of the storage area. The problem of unreasonable resource allocation of a high-safety area and a low-safety area in the related technology is solved.

The invention discloses a dynamic self-adaptive NAND Flash reading method and system based on artificial intelligence, a medium and equipment, and relates to the technical field of solid-state storage, the method comprises the following steps: S1, initiating a reading request, reading page data by using default voltage, decoding the page data through an LDPC algorithm, constructing a feature vector and performing preprocessing, inputting the voltage into a pre-trained neural network model, and carrying out voltage prediction; s2, carrying out fine sampling on the predicted voltage, reconstructing accurate threshold voltage distribution, and calculating a log-likelihood ratio; s3, designing a shared bottom layer backbone network, enabling a neural network model to have independent output branches, predicting the voltage, and evaluating the long-term health state of the block; and S4, designing an online transfer learning mechanism, and enabling the neural network model to quickly adapt to a new environment by using a small amount of new data. According to the method, the delay is greatly reduced, the power consumption is remarkably saved, data loss is prevented through early warning of bad blocks, and the write amplification factor is reduced to 1.26 through dynamic read interference suppression.

The invention provides a memory, an operation method of the memory and a memory system, and relates to the technical field of semiconductor chips. The memory comprises a memory array and a peripheral circuit coupled to the memory array, the memory array comprises memory blocks, and the memory blocks are coupled to the peripheral circuit through word lines. Wherein the storage block comprises a programmed storage unit and an unprogrammed storage unit, and the programmed storage unit comprises a first storage unit and a second storage unit. The peripheral circuit is configured to: perform a program operation on a third memory cell in the memory block, and apply a first voltage to a first word line coupled to the first memory cell at a first stage of a channel preparation stage of the program operation; and applying a second voltage to a second word line coupled to the second memory cell. Wherein the first word line is located between a third word line coupled with the third storage unit and the second word line, and the first voltage is larger than the second voltage.

Examples of the present application disclose a memory device. The memory device includes: a memory cell array comprising memory cells that store a plurality of memory bits, the plurality of memory bits corresponding to a plurality of orders of read voltages, and a preset number of the memory cells forming a code word; and a peripheral circuit coupled with the memory cell array and configured to: acquire a first result of at least one code word corresponding to a target read voltage of a target order; acquire a predicted valley bottom voltage of the target order according to the first result of the at least one code word corresponding to the target read voltage of the target order and a level in which the target order is located; and determine a target valley bottom voltage of the target order based on the predicted valley bottom voltage of the target order.

The embodiments of the present disclosure disclose a memory and system, a programming method, the method comprising: applying an Nth pulse to a selected memory cell with a target state of an i-th state; after applying the Nth pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, obtaining a first sub-result and an Nth second sub-result; the first sub-result indicating whether the threshold voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicating whether the threshold voltage of the selected memory cell is less than a target threshold voltage of the i-th state; determining, according to the Nth second sub-result, a memory cell that needs to be applied with an N+1th pulse among the memory cells with the target state of the i-th state; the difference between the N+1th pulse and the Nth pulse being greater than or equal to the difference between the target threshold voltage and the preset voltage; applying the N+1th pulse to the memory cell that needs to be applied with the N+1th pulse; after applying the N+1th pulse, when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, determining that the programming of the i-th state is passed.

A bandgap reference circuit includes a first, a second and a third current source, a first and a second amplifier. The first, the second and the third current source each includes two cascode PMOS transistors for reducing the voltage stress applied to PMOS transistors when receives a high power supply voltage. The first amplifier controls the PMOS transistors in the first and the second current source to ensure that the PMOS transistors have enough headroom when receives a low power supply voltage. The second amplifier provides a gain-boosting loop to prevent the system mismatch of the PMOS transistors in the first, the second and the third current source. A temperature coefficient adjustment unit introduces positive temperature coefficients and negative temperature coefficients in the currents generated by the first and second current source, and a resistor generates the reference voltage according to a current duplicated by the third current source.

To provide a method for programming and verifying multiple physical cells as a single logical multi-bit cell.SOLUTION: There is provided a method of programming a logical multi-bit cell 5400 in which physical cells 5401 are programmed, verified, and read as a single logical n-bit cell that can store more levels than each of m-bit cells. First, j of i physical cells 5401-1,..., 5401-i (where j≤i) are programmed and verified using a coarse programming method until a coarse current target for the j physical cells is achieved. Next, k out of the j physical cells (where k≤j), are programmed and verified using a precision programming method until a precision current target is achieved for k physical cells.SELECTED DRAWING: Figure 55

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

A semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. Each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.

The invention relates to a semiconductor device and a method of operating the same. A memory device includes a bit line control circuit and a row decoder. The bit line control circuit applies a verify pre-charge voltage to a program prohibition bit line after a program pulse period, the program prohibition bit line holding the program prohibition voltage during the program pulse period. The row decoder forms a channel in a string coupled between a program-prohibition bit line and a source line. A program prohibition voltage of the program prohibition bit line is discharged to the verification pre-charge voltage through the channel.

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: determining whether a workload change associated with a segment of the memory device satisfies a first threshold criterion for triggering an offset bin update; responsive to determining that the workload change satisfies the first threshold criterion, performing a calibration measurement of a center of a voltage valley for each state of each cell in the segment of the memory device; repeating the calibration measurement until a result of the calibration measurement is less than or equal to a threshold value; and updating a threshold voltage offset bin associated with the segment of the memory device based on the result of the calibration measurement.

A predictive read threshold calibration method is provided in which a dedicated hardware module is used for read threshold calibration. The hardware module uses a tree-based inferencing model to generate trees that produce respective inference results based on a plurality of read thresholds. An inferred read threshold is obtained by summing the inference results of the trees, and the memory is read using the inferred read threshold. Other embodiments are provided.

A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.

The disclosed memory sub-system controller triggers read level voltage correction for reading a second portion of a memory based on errors encountered while reading data from a first portion of the memory. The controller reads a first portion of data from a first portion of a set of memory components using a set of read threshold levels and determines a read bit error rate (RBER) associated with the data read from the first portion of the set of memory components. The controller determines that the RBER associated with the data read from the first portion transgresses a threshold RBER. The controller selects an individual read level correction process from a plurality of read level correction processes and reads a second portion of data from a second portion of the set of memory components using the set of read threshold levels adjusted based on the selected individual read level correction process.

Before a read threshold is needed to read a wordline in memory, a data storage device can infer a plurality of read thresholds based on possible conditions of the memory that may exist when the read threshold is eventually needed. When the read threshold is needed, it is selected from the previously-inferred read thresholds based on the current conditions of the memory. This can improve latency and throughput, improve quality of service, reduce power consumption, and reduce errors.