5results about "Micro-instruction address formation" patented technology

A computing device including a plurality of sensors, a system-on-module, a safety microcontroller and a plurality of communication interfaces communicatively coupling the system-on-module, the safety microcontroller and the plurality of sensors together. The system-on module can include an integrated interconnection of a plurality of different types of cores and one or more different types of memory. The system-on module can be configured to control operation and or performance of a system. The safety microcontroller can be configured to provide safety supervision of the system-on-module.

Systems, methods, and apparatuses relating to auto-prediction of tail-nested regions and loop many-tripcount regions of program code. For example, one embodiment of a processor comprises: a decoder to decode sequences of instructions, including branch instructions, into sequences of microoperations (uops); an execution unit to execute the sequences of uops; a branch predictor circuit to predict whether one or more of the plurality of branch instructions will be taken; and a branch predication manager circuit to dynamically detect tail-nested regions or many-tripcount (MTC) regions of loops corresponding to one or more branch instructions of the plurality of branch instructions, the branch predication manager comprising auto-predication circuitry to selectively perform predication of the one or more branch instructions.

Systems, methods, and apparatuses relating to execution and retirement of auto-prediction code regions. For example, one embodiment of a processor comprises: decode circuitry to decode sequences of instructions, including one or more branch instructions, into sequences of microoperations (uops); execution circuitry to execute the sequences of uops; a branch predictor circuit to predict whether the one or more branch instructions will be taken; auto-predication circuitry to selectively perform predication operations within an auto-predication region of uops associated with the one or more branch instructions; and uop insertion circuitry to insert a selection uop at an end of the auto-predication region, the selection uop to select between a first value stored in a first physical register and a second value stored in a second physical register based on whether the auto-predicated region is determined to be not taken or taken, respectively.

This disclosure provides a scheduling queue caching method, a cache queue, a microinstruction allocation system, and an apparatus. The method includes: obtaining the number of valid microinstructions to be read for a target thread based on the number of valid microinstructions corresponding to that target thread in the NSQ; reading the valid microinstructions of the number to be read from the NSQ and storing them in the target cache module corresponding to the target thread; determining the number of microinstructions to be allocated from the target cache module to the scheduling queue based on the number of valid microinstructions to be read and the target cache module; and reading the valid microinstructions of the number to be allocated from the target cache module and allocating them to the corresponding scheduling queue. This method decouples the logic between the NSQ and SQ, leaving logical space for the balanced allocation of microinstructions among the SQs, effectively improving performance.

The application discloses a controller, a program execution method and an electronic device, and belongs to the technical field of integrated circuit design. A first storage area of the controller is configured to store first instruction codes of an application program, the first instruction codes include at least one target function position, a function at the target function position is a function to be updated, and a function pointer corresponding to the function to be updated is further configured at the target function position. A processor of the controller is configured to acquire second machine codes, store the second machine codes in a second storage area, and the second machine codes are results after the function to be updated at the at least one target function position is updated. The first machine codes are executed, and in the case that the first machine codes are executed to the target function position, the second machine codes in the second storage area matched with the function pointer are executed according to the function pointer at the target function position. Therefore, the flexibility of program updating can be improved.