11results about "Micro-instruction address formation" patented technology

A computing device including a plurality of sensors, a system-on-module, a safety microcontroller and a plurality of communication interfaces communicatively coupling the system-on-module, the safety microcontroller and the plurality of sensors together. The system-on module can include an integrated interconnection of a plurality of different types of cores and one or more different types of memory. The system-on module can be configured to control operation and or performance of a system. The safety microcontroller can be configured to provide safety supervision of the system-on-module.

A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.

Systems, methods, and apparatuses relating to auto-prediction of tail-nested regions and loop many-tripcount regions of program code. For example, one embodiment of a processor comprises: a decoder to decode sequences of instructions, including branch instructions, into sequences of microoperations (uops); an execution unit to execute the sequences of uops; a branch predictor circuit to predict whether one or more of the plurality of branch instructions will be taken; and a branch predication manager circuit to dynamically detect tail-nested regions or many-tripcount (MTC) regions of loops corresponding to one or more branch instructions of the plurality of branch instructions, the branch predication manager comprising auto-predication circuitry to selectively perform predication of the one or more branch instructions.

The embodiment of the invention provides a municipal fire hydrant reuse type high-frequency pressure monitoring method and system, and relates to the technical field of technologies. The method comprises the following steps: acquiring a pressure sensing signal; in response to the pressure sensing signal, executing event pre-identification in a preset simulation domain to generate a filtered signal; generating a hardware wake-up interrupt instruction based on a comparison result of the filtered signal and a preset voltage threshold; and in response to the hardware wake-up interruption, waking up a main processor from a sleep mode, and executing high-frequency data acquisition and event confirmation on the pressure sensing signal through the wakened main processor. According to the invention, the problem of high standby power consumption under the condition of lossless capture of the high-frequency event is solved, so that the effect of reducing the standby power consumption under the condition of lossless capture of the high-frequency event is achieved.

Systems, methods, and apparatuses relating to execution and retirement of auto-prediction code regions. For example, one embodiment of a processor comprises: decode circuitry to decode sequences of instructions, including one or more branch instructions, into sequences of microoperations (uops); execution circuitry to execute the sequences of uops; a branch predictor circuit to predict whether the one or more branch instructions will be taken; auto-predication circuitry to selectively perform predication operations within an auto-predication region of uops associated with the one or more branch instructions; and uop insertion circuitry to insert a selection uop at an end of the auto-predication region, the selection uop to select between a first value stored in a first physical register and a second value stored in a second physical register based on whether the auto-predicated region is determined to be not taken or taken, respectively.

This disclosure provides a scheduling queue caching method, a cache queue, a microinstruction allocation system, and an apparatus. The method includes: obtaining the number of valid microinstructions to be read for a target thread based on the number of valid microinstructions corresponding to that target thread in the NSQ; reading the valid microinstructions of the number to be read from the NSQ and storing them in the target cache module corresponding to the target thread; determining the number of microinstructions to be allocated from the target cache module to the scheduling queue based on the number of valid microinstructions to be read and the target cache module; and reading the valid microinstructions of the number to be allocated from the target cache module and allocating them to the corresponding scheduling queue. This method decouples the logic between the NSQ and SQ, leaving logical space for the balanced allocation of microinstructions among the SQs, effectively improving performance.

The application discloses a controller, a program execution method and an electronic device, and belongs to the technical field of integrated circuit design. A first storage area of the controller is configured to store first instruction codes of an application program, the first instruction codes include at least one target function position, a function at the target function position is a function to be updated, and a function pointer corresponding to the function to be updated is further configured at the target function position. A processor of the controller is configured to acquire second machine codes, store the second machine codes in a second storage area, and the second machine codes are results after the function to be updated at the at least one target function position is updated. The first machine codes are executed, and in the case that the first machine codes are executed to the target function position, the second machine codes in the second storage area matched with the function pointer are executed according to the function pointer at the target function position. Therefore, the flexibility of program updating can be improved.

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.

A system can identify respective first accessibility weights associated with at least some application programming interfaces (APIs) of respective APIs exposed by respective microservices of a group of microservices of a microservice architecture. The system can determine a second accessibility weight for an API of the respective APIs based on how often the API is invoked with at least a subset of the respective APIs, and based on second respective accessibility weights of the respective first accessibility weights that are associated with at least the subset of the respective APIs. The system can determine respective total accessibility weights for the respective microservices based on the first accessibility weights and the second accessibility weight. The system can, based on the respective total accessibility weights, determine a selected microservice of the group of microservices on which to perform chaos testing. The system can perform the chaos testing on the selected microservice.

Embodiments of the present application provide a method for processing data and related devices. The method includes: obtaining an array index of an array access operation, where the array access operation is configured to access an element within an array; determining whether the array index exceeds a length of the array according to К length field(s) carried by an object of the array, where each length field among the К length field(s) corresponds to a length threshold, the each length field among the К length field(s) carries a piece of length information for indicating the length of the array, К is a positive integer greater than or equal to 1. According to the embodiments of the present application, an array length of arrays with any length may be indicated.