21results about "Micro-instruction address formation" patented technology

The present application provides an atomicity retaining method and a processor, and an electronic device. The method includes: generating N load / store operations from a vector load / store instruction, where N is a positive integer greater than or equal to 1; detecting whether there is an event during processing of the N load / store operations that renders the vector load / store instruction non-atomic; processing the N load / store operations; in a case that there is the event that renders the vector load / store instruction non-atomic, having none of the processing of the N load / store operations produce any processing effect, or having the N load / store operations all produce processing effects. The present application can realize retaining the atomicity of vector instructions.

The embodiment of the invention discloses a data generation method and device, a model updating method and device and electronic equipment, and the method comprises the steps: enabling a large language model to generate candidate instruction data based on seed instruction data under the condition that the seed instruction data is obtained through collection in advance, carrying out the scoring of the candidate instruction data through the large language model, and then carrying out the calculation of the candidate instruction data. And taking the candidate instruction data of which the score is greater than a preset score threshold as target instruction data. In this way, under the condition that the seed instruction data is obtained through collection, the instruction data can be automatically generated according to the collected seed instruction data by means of the large language model, so that the candidate instruction data is obtained; according to the instruction data generation method and device, the candidate instruction data can be selected from the candidate instruction data by means of the large language model to obtain the candidate instruction data with the high score, the candidate instruction data serve as the target instruction data, automatic instruction data generation is achieved, instruction data generation can be more efficient, and the cost is relatively lower.

A computing device including a plurality of sensors, a system-on-module, a safety microcontroller and a plurality of communication interfaces communicatively coupling the system-on-module, the safety microcontroller and the plurality of sensors together. The system-on module can include an integrated interconnection of a plurality of different types of cores and one or more different types of memory. The system-on module can be configured to control operation and or performance of a system. The safety microcontroller can be configured to provide safety supervision of the system-on-module.

A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.

Systems, methods, and apparatuses relating to auto-prediction of tail-nested regions and loop many-tripcount regions of program code. For example, one embodiment of a processor comprises: a decoder to decode sequences of instructions, including branch instructions, into sequences of microoperations (uops); an execution unit to execute the sequences of uops; a branch predictor circuit to predict whether one or more of the plurality of branch instructions will be taken; and a branch predication manager circuit to dynamically detect tail-nested regions or many-tripcount (MTC) regions of loops corresponding to one or more branch instructions of the plurality of branch instructions, the branch predication manager comprising auto-predication circuitry to selectively perform predication of the one or more branch instructions.

The embodiment of the invention relates to a scheduling queue, a processor, an electronic device and an instruction scheduling method. The scheduling queue comprises a first sub-queue, a second sub-queue and a queue control module. The first subqueue comprises N first data items for storing instruction data, and the second subqueue comprises N second data items for storing item indexes corresponding to the first data items. The queue control module is configured to determine an idle first data item in the first sub-queue to store instruction data input into the first sub-queue, and map and store an item index of a non-empty first data item in the first sub-queue into a second data item of the second sub-queue to obtain a corresponding non-empty second data item, and maintaining a corresponding relationship between the non-empty first data item in the first sub-queue and the non-empty second data item in the second queue. The scheduling queue can greatly reduce dynamic power consumption caused by data movement.

The embodiment of the invention provides a municipal fire hydrant reuse type high-frequency pressure monitoring method and system, and relates to the technical field of technologies. The method comprises the following steps: acquiring a pressure sensing signal; in response to the pressure sensing signal, executing event pre-identification in a preset simulation domain to generate a filtered signal; generating a hardware wake-up interrupt instruction based on a comparison result of the filtered signal and a preset voltage threshold; and in response to the hardware wake-up interruption, waking up a main processor from a sleep mode, and executing high-frequency data acquisition and event confirmation on the pressure sensing signal through the wakened main processor. According to the invention, the problem of high standby power consumption under the condition of lossless capture of the high-frequency event is solved, so that the effect of reducing the standby power consumption under the condition of lossless capture of the high-frequency event is achieved.

Computer-implemented method comprising: Receiving (210) a sequence of previous program counter addresses (110) of a computer program and corresponding delta values, each delta value defining a difference between a respective first memory address (122) and a respective second memory address (124), the first memory address being a memory address from which data was retrieved when an instruction pointed to by the corresponding program counter address (110) was executed, and the second memory address (124) being a memory address from which data was retrieved before data was retrieved from the first memory address (122); generating (220) an input representation based on the sequence of program counter addresses (110) and their corresponding delta values; Providing (230) the input representation as input to a recurrent neural network (300); Receiving (240) from the recurrent neural network (300) an output defining a probability distribution of future delta values, each probability in the distribution representing a probability that execution of a future instruction of the computer program will cause data to be retrieved from a future memory address equal to (i) a respective first memory address (122) from which data was retrieved when an instruction pointed to by a last program counter address (110) in the sequence executed, and (ii) the future delta value corresponding to the probability; Determining that one or more probabilities in the distribution satisfy a threshold criterion; and automatically inserting one or more retrieval instructions into the computer program, wherein execution of the one or more fetch instructions causes data to be fetched from the one or more future memory addresses associated with the one or more probabilities satisfying the criterion, and wherein the one or more fetch instructions are inserted into the computer program before future instructions of the computer program.

Systems, methods, and apparatuses relating to execution and retirement of auto-prediction code regions. For example, one embodiment of a processor comprises: decode circuitry to decode sequences of instructions, including one or more branch instructions, into sequences of microoperations (uops); execution circuitry to execute the sequences of uops; a branch predictor circuit to predict whether the one or more branch instructions will be taken; auto-predication circuitry to selectively perform predication operations within an auto-predication region of uops associated with the one or more branch instructions; and uop insertion circuitry to insert a selection uop at an end of the auto-predication region, the selection uop to select between a first value stored in a first physical register and a second value stored in a second physical register based on whether the auto-predicated region is determined to be not taken or taken, respectively.

Embodiments of the present disclosure relate to a cache and an operating method thereof, a microinstruction cache, a processor core, an instruction processing method, an electronic device, and a computer-readable storage medium. The cache includes a plurality of cache entries, each of which is configured to store information related to a microinstruction group, and each cache entry includes an address field corresponding to the corresponding microinstruction group; in response to a target microinstruction group being filled in the microinstruction cache, address information of the microinstruction address of the target microinstruction group in the microinstruction cache is stored in the address field of the cache entry corresponding to the target microinstruction group. By setting an address field in the cache entry included in the cache and storing the address information of the microinstruction group, the address information of the microinstruction group can be used to perform operations such as parallel reading of subsequent microinstruction groups.

A branch predictor predicts a first outcome for a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. In response to taking the first predicted outcome, information representing a remainder of the first block is stored. In response to not taking the first branch instruction, the branch predictor is restarted based on the remainder block. In some cases, an address of the first block is used as an index into a branch prediction structure to access an entry corresponding to a second block along a speculative path from the first block. A corresponding set of instances of branch condition logic are used to simultaneously predict outcomes for branch instructions in the second block, and in response to a misprediction, the predicted outcomes are used in combination with the remainder block to restart the branch predictor.

The embodiment of the invention discloses an interrupt processing method and device, electronic equipment and a storage medium. According to the technical scheme provided by the embodiment of the invention, under the condition that the interrupt signal of the current task is detected, the interrupt vector table is obtained by accessing the rapid memory based on the independent bus, the function address is obtained based on the interrupt type of the interrupt signal, and the corresponding interrupt processing function is obtained based on the function address to serve as the target function; executing the register saving instruction, and saving the register content of the current task into an interrupt stack based on the register saving instruction; the target function is executed, after the target function is executed, the register loading instruction is executed, and the register content stored in the interrupt stack is recovered based on the register loading instruction. By the adoption of the technical means, the task recovery speed after interrupt processing can be increased, and the interrupt processing efficiency is improved.

The present disclosure includes apparatuses and methods related to microcode instructions indicating instruction types. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

The application discloses a program running method and device on a micro control chip and a storage medium. The application divides a non-volatile memory into multiple storage areas, downloads at least one application program into at least one storage area in the non-volatile memory, obtains an offset address corresponding to the storage area of the downloaded application program, obtains a bus access signal, verifies the bus access signal according to the offset address, if the verification is passed, performs address conversion according to the offset address to obtain a program access address, and runs the application program according to the program access address. The application embodiment can divide the non-volatile memory on the micro control chip into multiple storage areas, download multiple programs into the storage areas, and after power-on, select the program to be executed according to the options of the non-volatile memory to debug and run, thereby saving repeated download debugging in the program development process and improving the efficiency of program development and running on the micro control chip.

This disclosure provides a scheduling queue caching method, a cache queue, a microinstruction allocation system, and an apparatus. The method includes: obtaining the number of valid microinstructions to be read for a target thread based on the number of valid microinstructions corresponding to that target thread in the NSQ; reading the valid microinstructions of the number to be read from the NSQ and storing them in the target cache module corresponding to the target thread; determining the number of microinstructions to be allocated from the target cache module to the scheduling queue based on the number of valid microinstructions to be read and the target cache module; and reading the valid microinstructions of the number to be allocated from the target cache module and allocating them to the corresponding scheduling queue. This method decouples the logic between the NSQ and SQ, leaving logical space for the balanced allocation of microinstructions among the SQs, effectively improving performance.

According to an embodiment of the present invention, a BMS ring daisy chain communication automatic addressing method and a disconnection addressing method are disclosed. According to the disconnection addressing method proposed by the present invention, the MCU only needs to send one automatic addressing command to automatically reallocate device addresses for all battery management modules at unknown disconnection locations and automatically mark the battery management modules at the disconnection locations with disconnection marks. There is no need to send commands to each battery management module one by one to write address information, and there is no need to read back one by one to confirm whether the disconnection is occurring or to confirm the location of the disconnection, thereby reducing the MCU time and software resource usage.

The application discloses a controller, a program execution method and an electronic device, and belongs to the technical field of integrated circuit design. A first storage area of the controller is configured to store first instruction codes of an application program, the first instruction codes include at least one target function position, a function at the target function position is a function to be updated, and a function pointer corresponding to the function to be updated is further configured at the target function position. A processor of the controller is configured to acquire second machine codes, store the second machine codes in a second storage area, and the second machine codes are results after the function to be updated at the at least one target function position is updated. The first machine codes are executed, and in the case that the first machine codes are executed to the target function position, the second machine codes in the second storage area matched with the function pointer are executed according to the function pointer at the target function position. Therefore, the flexibility of program updating can be improved.

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.

A system can identify respective first accessibility weights associated with at least some application programming interfaces (APIs) of respective APIs exposed by respective microservices of a group of microservices of a microservice architecture. The system can determine a second accessibility weight for an API of the respective APIs based on how often the API is invoked with at least a subset of the respective APIs, and based on second respective accessibility weights of the respective first accessibility weights that are associated with at least the subset of the respective APIs. The system can determine respective total accessibility weights for the respective microservices based on the first accessibility weights and the second accessibility weight. The system can, based on the respective total accessibility weights, determine a selected microservice of the group of microservices on which to perform chaos testing. The system can perform the chaos testing on the selected microservice.

Embodiments of the present application provide a method for processing data and related devices. The method includes: obtaining an array index of an array access operation, where the array access operation is configured to access an element within an array; determining whether the array index exceeds a length of the array according to К length field(s) carried by an object of the array, where each length field among the К length field(s) corresponds to a length threshold, the each length field among the К length field(s) carries a piece of length information for indicating the length of the array, К is a positive integer greater than or equal to 1. According to the embodiments of the present application, an array length of arrays with any length may be indicated.