1312 results about "Address mapping" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

The invention discloses an extension equipment function configuration method and device, computer equipment and a storage medium, and relates to the technical field of data processing. According to the method, a hardware and firmware collaborative dynamic configuration framework is constructed, and a receiving queue is adopted at an extension equipment end to trigger a central processing unit firmware processing mechanism; in combination with virtualization design of a shadow configuration space and a shadow register, dynamic reconstruction of configuration parameters and an address mapping strategy during operation is realized; a host end supports configuration space access, base address register remapping and memory data transmission interaction through a transaction generation and routing mechanism driven by an event type. Hardware solidification limitation of traditional extension equipment is broken through through software and hardware decoupling design, the problems that function extension capacity is insufficient, resource dynamic allocation is difficult and protocol updating and virtualization scenes cannot be adapted are solved, and the technical effects of improving configuration reconstruction efficiency and address space utilization rate and supporting virtual function creation are achieved. And the adaptability of the equipment in cloud computing and edge computing environments is enhanced.

The invention provides a many-core cache consistency system, a many-core cache consistency method, electronic equipment, a storage medium and a product, and the system is based on a network-on-chip architecture, and a plurality of nodes, corresponding routers and distributed directories deployed in the routers are introduced. Each node comprises one or more processor cores and a distributed last-stage cache, and a memory address is divided into a plurality of address blocks and is associated with the distributed last-stage cache through a dynamic address mapping rule. The distributed directories and the distributed last-stage caches are in one-to-one correspondence and used for recording the states of cache lines, the router is responsible for receiving and responding to requests from local or remote nodes, querying the distributed directories and updating the states of the cache lines, and efficient management of cache consistency is achieved. The technical scheme belongs to the technical field of communication, effectively solves the problems of high load and communication delay of a main node in a traditional cache consistency protocol, and improves data consistency and access efficiency in a multiprocessor system and a large-scale parallel computing environment.

The invention discloses an address mapping method in DPU local storage virtualization, which comprises the following steps: a virtual machine calls a system call interface provided by an address mapping configuration management module on a host side to perform mapping configuration of a virtual machine physical address and a host physical address, and issues the virtual machine physical address and length to a virtual address mapping module of a DPU; the virtual address mapping module manages global direct memory access address resources, firstly allocates a global direct memory access address on a host side, then maps a virtual machine physical address to the allocated global direct memory access address in a mapping page table of the DPU, and returns the virtual machine physical address to the address mapping configuration management module; and the address mapping configuration management module obtains the distributed global direct memory access address, and maps the distributed global direct memory access address to a host physical address in the IOMMU. According to the method, by optimizing address mapping, the efficient and flexible local storage virtualization service can be realized while the data reliability is ensured.

The invention relates to the technical field of network communication, and discloses a vehicle-mounted edge computing data recording system and method based on protocol adaptive analysis, and the system comprises a multi-protocol network access controller which is used for capturing an original data frame and extracting a physical feature triple; the identification analysis engine is used for executing hash operation on the triple to generate a physical feature code and retrieving a physical logic address mapping table; the direct memory access controller is used for responding to a target memory address pointer hit by retrieval and directly writing a data load into an input buffer area of the functional operation module, and by constructing a direct addressing mechanism based on Hash mapping, thorough decoupling of vehicle-mounted heterogeneous network physical topology and edge computing logic is achieved.

A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.

According to the system memory management method and system, the electronic equipment and the storage medium provided by the invention, the virtual address information in the access information is extracted, and the virtual address information comprises the target virtual address; under the condition that the target virtual address is determined to be in a first preset virtual address range according to the virtual address information, determining an initial physical address corresponding to an initial virtual address in the first preset virtual address range according to a preset address mapping table; performing physical address calculation processing according to the target virtual address, the initial virtual address and the initial physical address to obtain a target physical address corresponding to the target virtual address; and accessing a system memory based on the target physical address and performing memory management on the system memory. By quickly returning the conversion relation from the virtual address to the physical address in the specified range, the conversion efficiency from the virtual address to the physical address can be improved, a conversion page table does not need to be configured according to MMU granularity, waste of storage space can be reduced, and the address conversion efficiency can be improved.

The invention discloses a memory data migration method and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: determining the access heat of a storage device accepting the access of a computing node based on a memory access task executed by a switching controller and an address mapping table, so as to determine a source device and a candidate data unit, according to the access parameter of the candidate data unit and the state parameter of the storage device, calculating a performance score after the candidate data unit is stored in the storage device so as to determine the data unit to be migrated and the target device, so that cold and hot data identification from the perspective of a computer fast interconnection memory heterogeneous system is realized; the rationality of data migration is improved on the basis of quantitative performance scores; according to the method, the to-be-migrated data unit is controlled to be migrated from the source device to the target device, and the address mapping table is updated, so that the data migration task is prevented from influencing the host work of the computing node, and a cold and hot data migration scheme without being perceived by the host in the computer fast interconnection memory heterogeneous system is realized.

The invention provides a multi-host system and a cross-domain access method. The system comprises a structure manager and at least two host domains, the structure manager is used for discovering and managing a topological structure of the multi-host system, distributing segment serial numbers for hosts and distributing port identification numbers for host edge switches, edge ports and downstream edge switches; the structure manager obtains equipment information of the terminal equipment and sends the equipment information to the host; the host sends a request message to the terminal equipment through the host edge switch via the port-based routing switching network; the downstream edge switch establishes an association relationship between a segment serial number and a port identification number carried in the request message, and maps a physical address of a host needing cross-domain to a physical address of a host subjected to cross-domain; and the downstream edge switch receives the completion message, determines a port identification number corresponding to the segment serial number carried in the completion message based on the association relationship, carries the port identification number in the completion message as a destination end identifier, and sends the port identification number to a corresponding host.

The invention provides a communication method, device and system, electronic equipment and a storage medium, and relates to the technical field of communication. The method comprises the following steps: receiving an Ethernet data frame sent by a first host connected with a first network device, wherein the Ethernet data frame comprises a source MAC address and a destination MAC address; determining a virtual Ethernet identifier and a target site mapping prefix corresponding to the target MAC address according to a preset address mapping relationship; generating an IPv6 message header according to the virtual Ethernet identifier, the target site mapping prefix and the target MAC address, and packaging the Ethernet data frame according to the IPv6 message header to obtain an IPv6 message; and sending the IPv6 message to a second network device, decapsulating the IPv6 message by the second network device to obtain an Ethernet data frame, and sending the Ethernet data frame to a second host connected to the second network device. The present disclosure can reduce overhead and improve system security.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.

A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The method may include: utilizing a memory controller to receive a set of first commands from a host device, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block; determining a selected table update size among multiple predetermined table update sizes according to at least one predetermined rule, wherein the multiple predetermined table update sizes represent multiple table entry counts, respectively; and updating at least one logical-to-physical address mapping table in the NV memory according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, for further data accessing.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

The invention discloses a method and device for repairing codes in a memory, a storage medium, a chip and a computer program product, and the method comprises the steps: during starting, each target code block in a first memory is executed in sequence, and the target code blocks are obtained by dividing to-be-executed codes in the first memory in advance; when the target code block in the first memory is started to be executed every time, judging whether the target code block contains a code to be repaired or not; if the judgment result is yes, determining a target storage address of a mapping code block corresponding to the target code block in a second memory according to a preset address mapping relation, and skipping to the target storage address in the second memory to execute the mapping code block, and then jumping back to the first memory and continuing to execute the next target code block until it is confirmed that all the to-be-executed codes in the first memory are executed. According to the scheme, more efficient code repair can be realized in a lower storage space.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

The embodiment of the invention provides a model reasoning data caching method and device for a caching system and a storage medium, and the method comprises the steps: configuring a first virtual address mapped to a high-performance memory of the caching system for a data caching pool, and generating a first reasoning data according to the data size of the first reasoning data generated by a target reasoning model; determining a target memory space of the high-performance memory mapped by the first virtual address, and enabling the data volume of the first reasoning data to be in direct proportion to the memory space volume of the target memory space mapped by the first virtual address, thereby creating a dynamic data buffer pool of the target reasoning model, and then caching the first reasoning data based on the target memory space corresponding to the dynamic data buffer pool, thereby realizing on-demand allocation of the high-performance memory in the cache system, and improving the utilization efficiency and the use flexibility of the high-performance memory in the cache system.

In some implementations, a memory device may receive, from a host device, a write command instructing the memory device to write host data to a portion of a memory associated with a logical address. The memory device may determine a physical location of the memory associated with the logical address by using a wear leveling algorithm to map the logical address to the physical location of the memory, wherein the portion of the memory is associated with a wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomized parameter. The memory device may write the host data to the physical location of the memory.

Various methods and processing systems for the effective management of network traffic and facilitating data forwarding within distributed computing environments. Network components may be configured to amalgamate the Border Gateway Protocol (BGP) with Source Network Address Translation (SNAT) or network address port translation (NAPT) technologies to facilitate dynamic notification of network address accessibility and use port index identifiers to augment the precision and resilience of routing. A distributed SNAT / NAPT virtual network function (VNF) or cloud-native network function (CNF) may collaborate with LEAF switches or server aggregation devices to refine data transmission via adaptable address mapping and forwarding and enhance network scalability and resilience.

The invention discloses a cross-domain communication method, electronic equipment and a medium, and relates to the technical field of computers, the method comprises the following steps: receiving memory access information of first equipment; identifying whether the first equipment is cross-domain equipment or not according to first identification information of the first equipment in the memory access information; when the first equipment is not cross-domain equipment, performing cross-domain address mapping on the memory access information to generate a source end request message; sending the source end request message to a second non-transparent bridge in the target domain through the transmission bridge; receiving an initial response message forwarded by the second non-transparent bridge; and generating a final response message according to the initial response message, the first identification information and second identification information corresponding to the second equipment, and returning the final response message to the first equipment. According to the application, the non-transparent bridges located in different domains are connected through the transmission bridge, and the problems of cross-domain access expansibility and wiring are solved.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

Embodiments of this application disclose a memory sharing method and an apparatus. The method in embodiments of this application includes: A host side establishes a first memory page table via a shared virtual address management unit. The first memory page table includes mapping from a virtual address on the host side to a physical address on the host side. A first device side establishes a second memory page table via a shared virtual address agent unit. The second memory page table includes mapping from a virtual address on the first device side to a physical address on the first device side. An agent system memory management unit SMMU on the first device side updates the second memory page table based on the first memory page table, or the host side updates the first memory page table based on the second memory page table.

The invention relates to the technical field of data acquisition, and discloses a PCIe-based DMA data zero copy processing method and system. The method is applied to a zero copy processing system, and comprises a HOST module for distributing a physical DMA buffer area and mapping a physical address of the DMA buffer area to a logically continuous virtual address space; the HOST module is used for constructing a preset descriptor queue and sending a head address of the queue to the FPGA module; the FPGA module receives the initial address of the queue through a PCIe interface, analyzes a descriptor, and writes DMA data with a preset transmission length into a sub DMA buffer area of the HOST module; and the HOST module monitors the state of the DMA buffer area and adopts a dynamic flow control mechanism to adjust the data transmission rate of the FPGA module according to the state. According to the method provided by the embodiment of the invention, the physical DMA buffer area is mapped to the logically continuous virtual address space, and the application program can directly access the DMA data in the user space without copying through the middle of a kernel, so that zero-copy access is realized, the data processing delay is reduced, and the data transmission efficiency is improved.

An adaptive data management method for polymorphic addressing comprises the following steps: acquiring multi-scene data from the Internet of Things, preprocessing the multi-scene data, and constructing a standardized data set; and performing multi-dimensional classification on the multi-scene data based on the similarity among the key indexes in the standardized data set to obtain a classification table. And obtaining a polymorphic addressing scheme corresponding to each type of data in the classification table, and generating a polymorphic addressing mapping table in combination with the property parameters of each type of data. And storing the polymorphic addressing mapping table in a distributed storage end, carrying out addressing position distribution on each storage node in the distributed storage end through a network topology structure, and outputting a distributed storage strategy. And constructing a virtual node associated with each storage node, and when the distributed storage strategy is executed, splitting the polymorphic addressing mapping table so as to store the polymorphic addressing data with the first scene label to the virtual node. Thread blockage during reading and writing of the multi-scene data in the Internet of Things is avoided, and the data management efficiency is improved.

The invention relates to the technical field of network operation and maintenance and communication monitoring, and discloses a machine room fault node identification method and system based on network topology, and the method comprises the steps: obtaining real-time network topology data and link transmission indexes, and constructing a weighted directed graph and an evolution sequence; performing time sequence projection on the historical data according to the sequence to obtain a node state vector; calculating a deviation value, and if the deviation value exceeds the limit, extracting deviation characteristics and searching to obtain a potential abnormal region; dominant indexes are obtained through clustering and grouping, propagation influences are evaluated, and a priority sequence is determined; an initial fault source is positioned, a congestion link is tracked, and a service influence range is mapped through a logic address; extracting link safety risk characteristics, calculating a correction coefficient, adjusting an abnormal threshold value, and evaluating a positioning difficulty level; and finally, similar cases are retrieved to generate a repair instruction, model parameters are fed back and adjusted, and optimized stable configuration is obtained. According to the method, accurate recognition and closed-loop optimization of machine room faults can be realized.

The invention discloses a PCIe ECAM address mapping optimization method and system, and belongs to the technical field of operating system optimization, and the method comprises the steps: formulating a PCIe device region division rule, and dividing a PCIe device into a high-frequency access region device and a low-frequency access region device according to the device distribution condition in a PCIe bus topology based on the rule; the page table allocation comprises static page table pre-allocation and dynamic page table allocation adjustment, based on PCIe device area division, devices in a high-frequency access area are subjected to centralized memory mapping with a large page as the granularity, and devices in a low-frequency access area are subjected to independent memory mapping with a small page as the granularity; and setting an access frequency threshold, monitoring the access frequency of the PCIe equipment configuration space when the system runs, and merging or splitting the page table through the memory management unit. The number of page table items can be remarkably reduced, the hit rate of the TLB is increased, and the overall memory access efficiency of a system is improved.

The embodiment of the invention provides an input and output memory management unit, a memory access method and related equipment, and the input and output memory management unit comprises an input and output translation bypass buffer which comprises a cache table item used for caching a mapping relation between an equipment virtual address and a system physical address carried by a memory access request; an address space identifier of the equipment sending the memory access request is cached in a label item of the cache table item; and when a memory access request is obtained, querying a cache table item of the input / output translation bypass buffer at least based on the sent address space identifier, so as to obtain a system physical address mapped by the cached equipment virtual address in the address item corresponding to the tag item hit by the query. According to the technical scheme provided by the embodiment of the invention, on the basis of ensuring that the function of the input / output translation bypass buffer is realized, the reliability and the safety of determining the physical address of the system between devices can be improved.

The embodiment of the invention discloses a system startup memory detection method and device, equipment and a storage medium, and the method comprises the steps: calculating the maximum value of a Hypervisor early virtual address mapping range according to the initial address of Hypervisor operation before a final page table takes effect; when the dynamic allocation pool is utilized to allocate the memory page, determining a virtual address range of the allocated memory page by utilizing a base address of the allocated memory page, and detecting whether the virtual address range of the allocated memory page exceeds a maximum value of a Hypervisor early virtual address mapping range or not; and when the maximum value of the Hypervisor early virtual address mapping range is exceeded, outputting an error prompt, and returning a memory error. Compared with a traditional estimation mode, the probability that estimation is inaccurate due to the fact that dynamic allocation changes is reduced, the memory errors can be accurately detected in advance before the system crashes, and a developer can conveniently locate the reason of crashes.