2028 results about "Address mapping" patented technology

For optimizing access to system memory having a plurality of memory banks, interleaving can be used when storing data so that data sequences are distributed over memory banks. The invention introduces an address-mapping method applying a table lookup procedure so that arbitrary, non-power-of-two interleave factors and numbers of memory banks are possible for various strides.

An electronic memory module according to the invention provides non-volatile memory that can be used in place of a DRAM module without battery backup. An embodiment of the invention includes an embedded microprocessor with microcode that translates the FB-DIMM address and control signals from the system into appropriate address and control signals for NAND flash memory. Wear-leveling, bad block management, garbage collection are preferably implemented by microcode executed by the microprocessor. The microprocessor, additional logic, and embedded memory provides the functions of a flash memory controller. The microprocessor memory preferably contains address mapping tables, free page queue, and garbage collection information.

An information handling system is provided. The information handling system includes a first hypervisor running on a first host and a second hypervisor running on a second host. The first hypervisor managing a first virtual switch, and the second hypervisor managing a second virtual switch. The information handling system also includes a plurality of virtual machines (VMs), including a first VM, which is part of a first tenant, running on the first host, and a second VM, part of a second tenant, running on the second host. The first virtual switch has a mapping in memory that maps a customer-specific multicast IP address, used by the plurality of VMs to indicate a multicast group that includes VMs on the first and second tenants, to a global multicast IP address used by the first and second hosts.

A method for minimizing the degradation of performance upon accessing a flash memory using a logical-physical mapping scheme, and a method for efficiently storing and managing information on logical-physical mapping in a flash memory. A method for writing data in a flash memory includes determining whether a sector is empty in a physical page having a most recently written logical page number of data to be written, the offset of the sector matching that of the data to be written; if the sector is empty, writing the data in the sector to the physical page; and if the sector is not empty, selecting an empty physical page to write the data to a sector in the selected empty physical page of which the offset matches that of the data to be written and writing a logical page number for the data to the selected empty physical page.

Improved reliability high endurance non-volatile memory device with zone-based non-volatile memory file system is described. According to one aspect of the present invention, a zone-based non-volatile memory file system comprises a two-level address mapping scheme: a first level address mapping scheme maps linear or logic address received from a host computer system to a virtual zone address; and a second level address mapping scheme maps the virtual zone address to a physical zone address of a non-volatile memory module. The virtual zone address represents a number of zones each including a plurality of data sectors. Zone is configured as a unit smaller than data blocks and larger than data pages. Each of the data sector consists of 512-byte of data. The ratio between zone and the sectors is predefined by physical characteristics of the non-volatile memory module. A tracking table is used for correlating the virtual zone address with the physical zone address. Data programming and erasing are performed in a zone basis.

In a computer network of devices, at least some of the devices (i.e. the DCHP devices) have a static (e.g. MAC) address which does not change over time and a dynamic (e.g. IP) address which may change over time. There is disclosed a method and computer program for mapping the static address and dynamic address for the devices comprising polling said devices using said IP addresses and during said polling determining the MAC addresses of the devices, and providing a set of mapped static and dynamic addresses, said method including repeating the steps of the method at intervals.

Using the method of the invention, it is possible, when entering a particular conversation in a database, to access the IP addresses, to determine which is the current DHCP device that address maps to, and assign the conversation to that device and store it in the database assigned to that device. Therefore, for each DHCP device, one can store a history of the conversations or traffic involved in that device.

The invention relates to a method for allocating mass storage resources according to needs in a heterogeneous SAN (Storage Area Network) environment, belonging to the field of storage area networks, in particular to the technical field of storage virtualization therein. The invention is characterized by designing and realizing an out-of-band storage virtualization system aiming at a heterogeneousstorage application server and various storage devices in the SAN environment and providing a method for allocating the mass storage resources according to needs based on allocation while writing anddynamic address mapping mechanism on the basis of the system. The method can be used for allocating the storage resources according to the actual needs of applications, dynamically expanding the mapping relation between the logic storage space and the physical storage space, effectively increasing the utilization rate of the storage resources and the expandability of storage capacity, reducing the maintenance cost of the storage devices and realizing instant storage purchase.

The present invention relates to a method, system, client device, gateway device and computer program product for maintaining a state information in an intermediate network function, wherein the state information expires after a predetermined idle period. Detecting means are provided for detecting an idle state of a connection. In response to the detecting means, a transport protocol used for encapsulating data is changed from a first protocol with a first predetermined idle period to a second protocol with a second predetermined idle period, said second predetermined idle period being longer than said first predetermined idle period. Alternatively, a connection parameter is provided to a device for a parallel second connection in a set-up negotiation via said first connection. This connection parameter is then used for setting up a parallel second connection to the device based on the second transport protocol used for encapsulating data with the second predetermined idle period. Then, an information linking the first and second connections is transmitted from the device to the data network, wherein the second connection is used for transmitting a wake-up notification to the device in response a detected idle state. Both alternatives provide the advantage of reduced keep-alive signaling and thus enhanced battery efficiency.

Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention.

A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.

A “Variable-Rate Perfect Hasher” maps sparse variable-rate data of one or more dimensions into a hash table using a perfect hash function. In various embodiments, perfect hash tables are populated by first computing offset table address for each data point of a domain of sparse variable-rate data elements. Offset vectors are then computed for each offset table address based in part on the size of each data element by evaluating offset vectors in order of a sum of the data point addresses mapping to each offset vector. These offset vectors are then stored in the offset table. For each data point, the corresponding offset vector is then used to compute a hash table address. Data elements are then perfectly hashed into the hash table using the computed hash table addresses. The resulting hash tables support efficient random access of the variable-sized data elements stored therein.

A process is disclosed in which a security policy is associated with a virtual private network (VPN) interface at a first device, for example, a router. Input is received specifying an association of a VPN endpoint address to a corresponding routable network address of a second device. A message is issued to a security module at the first device, the message including the routable network address of the second device and the security policy. Encryption state information is generated for network traffic from the first device to the second device, based on the message. The process is applicable to a hub-and-spoke network architecture that utilizes a point-to-multipoint GRE tunnel and the IPsec protocol for security. The process is dynamic in that the encryption state is generated for traffic over a VPN link, in response to notification of a virtual address-to-real address mapping, i.e., the association. In an embodiment, the association is an NHRP mapping.

A method is for recovering a block mapping table in a system including a flash memory device, where the block mapping table utilizes address mapping in accordance with a wear-leveling scheme. The method includes reading block arrangement information from the flash memory device for the wear-leveling scheme, restoring the block mapping table with reference to allocation block information included in the block arrangement information and scanning address allocation information included in spare regions of erased blocks of the flash memory device with reference to erased block information included in the block arrangement information and updating the block mapping table in accordance with the scanned address allocation information.

Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

A processor (e.g. utilizing an operating system and/or circuitry) may access physical memory by paging, where a page is the smallest partition of memory mapped by the processor from a virtual address to a physical address. An application program executing on the processor addresses a virtual address space so that the application program may be unaware of physical memory paging mechanisms. A memory control layer manages physical memory space in units of sub-blocks, wherein a sub-blocks is smaller than a size of the page. Multiple virtual address blocks may be mapped to the same physical page in memory. A sub-block can be moved from a page (e.g. from one physical memory to a second physical memory) without moving other sub-blocks within the page in a manner that is transparent to the application program.