472 results about "Address mapping" patented technology

The invention relates to the technical field of network communication, and discloses a vehicle-mounted edge computing data recording system and method based on protocol adaptive analysis, and the system comprises a multi-protocol network access controller which is used for capturing an original data frame and extracting a physical feature triple; the identification analysis engine is used for executing hash operation on the triple to generate a physical feature code and retrieving a physical logic address mapping table; the direct memory access controller is used for responding to a target memory address pointer hit by retrieval and directly writing a data load into an input buffer area of the functional operation module, and by constructing a direct addressing mechanism based on Hash mapping, thorough decoupling of vehicle-mounted heterogeneous network physical topology and edge computing logic is achieved.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention relates to the technical field of network operation and maintenance and communication monitoring, and discloses a machine room fault node identification method and system based on network topology, and the method comprises the steps: obtaining real-time network topology data and link transmission indexes, and constructing a weighted directed graph and an evolution sequence; performing time sequence projection on the historical data according to the sequence to obtain a node state vector; calculating a deviation value, and if the deviation value exceeds the limit, extracting deviation characteristics and searching to obtain a potential abnormal region; dominant indexes are obtained through clustering and grouping, propagation influences are evaluated, and a priority sequence is determined; an initial fault source is positioned, a congestion link is tracked, and a service influence range is mapped through a logic address; extracting link safety risk characteristics, calculating a correction coefficient, adjusting an abnormal threshold value, and evaluating a positioning difficulty level; and finally, similar cases are retrieved to generate a repair instruction, model parameters are fed back and adjusted, and optimized stable configuration is obtained. According to the method, accurate recognition and closed-loop optimization of machine room faults can be realized.

The invention discloses an accelerator card resource sharing system, method and device and electronic equipment, and relates to the technical field of accelerator cards, the system comprises an address mapping module and a memory copying engine module, the address mapping module is used for receiving an access request of an accelerator card video memory of a source host, querying a mapping relation of virtual addresses in a dynamic mapping table and copying the virtual addresses to the source host; the memory copy engine module generates target label information for identifying a target data packet transmitted across hosts, the dynamic mapping table reflects a mapping relation between a source host virtual address and a target host accelerator card physical address, and the memory copy engine module copies the target data packet according to the transmission priority and sequence information of the target data packet contained in the target label information. And executing cross-host data transmission to ensure that the data is efficiently transmitted to an accelerator card video memory of a target host. According to the embodiment of the invention, the problems of relatively high delay and insufficient flexibility in coping with the complex demand of acceleration card cluster sharing in the prior art are effectively solved.

The invention provides a data writing performance improvement method for a storage device and the storage device, is applied to the storage device, and relates to the technical field of storage. The method comprises the following steps: receiving to-be-written data, and determining a logic unit address and a target address mapping table of the to-be-written data; if neither the meter reading completion chain table nor the meter reading request chain table contains the target address mapping table, adding a meter reading request node in the meter reading request chain table; after reading of the target address mapping table is completed, the target address mapping table is updated; the method comprises the following steps: establishing a meter reading completion chain table and a meter reading request chain table, adding a node for reading a target address mapping table corresponding to data to be written into the meter reading request chain table, after reading is completed, moving the node into the meter reading completion chain table, and hiding time delay in a meter reading process in a time interval when a storage device receives data from a host, and the time delay of reading and writing the address mapping table in the random writing process is reduced, so that the random writing performance is improved.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention belongs to the technical field of simulation, and particularly relates to a simulation result display method and device, a storage medium and equipment, and the display method comprises the steps: obtaining a global program counting address and instruction information according to a firmware logic file, and constructing a reference address mapping table based on the global program counting address and the instruction information; wherein the firmware logic file is a file for storing firmware execution logic related information; obtaining a firmware program counting address according to the firmware signal file; wherein the global program counting address comprises the firmware program counting address, and the firmware signal file is a file for storing response signal related information generated when the firmware executes the instruction information; in the execution process of playing back the instruction information, displaying the firmware program counting address based on the firmware program counting address and the reference address mapping table; according to the method, the debugging efficiency between the software and the firmware is improved.

According to the method, PCIe extended storage equipment is identified by responding to a system starting signal, and initialization and address mapping control logic is executed to construct a first address space addressable by a GPU (Graphics Processing Unit); then, loading model data according to an AI task instruction, and dynamically dividing hot, warm and cold multi-level data popularity levels by monitoring memory access frequency; a migration data block is generated based on the popularity level, a migration data flow is organized and verified through priority scheduling logic, and intelligent data scheduling between extended storage and a GPU video memory is achieved; finally, the resources are released after the task is completed. Therefore, dynamic expansion of the physical video memory capacity is effectively achieved, large-scale AI model localization training is met, dependence on a high-end GPU chip is remarkably reduced, and data safety and system economy are improved.

The present application discloses an industrial Ethernet communication method and system, a network device, and a computer storage medium. The method comprises: receiving a PDO packet sent by an industrial master station or a previous industrial slave station, and determining whether to forward the PDO packet to a next industrial slave station; and when a frame processing unit receives the PDO packet returned from the next industrial slave station, or determines that the PDO packet is not forwarded to the next industrial slave station, and if it is determined, on the basis of a preset address mapping rule, that a read instruction is present in the PDO packet, responding to the read instruction to write read target data into a target position of the PDO packet, and then forwarding the PDO packet to the industrial master station or the previous industrial slave station.

The invention discloses a system and method for improving data configuration efficiency of a test machine, and relates to the technical field of board card testing, the system comprises an FPGA PCIE module, a DMA address data analysis module and a data transmission module, a general data frame is divided into an independent 32b address field and an independent 32b data field through the arranged DMA address data analysis module, then bit [31] and 0 of an 32b address are analyzed to represent write operation, and the data transmission module is connected with the FPGA PCIE module. 1 represents read operation, an identifier is independently extracted and embedded into a subsequent instruction packet, then a bit [27: 0] of a 32b address is extracted, a target daughter card number is determined according to a preset address mapping table, and data is packaged after determination, so that data distribution of different address fields is realized, the data transmission module receives the data and then sends the data to each post-stage daughter card module in parallel, and data read-write is realized. Therefore, the read-write speed of the test machine is greatly increased, and the read-write efficiency is further improved.

Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input / output (I / O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.

A data reading / writing method includes a processor that sends a read / write request to the storage. The read / write request is used to request to perform data reading / writing in the storage, and the read / write request carries a logical address of data. After receiving the read / write request, the storage maps the logical address to target positions in banks of N storage chips in the storage, and performs data reading / writing at the target positions in the banks of the N storage chips. The target positions in the banks of the N storage chips are distributed in different areas.

The invention relates to the technical field of code generation, in particular to an implementation method for automatically generating register array codes. Reading register information of a register; constructing a register to design a digital twinborn body, performing early risk assessment on structured definition information, and outputting a risk report and an optimization strategy; running the formalized guarantee engine to verify the design logic, and obtaining a verification result, counter-example information and a first credibility score; operating an intelligent optimization engine, and outputting an optimization suggestion, a second credibility score and a consistency identifier; based on the verification result and the optimization suggestion, generating a final register hardware code, an embedded assertion and address mapping table, and synthesizing the first credibility score, the second credibility score and the consistency identifier to generate an overall credibility score; and iteratively updating the digital twin and the intelligent optimization engine according to the verification data and the performance data. According to the method, the register array code can be automatically generated with high credibility.

A computer express link fabric having: a plurality of computer express link switches; a plurality of computer express link connections among the computer express link switches; and a controller. The controller is configured to: map memory addresses in a mapped memory space to physical addresses of random access memory cells of memory devices connected to the computer express link fabric; and implement, in a storage space of a memory sub-system connected to the computer express link fabric and having non-volatile memory cells, a persistent copy of data stored by memory access requests received in the computer express link fabric and having memory addresses in the mapped memory space.

The invention provides a memory erasing management method and device, electronic equipment and a storage medium. Determining a target storage page for storing the to-be-processed data according to the erasing management information in the management area of each storage page; determining a first logical address corresponding to a first physical address of the target storage page and a second physical address corresponding to a second logical address of the to-be-processed data according to page address mapping information in the erasing management information; switching the mapping of the first logic address to the second physical address, switching the mapping of the second logic address to the first physical address, and updating the read erasing management information; and writing the to-be-processed data into a content area of the target storage page based on a mapping relationship between the second logic address and the first physical address. According to the method, the appropriate target storage page is selected for the to-be-processed data to be stored, so that all the storage pages are subjected to balanced loss together, and the purpose of aging together is achieved.

The invention relates to the technical field of data storage, and discloses a memory particle test method, which comprises the following steps that: 32-bit memory particles relate to a first channel (16-bit) and a second channel (16-bit), the first channel (16-bit) and the second channel (16-bit) of the 32-bit memory particles correspond to physical blocks in the 32-bit memory particles, the 16-bit memory particles only relate to the first channel, and the second channel (16-bit) corresponds to physical blocks in the 32-bit memory particles. The first channel corresponds to a physical block in the 16-bit memory particle; all memory spaces of the 16-bit memory particles are scanned through a program of the 32-bit test system, if errors occur in the program, it is judged that the corresponding program relates to the second channel, codes related to the second channel in the test system are found, and the codes corresponding to the second channel are shielded. By means of channel shielding, code modification, address mapping and the like, compatibility of the 32-bit test system to two kinds of particles is achieved.

The invention relates to the technical field of computers, in particular to a data transmission method and device, electronic equipment and a storage medium, and is used for improving camera data transmission efficiency in a cross-system environment. The method is applied to the electronic equipment comprising a host machine, the host machine is used for creating and running a virtual machine through a virtualization engine, and operating systems are different. The method comprises the following steps: in response to an image acquisition request initiated by a target application in a virtual machine, creating a shared memory area through a host machine; calling an image acquisition device through a host machine to obtain image frame data, and storing the image frame data in a shared memory area; mapping a physical address of the image frame data in the shared memory region into an initial address visible to a virtual machine through a virtualization engine; mapping the initial address to a virtual address space of the application process layer by layer through an operating system of the virtual machine to obtain a target address; and reading the image frame data from the shared memory area based on the target address, and displaying the image frame data on the target application.

The invention discloses an SSD (Solid State Disk) garbage collection method and device with RAID (Redundant Array of Independent Disk) redundancy and a medium, and relates to the technical field of garbage collection, and the method comprises the following steps: in a garbage collection process, selecting a target NAND flash memory physical block of which the effective data volume meets a collection condition, copying the effective data to a new position, and updating address mapping; querying a first RAID block to which the target block belongs and all member block identifiers thereof according to a first mapping table and a second mapping table which record a mapping relationship between the NAND flash memory physical block and the RAID blocks; and recombining other blocks except the target block in the first RAID block into a second RAID block, recalculating and storing verification data for the second RAID block, synchronously updating the two mapping tables to reflect a new composition relationship, and finally erasing the target block. The physical block of the NAND flash memory is used as the minimum recovery unit to replace the traditional recovery mode taking the whole RAID block as the unit, and the block with the minimum effective data can be preferentially recovered, so that the effective data migration amount is remarkably reduced, the write amplification coefficient is reduced, the abrasion is reduced, and the service life of a hard disk is prolonged.

The invention provides a display device and a system performance optimization method, and the method comprises the steps: determining a hotspot scene item according to a hook function set and operation behavior data of a user, and carrying out the sampling of a process in the hotspot scene item, and obtaining a function sampling result; determining a hotspot function according to a preset sampling proportion and the function sampling result; copying the hotspot functions into a pre-applied continuous memory, and modifying reference addresses of the copied hotspot functions to merge the hotspot functions to obtain a hotspot function set; and mapping the preset virtual address to the hotspot function set. According to the method, hot scene items can be analyzed and hot functions and hot access files can be identified based on user interaction statistics, the smoothness of user operation is ensured through merging of the hot functions and preloading of the hot access files, the page missing phenomenon of memory access is reduced, the system performance is improved, and the user experience is improved. The problem of operation lagging or response delay caused by page missing of the memory access page and the like is solved, and the system operation efficiency and the system performance are improved.

The invention discloses a data access method and device in a multi-tenant environment, equipment and a storage medium, and belongs to the technical field of computer networks. The method comprises the following steps: acquiring configuration information of message-oriented middleware from custom resources; the custom resource is a data source instance for defining the message middleware in the function service platform; the configuration information comprises a tenant identifier; allocating a virtual address to a real address of the message-oriented middleware according to the tenant identifier to obtain address mapping information; the address mapping information comprises tenant identifiers of different message middleware and a mapping relationship between the tenant identifiers and virtual addresses, and different tenant identifiers correspond to different virtual addresses; and in response to a data access request of a tenant, forwarding the data access request through the cross-private cloud channel according to the address mapping information, so as to realize cross-private cloud access of the tenant to the message-oriented middleware. According to the method and the device, the problems of communication failure, data isolation failure and the like caused by possible conflicts of internet protocol addresses in a multi-tenant environment can be solved.

The invention discloses a data processing method, a multi-core heterogeneous system and a computer readable storage medium, and belongs to the technical field of data processing.The method comprises the steps that in the initialization stage of a hardware system, a physical storage space is allocated based on a predefined physical address boundary, and the physical storage space comprises a shared space; writing predefined configuration data corresponding to the shared space into a configuration register of the storage management module and latching the configuration register, wherein the configuration data comprises an access control strategy and a storage attribute; in the starting stage of the operating system, an address mapping relation is obtained, the address mapping relation comprises a target mapping relation, and under the condition that the operating system runs, a storage management module is triggered based on an instruction of a target operation to execute the target operation based on the address mapping relation, configuration data and a virtual address corresponding to the instruction, the target operation is read operation or write operation. The calculation amount of the processor is greatly reduced, and the time consumption for reading and writing data is reduced on the whole.

A method for sharing a distributed video memory across process groups and a computing device, the method comprising: in response to receiving a recovery instruction from an upper application, a first process in a plurality of processes traverses metadata of each virtual address in a first metadata table thereof, mapping a first physical address to each of the plurality of first virtual addresses of the local mapping type, wherein the recovery indication is sent by the upper application after determining that the second process group releases the video memories of the plurality of GPUs; under the condition that metadata of a target virtual address in the plurality of first virtual addresses comprises a reference relationship between a second virtual address in a second process and the target virtual address, the first process provides a first export value corresponding to the second virtual address and a target physical address to the second process, the target physical address is used for exporting the video memory from the second process, and the target virtual address and the target physical address are mapped.

The invention relates to an electrocardio atrial fibrillation classification detection method, system and device capable of resisting individual difference and a storage medium. The system comprises a signal acquisition module used for acquiring ECG signals; the invention discloses an anti-individual-difference preprocessing circuit. The signal segment reading module is used for reading a signal segment according to an overlapping segmentation strategy, the Hanning window weighting module is used for performing window function weighting on the signal segment and only storing a first half coefficient through address mapping multiplexing by utilizing the symmetry of a window function, and the FFT frequency domain transformation module is used for converting a time domain signal into a frequency domain; the QRS frequency domain enhancement filtering module is used for enhancing QRS spectrum components and attenuating individual difference frequency components, the IFFT time domain reconstruction module is used for converting frequency domain signals back to a time domain, and the amplitude normalization output module is used for eliminating signal amplitude differences among individuals; and the deep learning classification module is used for performing atrial fibrillation detection on the standardized signal. Based on a CPU and FPGA heterogeneous architecture, the accuracy and robustness of atrial fibrillation detection are improved, and the method is suitable for the fields of wearable monitoring, telemedicine and the like.

The invention discloses a data protection method, a memory, electronic equipment and a storage medium, and relates to the field of storage, the method is applied to the memory, and a logical address-to-physical address mapping table is configured and comprises a first mapping area and a second mapping area; wherein the first mapping area is used for recording an original mapping relation between a logic address and a physical address corresponding to read-write operation performed on the snapshot area before the snapshot protection mode is started; the second mapping area is used for recording a mapping relation between a logic address and a physical address corresponding to incremental read-write operation executed on the snapshot area after the snapshot protection mode is started; after a snapshot starting instruction is received, entering a snapshot protection mode, and determining a snapshot area needing to be protected according to preset configuration information; and locking an original mapping relation of the snapshot area in the first mapping area, and redirecting a data operation request initiated for the snapshot area to the second mapping area to execute incremental read-write operation.

This disclosure provides an I2C address conflict handling method, apparatus, device, and storage medium, relating to the field of computer technology and applied to BMC (Bus Management Center). The method first identifies address conflict events on the I2C bus and determines at least two conflicting devices and their address modification capabilities. Then, based on the address modification capability information, a target resolution strategy is selected from preset multi-level resolution strategies, and a target I2C address is matched to the target conflicting device from the address pool. Next, the target resolution strategy is executed, changing the I2C address of the target conflicting device to the target I2C address. Finally, the device address mapping table is updated, and the conflict handling information is recorded in a conflict tracing database. This solution achieves automated detection and resolution of I2C address conflicts, is compatible with various address modification capabilities, avoids manual intervention and secondary conflicts through dynamic address pool management and multi-level strategy adaptive selection, and establishes a full-process tracing mechanism, improving bus communication stability and operational efficiency.

The invention discloses an LWIP TTE network adaptation system based on a static ARP table. The LWIP TTE network adaptation system comprises a transmission module, a protocol conversion module, an LWIP protocol stack and a network calling module. The transmission module enables the standard TTE frame to be normally transmitted on the TTE switch; the protocol conversion module is used for protocol adaptation and data conversion; the LWIP protocol stack is used for packaging data needing to be sent and analyzing a received standard IP data packet; and the network calling module is used for transmitting the data and the target IP address information to the LWIP protocol stack and receiving a data packet fed back by the LWIP protocol stack. Protocol adaptation and data conversion are carried out through the protocol conversion module, the communication barrier between an IP protocol and a TTE protocol is broken, and conversion from an IP address to a communication identifier supported by TTE is realized; the network adaptation system uses the simple query logic of the LWIP protocol stack and the static address mapping table, so that the embedded program developed by depending on the TCP / IP protocol stack can be accessed to the TTE network at low cost, and the complexity of program migration work is simplified.