113 results about "Process memory" patented technology

The browser tab page data storage method supporting data encryption comprises the steps that browser tab page interaction behaviors are monitored in real time to generate a dynamic factor, and a session key dynamically changing along with the life cycle of a tab page is generated in combination with a process ID of the tab page; based on a self-adaptive encryption strategy, respectively encrypting structured data and unstructured data of the label page; wherein the structured data are encrypted according to field sensitivity levels, and the unstructured data are encrypted through mapping binding of a secret key and the data; the encrypted data and a timestamp voucher of the session key are stored in an associated mode, decryption operation is only allowed to be completed in a label page process memory generating the session key, and the session key is not stored in a landing mode; and when the label page is closed, synchronously clearing the decryption data in the session key and the process memory. According to the method and the device, the defects that the dynamic generation of the key cannot be realized and the key cannot fall to the ground at present are overcome.

The invention discloses a model scheduling method and device based on multi-level cache, equipment and a medium, and relates to the field of artificial intelligence, and the method comprises the steps: in a model deployment process, updating the current model popularity of a corresponding to-be-reasoned model in a preset cache architecture based on an obtained model access request; wherein cache layers of the preset cache architecture are respectively a video memory cache layer, a process memory cache layer, a shared memory cache layer and a persistent cache layer from top to bottom; determining a target cache layer of the to-be-reasoned model in a preset cache architecture, and when the target cache layer is a video memory cache layer, triggering a preset reasoning operation on the to-be-reasoned model; and when the target cache layer is a non-video memory cache layer, scheduling the to-be-reasoned model to the video memory cache layer based on each current model heat in other cache layers located above the target cache layer, so as to trigger a preset reasoning operation on the to-be-reasoned model in the video memory cache layer. Therefore, efficient utilization and intelligent management of model resources can be realized.

The invention relates to a method for optimizing electroplating and etching process parameters, which comprises the following steps of: establishing an interface migration behavior relationship by analyzing the influence of metal ions, doped impurities and surface roughness factors on a reaction interface migration rate and a boundary layer flow behavior in an electroplating and etching process; interface migration behaviors are combined with parameter sensitivity analysis, the influence of process parameters on the interface behaviors is dynamically evaluated, and priority optimization sorting is carried out; dynamic interval zooming is carried out on the sensitive parameters by using the fitted sensitivity function, and a local adjustment range is generated according to material types and graph complexity; a preorder process memory mapping relation is introduced, and morphology evolution information recorded in the electroplating process is transmitted to an etching parameter optimization module; local fine adjustment is carried out on the etching rate, angle control and a disturbance mechanism, and the previous electroplating state is responded; collecting a fluctuation interface feedback signal; establishing a closed-loop optimization control loop of micro-disturbance, response evaluation and parameter correction; and the process consistency and the structure uniformity are improved.

The invention discloses an API-oriented dynamic fuzz testing and vulnerability detection method, and belongs to the technical field of software security testing. The method comprises the following steps: extracting a dependency relationship, an input parameter, an output response and context state data of API calling, generating an initial API dependency graph, dynamically updating by capturing API state change in real time, forming an API state graph, and executing boundary-oriented variation based on parameter constraint characteristics, so as to obtain an API state graph; generating a variation test parameter, calling an API (Application Program Interface) of the variation test parameter to monitor a process memory behavior and response metadata, and generating a multi-dimensional abnormal signal; and performing mode matching on the abnormal signal and the vulnerability feature knowledge base, outputting a vulnerability type label and generating a path tracing report. According to the method, a context state sensing dynamic graph modeling technology is adopted, and a boundary-oriented intelligent variation strategy and multi-source abnormal behavior collaborative analysis are combined, so that precise vulnerability triggering, intelligent vulnerability judgment and complex scene coverage can be realized.

The invention relates to an artificial intelligence chip, a method for processing memory access related instructions, a computing device, a computer readable storage medium and a computer program product. The artificial intelligence chip comprises a calculation core, the calculation core comprises a calculation unit, the calculation unit at least comprises a loading storage cache module, the loading storage cache module comprises a queuing module, the queuing module is configured to process memory access related instructions which do not carry predetermined modifications in a predetermined domain segment, and the queuing module is configured to queue the memory access related instructions; the predetermined modification indicates whether the memory access related instruction bypasses the queuing module and is provided to the bypass module; and the bypass module is configured to process the memory access related instruction with the predetermined modification carried by the predetermined domain segment. According to the invention, the queuing and arbitration time delay of the memory access request can be obviously reduced, and the response time of the memory access request is reduced.

The invention discloses an intelligent agent memory management method and system. According to the method, deep semantic organization of memory content is realized by defining a structured memory unit containing ternary metadata formed by a multi-label set, a multi-dimensional attribute set and a multi-level path; and receiving and processing a memory operation from any trigger event through a unified memory management framework. According to the method, the problems of low retrieval precision, poor data isolation between instances and tight coupling with service logic caused by flattening of a memory structure of an existing agent system are effectively solved, and the performance, the safety and the expandability of the agent system in enterprise-level application are remarkably improved.

The invention relates to a memory data processing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring a firmware program file and a program running condition of the firmware program file; dividing the firmware program file into a plurality of program section files according to the program running condition; in response to a state transition instruction of a target host, obtaining state indication information and shared memory information corresponding to the target host; and selecting part of the program segment file as a target program segment file according to the state indication information, and transferring the target program segment file to a shared memory of the target host according to the shared memory information. By adopting the method, the problem of insufficient memory in the running process of the system can be solved.

Various embodiments include techniques for processing memory operations in a computing system. The computing system includes a central processing unit (CPU) and an auxiliary processor, such as a parallel processing unit (PPU). The PPU can be divided into multiple partitions. Although the partitions are included in a single PPU, the CPU can track the partitions as if the partitions are independent devices rather than different portions of a single device. When two different partitions generate memory operations that access the same memory address in CPU memory address space, the two partitions employ two different data paths. The CPU can use path information for the two different paths to identify which partition generated each memory operation. As a result, the CPU can maintain data consistency and memory coherency in a system where a PPU is divided into multiple partitions.

The invention provides an extensible near-memory computing coprocessor architecture for a computing system. The architecture comprises a main processor; the storage module comprises a plurality of storage particles, and the storage module is configured to store calculation data required by the main processor; the at least one near memory coprocessor is integrated with all the storage particles through 2D, and the interface protocol of the near memory coprocessor architecture is the same as the interface protocol of the storage particles; the near-memory coprocessor is configured to perform near-memory computation on a storage-intensive computation task and store a result of the near-memory computation into the storage particle. Through the framework, the problem that the efficiency is low when an existing processor framework processes memory access intensive tasks is solved.

The invention discloses a controller memory buffer management method, system and device, a medium and a product, and relates to the technical field of data storage, and the method comprises the following steps: obtaining state information of a memory block; determining a first to-be-processed memory block and a second to-be-processed memory block according to the state information; if the size of the fragments is greater than a threshold value, recycling the fragments; and generating a virtual address according to the physical address of the second to-be-processed memory block, and mapping the second to-be-processed memory block into a continuous memory space. The problem that discontinuous memory blocks and memory blocks containing fragments are prone to occurring in a memory buffer area of a controller, and communication delay of SSD access of a host is increased can be solved. According to the method, the fragments of the memory blocks can be rapidly detected and arranged, the fragments are recycled, the space utilization rate of the CMB is improved, the second to-be-processed memory block is mapped into the continuous memory space through the virtual address, it is ensured that the host can logically access the continuous memory space, and the addressing frequency is reduced.

The embodiment of the invention provides a memory strategy management method and device, and relates to the technical field of computers.The method comprises the steps that a kernel of a multi-memory-node system receives a strategy setting request sent by a first process through preset system calling, and the strategy setting request comprises strategy setting parameters and an identifier of a second process; verifying the permission and strategy setting parameters of the first process and the second process; if it is determined through verification that the first process has the permission to modify the memory strategy, the strategy setting parameters are legal, and the second process exists, the memory strategy of the second process is processed according to the strategy setting parameters. According to the scheme, the problems that in the prior art, cross-process memory strategy management operation is complex, flexibility and adaptability are insufficient, and extra safety risks, performance fluctuation and instability are possibly introduced can be solved.

An electronic device includes: at least one processor comprising processing circuitry; and memory, comprising one or more storage mediums, a decoder, a post-processing memory, a renderer, the memory being configured to store instructions, wherein the decoder is configured to decode a frame among a plurality of frames of a video stored in an input buffer, and to generate a decoded frame. The post-processing memory may post-process the decoded frame, and to generate a post-processed frame. The renderer may render the decoded frame or the post-processed frame stored in an output buffer. The instructions may cause the electronic device to: set the output buffer based on time required for a post-processing, and adjust a speed of inputting the plurality of frames into the input buffer based on a speed at which the rendered frame is played via a display.

The invention discloses a memory recovery method and device, a vehicle, electronic equipment and a storage medium, and the method comprises the steps: obtaining a remaining memory amount in response to a memory recovery signal, and judging whether the remaining memory amount is lower than a remaining memory upper limit or not; the residual memory capacity is a difference value between the system memory capacity and all process memory capacities; when the remaining memory amount is lower than the upper limit of the remaining memory, sequentially detecting whether the process memory amount of each process exceeds a respective corresponding memory available threshold value or not, and determining the process exceeding the memory available threshold value as a to-be-recycled process; and respectively carrying out memory recovery processing on all the processes to be recovered. According to the memory recovery method provided by the invention, after it is predicted that the remaining memory amount is lower than the upper limit of the remaining memory, the process memory amount of each process is detected in sequence, the to-be-recovered processes are determined, and all the to-be-recovered processes are subjected to memory recovery processing, so that the memory recovery efficiency is improved, and safe, stable and efficient operation of a system is ensured.

The invention provides an extensible near-memory computing coprocessor architecture for a computing system. The architecture comprises a main processor; the storage module comprises a plurality of storage particle layers, each storage particle layer comprises a plurality of storage particles, and the storage module is configured to store calculation data required by the main processor; the at least one near-memory coprocessor is integrated with the at least two storage particle layers through 3D, and the interface protocol of the near-memory coprocessor architecture is the same as the interface protocol of the storage particles; the near-memory coprocessor is configured to perform near-memory computation on a storage-intensive computation task and store a result of the near-memory computation into the storage particle. Through the framework, the problem that the efficiency is low when an existing processor framework processes memory access intensive tasks is solved.

The invention relates to the technical field of artificial intelligence, and provides a memory data processing and question answering method and device of a large language model, computer equipment and a readable storage medium. The memory data processing method of the large language model comprises the following steps: according to a memory summary template of a business field to which a to-be-processed dialogue record fragment of the large language model belongs, performing memory summary on the to-be-processed dialogue record fragment to obtain a to-be-processed memory stream; performing conflict detection on the to-be-processed memory stream and a memory stream in a memory database of the large language model; when a conflict detection result shows that the high-correlation memory flow of the to-be-processed memory flow exists in the memory database, determining a memory update content type of the to-be-processed memory flow; and according to the memory update content type, determining a corresponding processing measure so as to perform corresponding processing on the to-be-processed memory flow and the high-correlation memory flow. By adopting the method, the accuracy of model answering can be improved.

The invention relates to the technical field of CAE (Computer Aided Engineering) software, in particular to a memory management method for a CAE software iterative solution method, which comprises the following steps of: pre-loading a memory management library when the CAE software is started; when the CAE software is iterated for the first time, a memory management library is called to allocate a memory, and a preposed central memory pool and a preposed process memory pool are established; in the first iteration process, memory portrait information is collected, and a memory portrait database is established; during subsequent iteration of the CAE software, the memory management library establishes a central memory pool according to the memory portrait database; before each iteration of the CAE software starts, the process memory pool is established for each process according to the memory portrait database, and by means of the scheme, the problem that the overall performance of a CAE software iteration solution method is low due to low memory management efficiency is solved.

The invention provides a data prefetching method, and relates to the technical field of artificial intelligence, in particular to the technical field of chips and the technical field of caches. The specific implementation scheme is as follows: in response to the situation that the number of available resources in a missed state temporary storage unit is greater than or equal to an available number threshold value for a to-be-processed memory access instruction and the to-be-processed memory access instruction hits target prefetch information, determining a prefetch address according to an access address of the to-be-processed memory access instruction and a prefetch offset in the target prefetch information; the available number threshold value is determined according to continuous memory access information for the memory access instruction to be processed, and the continuous memory access information is determined according to a plurality of continuous first memory access instructions in a memory access time period for the memory access instruction to be processed; the plurality of continuous first memory access instructions are a plurality of instructions with the same offset of any two adjacent addresses in the memory access time period. The invention further provides a data processing device, electronic equipment and a storage medium.

The application discloses a trend early warning method, device and equipment of a converter valve cooling system and a medium. The method is to use disturbance recording wave data generated by periodic switching of a main pump to extract characteristic parameters representing system operation states to form a training set and a verification set. Then, a new observation vector selects training set data according to a KNN strategy to dynamically construct a process memory matrix and obtains an estimated vector according to multivariate state estimation. The cosine similarity of the estimated vector and the observation vector is calculated. The cosine similarity statistical value of the verification set is used as a warning threshold. The cosine similarity of the observation vector is compared with the warning threshold, and a trend early warning is issued. The application extracts characteristic parameters by using disturbance recording wave data generated by periodic switching of a main pump, solves the problem that the converter valve cooling system cannot perform fluid parameter trend early warning, and is simple and easy to implement.

Examples provide an apparatus, device, method, computer program and non-transitory machine-readable storage medium including program code for processing memory spill code during compilation of a computer program. The non-transitory machine-readable storage medium includes program code for processing memory spill code during compilation of a computer program, when executed, to cause a machine to perform identifying a plurality of instructions related to scalar memory spill code during compilation of a computer program, and transforming at least a subset of the plurality of instructions into vectorized code.

The invention provides an offline data processing method and device, terminal equipment and a storage medium, and belongs to the technical field of data processing. The method comprises the following steps: acquiring offline SQL data corresponding to a current fault; compressing the offline SQL data to obtain compressed SQL data; obtaining a current fault type, and predicting a current fault duration period according to the current fault type; predicting the offline SQL volume of the fault according to the duration period of the fault; if the duration period of the fault is less than a preset period and the offline SQL volume of the fault is less than a preset volume, writing the compressed SQL data into a process memory, otherwise, writing the compressed SQL data into a local disk; wherein the preset volume is a preset percentage of the available volume of the current process memory. According to the method and the device, the occupied space of the offline SQL data can be reduced, and application scenes with a relatively long fault period and a relatively short fault period can be considered.

Aspects of the embodiments are directed to systems, devices, and methods for accessing a storage device as memory. The embodiments include a microprocessor comprising a microprocessor system agent and a field programmable gate array (FPGA). The FPGA includes the FPGA system agent that processes memory access requests received from the microprocessor system agent across a communication link; a memory controller communicatively coupled to the system agent; and a high-speed serial interface linking the system agent with the storage system. The embodiments may also include a storage device connected to the FPGA via the high-speed serial interface.

The application discloses a code injection attack analysis and detection method and system, and belongs to the technical field of computer network security, and the method comprises the steps of: reproducing a known code injection attack under a Windows monitoring environment, and constructing an API feature stack frame list; monitoring cross-process memory page allocation of a target program, and constructing a floating memory page list; based on the API feature stack frame list and the floating memory page list, performing code injection attack analysis and detection on the target program; and using ETW log monitoring technology to realize asynchronous monitoring of memory page permission modification operations, and regarding abnormal permission modification behavior on the floating memory page as illegal behavior. The application can realize real-time monitoring of abnormal behavior detection code injection attack behavior in a Windows operating system.

The present application discloses a method, device and storage medium for monitoring the memory of a process. In the case where a target process loads a target program, the method collects a reference value of the target program; and respectively in the loading stage and the running stage of the target program, obtains the code segment and the data segment corresponding to the target program, and performs hash calculation to obtain a first hash value and a second hash value, and then determines the monitoring result of the target process by comparing the first hash value and the second hash value with the reference value respectively. The process monitoring method provided by the present application not only monitors the process in the stage where the target process loads the target program, but also monitors the process in the stage where the target process runs the target program, expands the monitoring scope of the process, realizes the monitoring of the entire running process of the target process, and improves the security of the process running.

The embodiment of the invention provides a management method for processing bad blocks of a memory and a memory system. A coding management circuit; and a memory access instruction decoding unit. The memory access instruction decoding unit is used for receiving an instruction from a bus; identifying bad blocks in the memory; judging whether the instruction indicates to access the bad block or not; when the instruction indicates that data is written into the bad block, the address of the bad block and the data are output to the coding management circuit so as to trigger the coding management circuit to update the coding management circuit; when the instruction indicates to read the bad block, the address is output to the coding management circuit so as to trigger the coding management circuit to output simulation data of the bad block, and the coding management circuit obtains the simulation data according to the address.

Systems and methods for collecting and processing memory-related data and synthesizing memory-based narratives that includes collecting memory input data from one or more users, constructing a memory graph comprising a hierarchical data structure including one or more graphical nodes for storing the memory input data, assimilating the memory graph into a semantic collage of distinct memory graphs, generating a mnemonic narrative artifact comprising memory input data from related memory graphs, and surfacing the mnemonic narrative artifact via a user interface to one or more users.

The present application discloses a method and system for managing memory of an external device, which relates to the field of computer technology. The method and system include obtaining device information of an external device; constructing a device priority database based on the device information, wherein the device priority database includes at least the device type, the device hot-swap status, the resource occupancy of the external device, and the priority; dividing the system runtime memory into multiple sub-memory pools based on the priority of the device in the device priority database, wherein the sub-memory pools are used to process memory requests of devices of preset importance; managing the sub-memory pools using preset management rules corresponding to the sub-memory pools to manage the memory of the external device, thereby solving the technical problem of low memory management efficiency caused by the inability to perform dynamic adjustment when memory demand fluctuates in high-density device scenarios, and achieving the technical effect of dynamically adjusting memory resources and improving memory management efficiency.

Disclosed embodiments relate to systems and methods for securely storing a secret. Techniques include accessing a secret associated with a network identity and generating a primary encryption key for encrypting the secret. Generating the primary encryption key includes: accessing a first encryption key associated with the network identity, accessing a second encryption key stored in a process memory location associated with a machine of the network identity, and applying a primary key hash function to the first encryption key and the second encryption key to generate the primary encryption key. Techniques further include encrypting the secret using the primary encryption key to generate an encrypted secret; obfuscating the encrypted secret to generate an obfuscated encrypted secret; and storing the obfuscated encrypted secret in a secured storage location associated with the machine of network identity.

This application discloses a multi-agent collaboration method, apparatus, electronic device, and storage medium. The method includes, in response to a user-input query, determining the scope of agents to be invoked in a model decision-making stage. This model decision-making stage invokes at least process memory and summary memory. The process memory records the temporal trajectory, type, and triggering conditions of each agent's invocation, while the summary memory simplifies the memory information for each round of interaction. Based on the scope of agents to be invoked, the generated content of each agent is decomposed in a model generation stage, which invokes at least the summary memory. Finally, based on the generated content of each agent, a final output result is obtained. This application achieves a stronger understanding and decomposition capability for user-fuzzy questions, understanding user questions at the memory level, thereby invoking agents not mentioned in the user question and completing multi-agent collaboration.

The invention discloses an interconnection query method and device for database computing nodes, equipment and a medium. The method comprises the following steps: in response to a data query request of a client, performing identifier existence verification on a communication query identifier of the data query request to obtain an identifier verification result; if the identifier verification result is that the data query request has the connected query identifier, determining a to-be-connected computing node from the candidate computing nodes according to the data query request; according to the data query request, determining a sub-query request of a to-be-connected computing node, and sending the sub-query request to the to-be-connected computing node; when candidate memory table data returned by the computing node to be connected is received, determining processed memory table data and unprocessed memory table data according to the candidate memory table data; and determining a target query result according to the processed memory table data, the unprocessed memory table data and target memory table data of the target computing node. According to the technical scheme, the database query efficiency and flexibility can be improved.

1. Name of the product in this design: Graphical User Interface for Memory-Assisted Analysis Tool for Electronic Devices. 2. Purpose of this design: An electronic device. 3. The key design features of this product are: the content of the graphical user interface in the electronic device. 4. The picture or photo that best illustrates the key design points: Design 1 front view. 5. As is customary, the top view, bottom view, left view, right view, and rear view of each design are omitted. 6. Design 1 is designated as the basic design. 7. Purpose of the graphical user interface: for monitoring and analyzing process memory handle data. 8. Human-computer interaction method of graphical user interface: Design 1 main view displays process Memory data in multiple dimensions; clicking the drop-down list control containing the text "Memory" in the top toolbar enters Design 1 change state diagram 1, which displays the sub-item list of the drop-down list; clicking the "Handle" sub-item in the sub-item list enters Design 1 change state diagram 2, which displays Handle data. Design 2's main view displays multi-dimensional process Memory data; clicking the drop-down list control containing the text "Memory" in the top toolbar enters Design 2's change state diagram 1, displaying the drop-down list's sub-items; clicking the "Thread" sub-item in the sub-item list enters Design 2's change state diagram 2, displaying Thread data. Design 3's main view displays process memory data across multiple dimensions; clicking the dropdown list control containing the text "Memory" in the top toolbar leads to Design 3's change state diagram 1, displaying the dropdown list's sub-items; clicking the "Cpu" sub-item in the sub-item list leads to Design 3's change state diagram 2, displaying CPU data.