212 results about "Virtual memory" patented technology

The invention provides a complex scene-oriented AI large model lightweight deployment method, and relates to the technical field of edge computing, and the method comprises the steps: carrying out the structured pruning of a pre-trained Transform network based on the attention head importance score, carrying out the dynamic sparsification of the activation state of a feedforward network according to the input tensor entropy value, employing the dynamic mixing precision quantization, and carrying out the reconstruction of an AI large model. Obtaining network parameters after pruning quantization; deploying the pruned and quantized network parameters to an edge computing device, distributing a feature extraction operator to a neural network processor through a heterogeneous computing scheduler, and unloading a classification operator to a multi-core central processing unit; and managing an on-chip memory in combination with a virtual memory paging mechanism, realizing zero-copy data transmission by utilizing a direct memory access controller, and outputting a reasoning result tensor. According to the method, efficient and reliable operation of the large model at the resource-constrained edge node is realized.

The invention relates to a memory management method and device applied to a server-free data center, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in response to a virtual memory application instruction, performing virtual memory allocation in a local computing resource pool to obtain a virtual address space; in response to the virtual address access instruction, acquiring cache information of the computing resource pool, and triggering missing page interruption under the condition that data corresponding to the virtual address is not hit in the cache information; the cache information comprises locally cached cache data and page table information; acquiring physical memory resources in a memory resource pool according to the virtual address and the page table information under the condition of triggering missing page interruption of the anonymous page; and updating the page table information and the cache information according to the physical memory resources. By adopting the method, the processing delay of the data center can be reduced while the decoupled memory management logic is used for improving the resource utilization rate.

The invention provides a hot upgrade method for a virtual machine monitor (VMM), which comprises the following steps of: pausing the operation of a virtual machine, storing state information of an original VMM, and reserving a kernel-based virtual machine KVM extension page table and a memory management structure of the original VMM; reserving a page global directory and a virtual memory area VMA corresponding to a virtual machine RAM area according to the memory management structure, and refreshing a process address space described by the memory management structure into a new VMM execution program so as to complete switching of the original VMM into the new VMM; and executing the new VMM, recovering the state information to the new VMM, and inheriting the KVM extension page table by the new VMM to recover the operation of the virtual machine. The invention further provides computer equipment, a computer readable medium and a computer program product.

Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.

The invention discloses a memory access method and device, a storage medium and a program product, and relates to the technical field of memory access, comprising: monitoring memory access information of a target memory; the memory access information comprises a missing page address sequence during memory access, an address distribution characteristic when an address conversion failure event occurs in an address conversion lookaside buffer, a cross-node access event and a virtual memory access frequency; determining corresponding target feature information; the target feature information comprises spatial locality, thermal density, access dispersion and unbalance degree data; and determining a current memory access mode based on the target feature information, and determining a target access strategy from preset memory access strategies configured with different memory page table prefetching rules to access the memory. The memory access feature information is quantified through the memory access information, the corresponding memory access mode is determined, and the corresponding memory page table prefetching rule is executed, so that the traversal delay of the multi-level page table can be reduced, and the memory access performance is improved by fully utilizing the memory bandwidth.

The invention relates to a progressive memory delay monitoring and diagnosis method oriented to a virtual memory subsystem. The method comprises the following steps: mounting a BPF program to a plurality of key event points on a kernel; when the key event point is triggered, acquiring state information of a corresponding event; packaging the state information into an event, and writing the event into a perf ring buffer associated with the outputmap; and the user mode program asynchronously reads the packaged event from the perf ring buffer, performs classification and aggregation according to the process and the event type, generates a delay terminal log and a histogram, and outputs a diagnosis result. Through systematic architecture design, the state keeping capability and the kernel context access capability of the eBPF are combined with an event model of a virtual memory subsystem, and a set of closed-loop monitoring system oriented to a diagnosis target is constructed. High-precision and high-reliability memory operation delay measurement is realized.

A file system in a user space partition of virtual memory may be mounted by a computing device that runs a virtual machine which includes a set of storage disks. The file system in user space may then expose one or more virtual files associated with one or more storage disks that correspond to one or more loop devices configured to map files of the virtual machine to the one or more virtual files. The computing device may then receive a request to read a data block stored at the virtual machine and may identify a file and corresponding virtual file that stores the requested data block based on a set of metadata provided by the loop devices. The computing device may then determine the location of the data block stored at the virtual machine, and may read the data block from the determined location.

Examples are disclosed herein relating to memory paging. In some examples, a host device is configured to communicate with an expansion device. The expansion device can include first and second memory, and a device virtual memory address (DVA) table. The expansion device can store data that can be requested by the host device. The first memory is a cache for the second memory based on a page presence table (PPT). The PPT can indicate a presence of second memory pages in the first memory cache. The DVA table can include information to locate data in the first memory based on a host physical memory address of a memory request. The device physical memory address can identify a memory location at which the data is stored. The data can be provided from the expansion device to the host device in response to the memory request based on the PPT.

The embodiment of the invention provides a core dump file generation method and device, electronic equipment and a medium, and relates to the technical field of data processing.The method comprises the steps that in response to abnormity of a target process, a thread causing the abnormity of the target process is determined as a target thread from threads of the target process; retrieving a virtual memory address from a register occupied by the target thread and a stack memory area of the target thread; determining a target address of a data page which belongs to a heap memory area and has mapping from the retrieved virtual memory address; and generating a core dump file containing the data page mapped by the target address. By applying the scheme provided by the embodiment of the invention, the validity of the core dump file can be improved while the size of the core dump file is reduced.

Examples of the present disclosure disclose a memory system and an operation method thereof and a storage device and an operation method thereof. The memory system includes a memory device and a memory controller, the kth memory blocks in memory planes in the memory device form one super memory block, super memory blocks form one virtual memory block, the mth physical pages coupled with the nth word lines in the memory planes from a same super memory block in the virtual memory block form one virtual physical page, the virtual physical pages from super memory blocks in a same virtual memory block form one strip; and the memory controller is configured to: receive memory data that needs to be written to a strip; generate parity check data of the strip according to the memory data; and send the memory data and the parity check data to the memory device.

The invention provides a dynamic adaptive memory and hard disk hybrid writing method and device. The method comprises the following steps: generating a spatio-temporal feature vector based on a memory access sequence; obtaining a popularity calculation formula according to the spatial-temporal feature vector, and calculating a data popularity value of the data memory by using the popularity calculation formula; obtaining a data popularity probability according to the data popularity value of the data memory; and dividing the memory data into four levels of superheat, heat, temperature and cold according to the data popularity probability, obtaining a comprehensive utilization rate by integrating three factors of a physical memory utilization rate, a system idle bandwidth and queue response delay, and executing a corresponding migration strategy according to the comprehensive utilization rate. Through real-time data popularity analysis, a difference bit pre-migration strategy and a dynamic priority adjustment algorithm, efficient identification and scheduling of cold and hot data of the virtual memory are realized, and the hybrid writing performance between a physical memory and a hard disk is optimized.

Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.

There is provided a method, system and non-transitory storage medium for serving a large language model (LLM) engine by allocating memory on demand. A virtual memory space with virtual pages is initialized for a tensor. A first request with first input tokens is received, added to the tensor by being allocated to first virtual pages and mapped to first page frames in physical memory. The tensor is provided to the LLM engine for processing. A second request with second input tokens is received, and a first output token is received from the LLM engine. The first output token is added to the tensor by being allocated to a second virtual page contiguous to the first virtual pages and mapped to a second page frame. The second input tokens are allocated to second virtual pages and mapped to second page frames in physical memory. The tensor is provided for further processing.

To provide an information processing device that enables overlapping of communication and calculation without buffering the communication between calculation processes on a host.SOLUTION: In an information processing device, a coprocessor-host memory translation function maps a calculation process virtual memory for a calculation process in a coprocessor provided in the information processing device to an offloading function virtual address for collective communication offloading. The collective communication offloading function uses the mapped offloading function virtual address to perform remote direct memory access (RDMA) for another information processing device connected via a network, and implements communication between the calculation process and a calculation process of the other information processing device.SELECTED DRAWING: Figure 1

The invention discloses an automatic AI memory leak intelligent positioning and root cause traceability analysis system, and relates to the technical field of memory leak intelligent positioning and root cause traceability analysis. The automatic AI memory leak intelligent positioning and root cause traceability analysis method includes the following steps: S1, data acquisition: performing index acquisition through a multi-dimensional data acquisition unit, and supporting physical memory and virtual memory utilization rate, heap and stack memory allocation and log release, object creation, track destruction and thread execution state index acquisition; according to the automatic AI memory leak intelligent positioning and root cause tracing analysis system, the leak position is positioned, the root cause can be analyzed from dimensions such as code defects, improper configuration and resource competition, the leak recurrence rate is reduced, normal memory fluctuation and a real leak mode are effectively distinguished through sliding window time sequence analysis, exception screening and feature engineering optimization, and the reliability of the system is improved. False alarms are reduced, and the accuracy of abnormal event identification is improved.

The application is suitable for the technical field of electric power, and provides a memory pool configuration method, system, electronic device and computer program product, wherein the method comprises the following steps: a first virtual relay protection device of a relay protection device is constructed; in a virtual communication environment, the number of memory pool nodes of the first virtual relay protection device is expanded from a first number to a second number based on the required storage space capacity size of power interaction data in communication; based on the second number of memory pool nodes, the capacity size types of memory blocks contained in all memory pool nodes in the virtual memory pool of the first virtual relay protection device are obtained, and the number of memory blocks of each capacity size type is obtained; based on the obtained information, the number of memory pool nodes of the relay protection device is adjusted to a third number, and a target number of memory blocks of the same capacity size type are configured for each memory pool node. The scheme can realize active optimization of memory pool configuration, reduce personnel cost, and improve memory pool configuration efficiency.

The present disclosure relates to a data processing method, device, system, computer device and storage medium. The method comprises: in the case of listening to an agent process updating a data set file corresponding to a service process, performing in-memory mapping on the updated target data set file to obtain a virtual memory address of the target data set file; releasing data in an original data set file in a physical memory of the service process; and writing data in the target data set file into the physical memory according to the virtual memory address of the target data set file. The embodiment of the present disclosure can reduce memory consumption.

A hardware mechanism at each dielet of a multi-dielet processing system is aware of engine page-table binds at all the dielets, thereby providing accurate traffic notifications to software (e.g., a unified virtual memory driver) for on-demand page-migration between system memory and GPU memory. The mechanism broadcasts binding information to access counters on each dielet so the access counters are able to correlate engines requesting memory access with bound virtual memory pages and generate corresponding informative notifications. A flexible multi-dielet counter clear capability enables software to clear access counters.

Provided is a computer agent and method to detect and prevent ransomware attacks early without losing customer data, without polluting the customer's file system or consuming any space on a storage device. The computer agent installs a kernel mode layered file system driver which is attached to encryption level group of a filter manager. With this layered file system filter driver design, it creates virtual canary files in directories which appear like normal files to any user or application though these files will not reside on disk. These virtual canary files are spread as baits across the file system to detect and prevent any malicious attack from any process or application. So that the Virtual Canary Files do not consume a large amount of memory, internal structures representing Virtual Canary Files are placed in virtual memory, but actual contents of the Virtual Canary Files do not reside in virtual memory. Other embodiments disclosed.

The embodiment of the invention provides a memory control method, computing equipment, a storage medium and a program product. The method comprises the steps of obtaining a heap expansion request for a heap memory of an application program; in response to the heap expansion request, allocating a virtual memory page with a large page size for the application program based on the heap memory; wherein the initial address of the virtual memory page is aligned according to the size of the large page; the virtual memory page is used for mapping to a physical memory page corresponding to the large page size, and generating a page table item according to a mapping result. According to the technical scheme provided by the embodiment of the invention, the virtual memory page with the large page size is allocated, and the initial address of the virtual memory page is aligned according to the large page size, so that the system performance is effectively improved, and the memory access efficiency is improved.

Disclosed in the embodiments of the present application are a root file system loading method and a related apparatus. In the method, a part of a virtual memory is simulated as a random access memory disk (RAMDISK) mechanism used by a block device. First, a read-only memory file system (ROMFS) mirror image file on an initial physical address is acquired; and then, a virtual address corresponding to the initial physical address of the ROMFS mirror image file is directly used as the starting address of the block device, such that the copy operation of copying the ROMFS mirror image file to the block device is executed on the initial physical address, thereby formatting the block device. Then, a kernel can be booted by means of mounting the ROMFS mirror image file in the block device as a root file system. By using the ROMFS image file as a root file system and reducing copy operations during a boot process, the kernel boot time is shortened in read‑only application scenarios requiring fast boot, thereby achieving fast kernel boot.

A computing device comprises a processor, a table walker, and a memory storing a segmented reverse map table in multiple non-contiguous portions of the memory. The table walker is configured to translate a virtual memory address specified by a memory access request to a physical memory address associated with the virtual memory address; and provide a requester associated with the memory access request with access to the associated physical memory address in response to an indication at the reverse map table that the requester is authorized to access the associated physical memory address.

A computer-implemented method for optimizing memory usage. A processor set classifies data stored in virtual memory into hot data and cold data based on frequency of access for the data stored in the virtual memory. The processor set segregates the hot data and the cold data into different memory regions in the virtual memory to generate hot memory regions comprising the hot data and cold memory regions comprising the cold data. The processor set maps the hot memory regions to large physical pages in memory pages of physical memory and the cold memory regions to small physical pages in the memory pages. The processor set disclaims data in the cold memory regions from the memory pages of physical memory to reduce memory space used in the physical memory.

A first hypervisor running on a first processor cluster is provided. During operation, the first hypervisor can determine a first set of processing nodes and a first memory unit of the first processor cluster in response to the booting up of a first Basic Input / Output System (BIOS) of the first processor cluster. The first hypervisor can discover a second hypervisor running on a second processor cluster comprising a second set of processing nodes and a second memory unit. The first hypervisor can operate, with the second hypervisor, a distributed system comprising the first and second sets of processing nodes and the first and second memory units. The first hypervisor can then operate, with the second hypervisor, a global virtual machine on the distributed system. The virtual memory space of the global virtual machine can be mapped to respective memory spaces of the first and second processor clusters.

A system for hardware partitioning of a cloud server includes one or more processor cores. The first processor core executes instructions to partition at least a portion of the one or more processor cores into one or more partitions. The system includes one or more distributed virtual memory (DVM) interposers, each DVM interposer including a respective partition identifier that identifies a partition. Each DVM interposer performs a prevention action in response to receiving a DVM message that includes a partition identifier that is different from the partition identifier of the DVM interposer. The system includes one or more interrupt interposers. Each interrupt interposer is associated with a processor core of the one or more processor cores. Each interrupt interposer prevents a first interrupt originating from the associated processor core from being provided to processor cores outside the partition of the associated processor core.

To provide a system and a method for a hardware partition of a cloud server.SOLUTION: The system includes one or more processor cores including a managed processor core that executes instructions to divide at least a portion of the one or more processor cores into one or more partitions, and at least one distributed virtual memory (DVM) hub that obtains DVM messages from the processor cores, determines one or more recipient processor cores of the DVM messages, and provides the DVM messages to the determined recipient processor cores. The system also includes one or more interrupt interposers that are each associated with a processor core and that prevent interrupts originating from the associated processor core from being provided to processor cores that are outside of the partition of the associated processor core.SELECTED DRAWING: Figure 1

The present invention relates to a system for protecting against cyber-attacks on a host machine, comprising: (a) at least one MTS, connected to the bus lines, of said memory device(s), of said host, for sampling the electrical signals, intended for said memory device(s); (b) at least one MRMU, connected to said MTS(s), for receiving said sampled signals from said MTS(s) and translating said sampled signals for reconstructing the physical and virtual memory content of said host, into at least one MLM of said host machine; (c) a memory, connected to said MRMU, for storing said at least one MLM; and (d) an IPU, connected to said MRMU(s), and connected to said memory, for detecting, identifying, and analyzing at least one EOI within the reconstructed host memory content, on said memory, and for classifying said at least one EOI as legitimate or malicious.

The present application relates to the technical field of taint data propagation analysis, and provides a taint label processing method, device, equipment and medium, the method: obtaining a first-level page table first address corresponding to a program to be analyzed, obtaining a virtual memory address, obtaining page table entry values of different-level page tables according to the virtual memory address, using the multi-level page table for indexing according to the first-level page table first address and the page table entry values of different-level page tables, and obtaining a taint label corresponding to the virtual memory address in a taint label memory space.The present application limits the memory range of the program and configures the multi-level page table, when searching for the taint label, uses the multi-level page table for indexing according to the first-level page table first address and the page table entry values of different-level page tables, and obtains the taint label corresponding to the virtual memory address in the memory range in the taint label memory space, so as to achieve the purposes of effectively reducing the space occupation and quickly indexing.

The application provides a method, device, DPU chip, AI cluster acceleration card and cloud computing host for optimizing DPU side memory, comprising: sending a memory optimization request to a host; receiving a response notification from the host; constructing a virtual memory exchange device according to the response notification; when a memory low water line threshold is triggered, exchanging out DPU side memory into the virtual memory exchange device; when memory in the virtual memory exchange device needs to be accessed, exchanging in corresponding memory in the successfully reserved host side memory address range into the DPU side memory. According to the technical scheme of the application, the memory resource dynamic optimization and expansion of the DPU can be realized at low cost, the disk IO delay is reduced, and the overall system performance is improved.

Discloses are systems and method for detecting malicious code in a file. The system receives at least one file. The system analyzes the at least one file, during which offsets from a beginning of the at least one file are detected for data that is similar to code that assembles strings in memory from data included in machine instructions. The system performs emulation of the machine instructions included in the code according to the detected offsets, further comprising: checking an effect of each respective machine instruction of the machine instructions on a control flow, and extracting strings from virtual memory if the respective machine instruction affects the control flow. The system analyzes extracted strings, during which malicious code is detected using malicious code detection rules.