109 results about "Virtual memory" patented technology

Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.

There is provided a method, system and non-transitory storage medium for serving a large language model (LLM) engine by allocating memory on demand. A virtual memory space with virtual pages is initialized for a tensor. A first request with first input tokens is received, added to the tensor by being allocated to first virtual pages and mapped to first page frames in physical memory. The tensor is provided to the LLM engine for processing. A second request with second input tokens is received, and a first output token is received from the LLM engine. The first output token is added to the tensor by being allocated to a second virtual page contiguous to the first virtual pages and mapped to a second page frame. The second input tokens are allocated to second virtual pages and mapped to second page frames in physical memory. The tensor is provided for further processing.

The invention discloses an automatic AI memory leak intelligent positioning and root cause traceability analysis system, and relates to the technical field of memory leak intelligent positioning and root cause traceability analysis. The automatic AI memory leak intelligent positioning and root cause traceability analysis method includes the following steps: S1, data acquisition: performing index acquisition through a multi-dimensional data acquisition unit, and supporting physical memory and virtual memory utilization rate, heap and stack memory allocation and log release, object creation, track destruction and thread execution state index acquisition; according to the automatic AI memory leak intelligent positioning and root cause tracing analysis system, the leak position is positioned, the root cause can be analyzed from dimensions such as code defects, improper configuration and resource competition, the leak recurrence rate is reduced, normal memory fluctuation and a real leak mode are effectively distinguished through sliding window time sequence analysis, exception screening and feature engineering optimization, and the reliability of the system is improved. False alarms are reduced, and the accuracy of abnormal event identification is improved.

The present disclosure relates to a data processing method, device, system, computer device and storage medium. The method comprises: in the case of listening to an agent process updating a data set file corresponding to a service process, performing in-memory mapping on the updated target data set file to obtain a virtual memory address of the target data set file; releasing data in an original data set file in a physical memory of the service process; and writing data in the target data set file into the physical memory according to the virtual memory address of the target data set file. The embodiment of the present disclosure can reduce memory consumption.

Provided is a computer agent and method to detect and prevent ransomware attacks early without losing customer data, without polluting the customer's file system or consuming any space on a storage device. The computer agent installs a kernel mode layered file system driver which is attached to encryption level group of a filter manager. With this layered file system filter driver design, it creates virtual canary files in directories which appear like normal files to any user or application though these files will not reside on disk. These virtual canary files are spread as baits across the file system to detect and prevent any malicious attack from any process or application. So that the Virtual Canary Files do not consume a large amount of memory, internal structures representing Virtual Canary Files are placed in virtual memory, but actual contents of the Virtual Canary Files do not reside in virtual memory. Other embodiments disclosed.

The embodiment of the invention provides a memory control method, computing equipment, a storage medium and a program product. The method comprises the steps of obtaining a heap expansion request for a heap memory of an application program; in response to the heap expansion request, allocating a virtual memory page with a large page size for the application program based on the heap memory; wherein the initial address of the virtual memory page is aligned according to the size of the large page; the virtual memory page is used for mapping to a physical memory page corresponding to the large page size, and generating a page table item according to a mapping result. According to the technical scheme provided by the embodiment of the invention, the virtual memory page with the large page size is allocated, and the initial address of the virtual memory page is aligned according to the large page size, so that the system performance is effectively improved, and the memory access efficiency is improved.

Disclosed in the embodiments of the present application are a root file system loading method and a related apparatus. In the method, a part of a virtual memory is simulated as a random access memory disk (RAMDISK) mechanism used by a block device. First, a read-only memory file system (ROMFS) mirror image file on an initial physical address is acquired; and then, a virtual address corresponding to the initial physical address of the ROMFS mirror image file is directly used as the starting address of the block device, such that the copy operation of copying the ROMFS mirror image file to the block device is executed on the initial physical address, thereby formatting the block device. Then, a kernel can be booted by means of mounting the ROMFS mirror image file in the block device as a root file system. By using the ROMFS image file as a root file system and reducing copy operations during a boot process, the kernel boot time is shortened in read‑only application scenarios requiring fast boot, thereby achieving fast kernel boot.

A first hypervisor running on a first processor cluster is provided. During operation, the first hypervisor can determine a first set of processing nodes and a first memory unit of the first processor cluster in response to the booting up of a first Basic Input / Output System (BIOS) of the first processor cluster. The first hypervisor can discover a second hypervisor running on a second processor cluster comprising a second set of processing nodes and a second memory unit. The first hypervisor can operate, with the second hypervisor, a distributed system comprising the first and second sets of processing nodes and the first and second memory units. The first hypervisor can then operate, with the second hypervisor, a global virtual machine on the distributed system. The virtual memory space of the global virtual machine can be mapped to respective memory spaces of the first and second processor clusters.

To provide a system and a method for a hardware partition of a cloud server.SOLUTION: The system includes one or more processor cores including a managed processor core that executes instructions to divide at least a portion of the one or more processor cores into one or more partitions, and at least one distributed virtual memory (DVM) hub that obtains DVM messages from the processor cores, determines one or more recipient processor cores of the DVM messages, and provides the DVM messages to the determined recipient processor cores. The system also includes one or more interrupt interposers that are each associated with a processor core and that prevent interrupts originating from the associated processor core from being provided to processor cores that are outside of the partition of the associated processor core.SELECTED DRAWING: Figure 1

The present invention relates to a system for protecting against cyber-attacks on a host machine, comprising: (a) at least one MTS, connected to the bus lines, of said memory device(s), of said host, for sampling the electrical signals, intended for said memory device(s); (b) at least one MRMU, connected to said MTS(s), for receiving said sampled signals from said MTS(s) and translating said sampled signals for reconstructing the physical and virtual memory content of said host, into at least one MLM of said host machine; (c) a memory, connected to said MRMU, for storing said at least one MLM; and (d) an IPU, connected to said MRMU(s), and connected to said memory, for detecting, identifying, and analyzing at least one EOI within the reconstructed host memory content, on said memory, and for classifying said at least one EOI as legitimate or malicious.

The present application relates to the technical field of taint data propagation analysis, and provides a taint label processing method, device, equipment and medium, the method: obtaining a first-level page table first address corresponding to a program to be analyzed, obtaining a virtual memory address, obtaining page table entry values of different-level page tables according to the virtual memory address, using the multi-level page table for indexing according to the first-level page table first address and the page table entry values of different-level page tables, and obtaining a taint label corresponding to the virtual memory address in a taint label memory space.The present application limits the memory range of the program and configures the multi-level page table, when searching for the taint label, uses the multi-level page table for indexing according to the first-level page table first address and the page table entry values of different-level page tables, and obtains the taint label corresponding to the virtual memory address in the memory range in the taint label memory space, so as to achieve the purposes of effectively reducing the space occupation and quickly indexing.

The application provides a method, device, DPU chip, AI cluster acceleration card and cloud computing host for optimizing DPU side memory, comprising: sending a memory optimization request to a host; receiving a response notification from the host; constructing a virtual memory exchange device according to the response notification; when a memory low water line threshold is triggered, exchanging out DPU side memory into the virtual memory exchange device; when memory in the virtual memory exchange device needs to be accessed, exchanging in corresponding memory in the successfully reserved host side memory address range into the DPU side memory. According to the technical scheme of the application, the memory resource dynamic optimization and expansion of the DPU can be realized at low cost, the disk IO delay is reduced, and the overall system performance is improved.

Discloses are systems and method for detecting malicious code in a file. The system receives at least one file. The system analyzes the at least one file, during which offsets from a beginning of the at least one file are detected for data that is similar to code that assembles strings in memory from data included in machine instructions. The system performs emulation of the machine instructions included in the code according to the detected offsets, further comprising: checking an effect of each respective machine instruction of the machine instructions on a control flow, and extracting strings from virtual memory if the respective machine instruction affects the control flow. The system analyzes extracted strings, during which malicious code is detected using malicious code detection rules.

The invention relates to a method and a device for managing LLC (Logical Link Control) resources. There is provided a method for managing LLC resources, comprising: receiving a memory mapping request from user mode software, the memory mapping request requesting to map a virtual memory address of the user mode software to a physical address of an LLC SRAM block; in response to the memory mapping request, allocating at least one LLC SRAM block from an LLC SRAM resource pool, where the LLC SRAM resource pool is a storage resource dynamically configured in an SRAM mode by configuring a first control state register in the LLC; establishing mapping from a virtual memory address of the user mode software to a physical address of the allocated LLC SRAM block, and configuring a page table item attribute of the mapping as a non-cache mode; and enabling the allocated LLC SRAM block by a second control state register.

During a post-copy migration process, latency and memory overrides can be avoided by implementing some techniques described herein. For example, during a post-copy migration process involving migrating a virtual machine from a source computing device to the destination computing device, a hypervisor can start the virtual machine on the destination computing device. After starting the virtual machine, the hypervisor can receive a message associated with storing data from a passthrough device to a virtual memory segment of the virtual machine on the destination computing device. Based on receiving the message, the hypervisor can prevent the virtual memory segment from being migrated from the source computing device to the destination computing device. This can prevent the data from the passthrough device from being overridden.

A fair and efficient guest to hypervisor virtual machine socket protocol may be provided by: in response to a host determining to reject a message received from a guest that was previously accepted for processing by the host, transmitting a rejection to the guest; in response to receiving, at the guest, the rejection, adding the message to a processing request queue on the guest; in response to determining that resources to handle the message have become available for the guest, transmitting an indication to the guest that the host is able to reaccept the message; in response to receiving, at the guest, the indication, retransmitting the message to the host according to the processing request queue; and in response to receiving the message from the guest a second time, accepting the message in an execution queue in a virtual memory of the host.

The invention discloses a memory training interaction device based on virtual reality and a virtual object recommendation method in memory training interaction, and the device comprises a database which is configured to store a plurality of types of memory objects for a user to select, and each type of memory object comprises a plurality of memory units; a virtual object having a certain memory association with the memory unit and an association mapping set between the memory unit and the virtual object are also stored; the memory object association module is used for recommending a plurality of virtual objects having different association strengths with the memory unit to the user; the scene construction module is configured to recommend a plurality of training modes and a plurality of virtual memory scenes to the user, and generate a corresponding VR virtual scene according to the virtual memory scene and the training mode selected by the user, so that the user interacts with a generated virtual object in the VR virtual scene; and the interaction module is configured to control the virtual object to complete a corresponding interaction action based on user operation. Through multi-mode training, personalized scene and interactive design, memory training efficiency and user experience are improved.

The invention discloses a software protection method based on a virtual machine encryption mode and a storage medium, and the method comprises the steps: encrypting to-be-protected data through a key to obtain encrypted data, the to-be-protected data comprising an executable code, a configuration file and a resource file of to-be-protected software; constructing a virtual machine execution environment in the equipment memory, wherein the virtual machine execution environment comprises a virtual processor, a virtual memory space and a virtual register; loading the encrypted data to a virtual memory space, and configuring a virtual processor; after the protected software is started, performing anti-debugging monitoring, and if a debugging behavior is monitored, executing an anti-debugging operation; during the running period of the to-be-protected software, the MAC address of the equipment is obtained regularly, and the legality of the equipment is verified; and when a preset self-destruction triggering condition is met, executing a self-destruction operation. According to the method, various security threats can be effectively resisted, and software code and data security is protected.

Approaches are described for a decentralized computing platform that enables dynamic execution of distributed services through a hybrid on-chain and off-chain architecture. The platform consists of a network of nodes, each running a virtual machine to host and execute service instances. A sequencer component records, sequences, and notarizes function calls to maintain a consistent service-level state across the network. Computation takes place off-chain on nodes that participate dynamically in specific services based on resource availability. A persistent virtual memory structure manages both service-level and instance-level state. The service-level state is synchronized across nodes participating in the same service, while the instance-level state is isolated to individual nodes for independent operations. The memory system is non-volatile, retaining state across function calls and enabling direct execution from memory. A universal procedure call (UPC) framework facilitates decentralized communication through multicast-enabled operations with customizable fault tolerance and supports applications from finance to high-performance computing.

A canary update method according to some embodiments is disclosed. The canary update method includes executing, by a processor configured to process tasks including the canary, computer program instructions to perform operations including extracting, by a processor, a first value from an array including N values, setting the canary to the first value, determining that the canary is updated based on a canary flag value of a first task, extracting, when determined that the canary is updated, a second value from the array, and updating the canary of the first task to the second value. The processor is configured to access a memory through a mapping circuit, and the mapping circuit includes mapping information between a physical memory region in the memory corresponding to the first task and a virtual memory region associated with the mapping circuit.

Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.

The embodiment of the invention provides a memory sharing method and device, electronic equipment, a storage medium and a product, and relates to the technical field of memory management. Allocating a virtual memory area of a corresponding first process to a shared virtual memory space bound with the target shared file; in response to an access request of the first process for the target virtual memory area, determining a target shared virtual memory space corresponding to the target virtual memory area; under the condition that the access request is not sent by the first process for the target virtual memory area for the first time, if a page table entry corresponding to a corresponding target shared virtual memory space exists in a target host address space to which the target shared virtual memory space belongs, responding to the access request based on the page table entry; and otherwise, allocating a physical page to the target shared virtual memory space, and generating a corresponding page table entry in the target host address space. The memory consumption can be reduced.

Efficient data movement in neural network accelerators operating within virtualized memory systems is challenged by high address translation latency and unique data access patterns. To address this challenge, address translation prefetch (ATP) mechanisms can be implemented to proactively translate virtual memory addresses before data movement. ATP can be performed in advance of any data movement or concurrently with data movement while being throttled by page transition in the data movement request stream. The ATP mechanism can enforce quotas on outstanding ATP requests, independently for read and write streams, to preserve resources for other processes running on the neural network accelerator. In dealing with competing ATP requests, the mechanism can employ weighted arbitration to balance between different types of ATP requests, utilizing a programmable ratio. The ATP mechanisms enable scalable, high-throughput neural network inference in virtualized environments, addressing data movement bottlenecks in neural network accelerator deployments.

A computing system including two or more processing units shares virtual memory for a program between the two or more processing units. Each of the processing units may include memory management circuitry to manage a respective page table corresponding to the virtual memory. A first portion of the addresses of the virtual address space of the program are mapped to addresses of physical memory associated with a first one of the two or more processing units, while a second portion of the addresses of the virtual address space are mapped to addresses in physical memory associated with a second one of the two or more processing units.

Techniques for managing the memory of computing devices that host multiple VMs by selecting optimally sized pages of virtual memory for programs running in the VMs. Virtual memory has traditionally been divided into pages of a single size (e.g., small, large, or huge) that are then offered to programs running in VMs. These page sizes have different benefits and drawbacks that must be considered when selecting the best page size for virtual memory. For example, small pages increase memory sharing between the VMs, but also result in an execution slowdown. Conversely, large pages improve execution performance by reducing latency in address translations, but limit memory sharing. This disclosure describes using small pages for sharable memory, and using large pages for private memory that cannot be shared. This provides the high performance needed for certain applications by using large pages, but still allows for increased memory sharing using small pages.

A memory management method and computing device, the method relating to a heap memory manager, the method comprising: obtaining a memory allocation request sent by a target application, the memory allocation request at least comprising a first identifier, the first identifier corresponding to a target instance waiting for memory allocation; the first identifier is matched with a plurality of current active identifiers, each active identifier corresponds to a plurality of allocated virtual memory pages, and the virtual memory pages corresponding to the plurality of active identifiers are different from one another; and if the active identifier matched with the first identifier does not exist, obtaining a newly added virtual memory page, transmitting a memory address in the newly added virtual memory page to the target application, and realizing memory space isolation of each instance in the application program on the level of the virtual memory page. The problem of batch instance crash caused by write overflow of a single instance can be avoided.

A system comprises one or more processor cores, including a management processor core that executes instructions to partition at least a portion of the one or more processor cores into one or more partitions. The system includes at least one distributed virtual memory (DVM) hub that obtains a first DVM message from a processor core; determines, based on a processor core identifier of the DVM message, one or more recipient processor cores for the first DVM message; and provides the first DVM message to the one or more recipient processor cores. The system includes one or more interrupt interposers that are each associated with a processor core and prevent an interrupt originating from the associated processor core from being provided to a processor core that is outside the partition of the associated processor core.

This invention belongs to the field of component attribute information management technology, specifically providing a method, apparatus, device, and medium for modifying non-integer attribute information of components. The method includes the following steps: identifying the component and attribute information to be modified; generating a configuration file for attribute information by searching for the target component's information; storing the non-integer attribute information into different sets according to attribute type; during the generation of a binary file based on the configuration file, searching for the corresponding attribute ID in the corresponding set according to the attribute category; checking the validity of the attribute values ​​to be modified in the configuration file based on the range of attribute values ​​in the set; generating the binary file when all categories of attribute values ​​are valid; refreshing the data in the binary file to the attribute database to complete the overwriting of the target component's attribute values; restarting the machine and loading the data in the attribute database into virtual memory to make the configuration effective. This method allows modification of attribute values ​​without compiling Pnor, improving efficiency.

The invention discloses a memory allocation method and system, electronic equipment and a storage medium. The method comprises the steps that the capacity of a to-be-allocated memory is determined, the to-be-allocated memory is used for storing compressed data, and the compressed data is used for representing a compression result of data exchanged between a physical memory and a virtual memory; target metadata matched with the capacity is searched in a structural body, and the structural body at least comprises metadata of different memories in a memory pool; based on the target metadata, position information of the to-be-allocated memory is determined, and the position information is used for representing the position of the to-be-allocated memory in the memory pool corresponding to the structural body; and based on the position information, allocating a memory corresponding to the compressed data from a memory pool. The technical problem that the memory cannot be effectively allocated is solved.

The embodiments of the present application belong to the technical field of computers. Disclosed are a hot page recognition method and a related device, which are used for improving the efficiency of hot page recognition. The method comprises: acquiring an access frequency corresponding to each memory block in a mapping table, the mapping table comprising a plurality of groups, each group comprising a plurality of memory blocks, the access frequency corresponding to a first memory block representing the number of times of, in response to a first memory access request, using the first memory block to map a first memory address to a physical memory region within a preset time period, a preset mapping relationship comprising a mapping relationship between a first address segment among memory access addresses and the groups in the mapping table, and the first address segment comprising an address segment having the highest data change frequency among memory access addresses indicated by a plurality of historical memory access requests; and, on the basis of the memory block in the mapping table whose access frequency meets a preset condition, determining a hot page among virtual memory pages, different memory blocks in the mapping table corresponding to different virtual memory pages, and the first memory access request being used for applying for a virtual memory page corresponding to the first memory access address.