397 results about "Virtual memory" patented technology

The invention provides a complex scene-oriented AI large model lightweight deployment method, and relates to the technical field of edge computing, and the method comprises the steps: carrying out the structured pruning of a pre-trained Transform network based on the attention head importance score, carrying out the dynamic sparsification of the activation state of a feedforward network according to the input tensor entropy value, employing the dynamic mixing precision quantization, and carrying out the reconstruction of an AI large model. Obtaining network parameters after pruning quantization; deploying the pruned and quantized network parameters to an edge computing device, distributing a feature extraction operator to a neural network processor through a heterogeneous computing scheduler, and unloading a classification operator to a multi-core central processing unit; and managing an on-chip memory in combination with a virtual memory paging mechanism, realizing zero-copy data transmission by utilizing a direct memory access controller, and outputting a reasoning result tensor. According to the method, efficient and reliable operation of the large model at the resource-constrained edge node is realized.

A key-value cache management system processes inference requests of a generative model. An inference request requests a starting virtual memory address and a number of layers in the generative model. In response to receiving an inference request, contiguous virtual memory space is reserved for the key-value cache in accordance with the inference request by assigning the starting virtual memory address in the key-value cache and calculating memory pointers for each layer in the model and each block so that the one or more blocks are written sequentially. The generated memory pointers are outputted to the generative model so that each self-attention layer writes computed key-value pairs at physical addresses in the key-value cache specified by the memory pointers.

The invention discloses a memory allocation method and related equipment, which are applied to electronic equipment, and the method comprises the following steps: receiving a first memory request of an application program, the first memory request comprising a target memory space value; determining a virtual address matched with the target memory space value from a virtual memory space, and determining a target virtual address to be mapped from the virtual address; a to-be-mapped target physical address is determined from a physical memory space, whether the target virtual address and the size and byte boundary of the target physical address meet a first condition is judged, and the first condition comprises the alignment type of the byte boundary; if the first condition is met, determining an attribute parameter matched with the first condition; and creating a page table matched with the attribute parameter, and establishing a mapping relationship between the target virtual address and the target physical address. By adopting the embodiment of the invention, the memory access efficiency can be improved.

The present application belongs to the technical field of data processing and relates to a network message processing method and apparatus, and a computer device and a storage medium. The method comprises: on the basis of a received target network message, acquiring a target memory block from a pre-constructed shared memory pool, so as to generate a message memory; on the basis of a network-interface-card driver, performing first identification processing on the target network message, so as to obtain a target network message descriptor; on the basis of the target network message descriptor, performing second identification processing on the message memory, so as to obtain a first socket buffer; and performing parsing processing on the first socket buffer by means of a network protocol stack, and on the basis of a parsing processing result, reading network message data from a virtual memory corresponding to the message memory, so as to complete the processing of the network message. In the present application, on the basis of a constructed shared memory pool, zero-copy network packet reception can be realized during network message processing, thereby avoiding performance loss caused by the memory copy of messages.

The invention discloses a data processing method, device and equipment and a readable storage medium, and the method comprises the steps: running a business application in a virtual machine, and obtaining a business application instruction set; the instruction type of the business application instruction set is an instruction type supported by a processor of the host machine; writing a service application instruction set in a virtual memory of the virtual machine into a shared physical memory in a virtual interaction device corresponding to the virtual machine, and generating writing notification information used for representing a writing completion state of the service application instruction set; the shared physical memory is a physical memory used for being jointly read and written by the virtual machine and the management program in the host machine; and in the management program, obtaining write-in notification information, obtaining the business application instruction set in the shared physical memory through the write-in notification information, and executing the business application instruction set through a processor of the host machine to obtain instruction execution data corresponding to the business application instruction set. By adopting the method and the device, the performance of running the business application by the virtual machine in the host machine can be improved.

Systems and methods herein are for at least one circuit to perform at least one process of different processes that may be associated with one or more applications, where the process may use one part of a virtual memory based on different requests by the different processes, where the virtual memory may include parts of equal allocations based on a maximum of different memory sizes in specifications associated with the different processes, where the one part of the virtual memory may be in a mapping with respect to one part of a physical memory of different allocated sizes, and where a translation for the mapping can occur using a start address and the maximum of the different memory sizes.

The invention relates to a memory management method and device applied to a server-free data center, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in response to a virtual memory application instruction, performing virtual memory allocation in a local computing resource pool to obtain a virtual address space; in response to the virtual address access instruction, acquiring cache information of the computing resource pool, and triggering missing page interruption under the condition that data corresponding to the virtual address is not hit in the cache information; the cache information comprises locally cached cache data and page table information; acquiring physical memory resources in a memory resource pool according to the virtual address and the page table information under the condition of triggering missing page interruption of the anonymous page; and updating the page table information and the cache information according to the physical memory resources. By adopting the method, the processing delay of the data center can be reduced while the decoupled memory management logic is used for improving the resource utilization rate.

An information handling system includes a hardware processor, a memory device operatively coupled to a serial peripheral interface (SPI) chip and the hardware processor. The SPI chip interfaces the hardware processor executing plural stages of boot modules during a boot process of the information handling system with allocated, reserved portions of the memory device for each stage of boot module executed in pre-boot, boot, and runtime via a virtual memory interface generated by execution of an original equipment manufacturer (OEM)-defined agnostic memory allocation module. The hardware processor executes the OEM defined agnostic memory allocation firmware to redefine the virtual memory interface for each allocated reserved portion of the memory device at each of the plural stages of the boot modules that are executed from pre-boot, through boot, and to runtime to provide adjustments to allocated, reserved portions of memory for later stages of executed plural stages of the boot modules.

The invention provides a hot upgrade method for a virtual machine monitor (VMM), which comprises the following steps of: pausing the operation of a virtual machine, storing state information of an original VMM, and reserving a kernel-based virtual machine KVM extension page table and a memory management structure of the original VMM; reserving a page global directory and a virtual memory area VMA corresponding to a virtual machine RAM area according to the memory management structure, and refreshing a process address space described by the memory management structure into a new VMM execution program so as to complete switching of the original VMM into the new VMM; and executing the new VMM, recovering the state information to the new VMM, and inheriting the KVM extension page table by the new VMM to recover the operation of the virtual machine. The invention further provides computer equipment, a computer readable medium and a computer program product.

The invention discloses a data processing method and a related device, and the method comprises the steps: firstly obtaining a target instruction of a virtual machine, and enabling the target instruction to be used for controlling the virtual machine; and then according to the target virtual memory address corresponding to the target instruction, an encryption key corresponding to the target instruction is determined, and different virtual memory addresses correspond to different encryption keys. And according to the encryption key, performing instruction coding on the target instruction through a coding algorithm to obtain a coding result, and storing the coding result as the target instruction in the target virtual memory address. Finally, in the running process of the virtual machine, when a calling request for the target instruction is obtained, the coding result is read from the target virtual memory address, instruction decoding is conducted on the coding result through a decoding algorithm corresponding to the coding algorithm according to the encryption key, and the target instruction is obtained. The encryption key is generated based on the storage address of the instruction, and the encryption key is used for instruction coding to realize the specificity of a coding result, so that the security of the virtual machine is improved.

Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.

The invention discloses a memory access method and device, a storage medium and a program product, and relates to the technical field of memory access, comprising: monitoring memory access information of a target memory; the memory access information comprises a missing page address sequence during memory access, an address distribution characteristic when an address conversion failure event occurs in an address conversion lookaside buffer, a cross-node access event and a virtual memory access frequency; determining corresponding target feature information; the target feature information comprises spatial locality, thermal density, access dispersion and unbalance degree data; and determining a current memory access mode based on the target feature information, and determining a target access strategy from preset memory access strategies configured with different memory page table prefetching rules to access the memory. The memory access feature information is quantified through the memory access information, the corresponding memory access mode is determined, and the corresponding memory page table prefetching rule is executed, so that the traversal delay of the multi-level page table can be reduced, and the memory access performance is improved by fully utilizing the memory bandwidth.

The invention relates to the technical field of virtual machines, and provides a virtual machine QEMU program hot upgrade method, system and device, and the method comprises the steps: starting a source virtual machine to generate an old version QEMU process, and distributing a corresponding virtual memory and an anonymous memory file descriptor for the memory of the source virtual machine through the old version QEMU process; configuring starting parameters of a target virtual machine, starting the target virtual machine on the same host by using the new-version QEMU file and the configured starting parameters of the target virtual machine, and generating a new-version QEMU process; the old version QEMU process establishes connection with the target virtual machine according to the starting parameters of the target virtual machine, and executes initialization of rear-end equipment of the target virtual machine and updating of state information of the virtual machine; and after the initialization of the back-end equipment of the target virtual machine and the updating of the state information of the virtual machine, running the target virtual machine and closing the source virtual machine. According to the method, the QEMU upgrading efficiency can be improved, system and network resources are saved, the success rate of QEMU upgrading is remarkably improved, and the influence of hot upgrading on services is reduced.

The invention discloses a server system based on a public cloud technology and an access method thereof, and belongs to the technical field of cloud services. The server system comprises a server and an external device inserted in the server. A virtual machine manager in the server is used for providing a virtual external device and a virtual memory for a virtual machine in the server, the virtual external device is obtained through device simulation based on the external device, and the virtual memory is obtained through device simulation based on a memory configured for the external device. The virtual device driver of the virtual external device is used for sending an access request carrying the target GPA to the external device when the virtual external device accesses the target GPA of the virtual memory. And the external device is used for obtaining a target host physical address corresponding to the target client physical address based on the access request, obtaining target data recorded by the target host physical address, and sending the target data to the virtual device driver. According to the invention, the address translation performance of the server system is effectively improved.

The invention discloses a data transmission system, method and device, a storage medium and a computer program product, and relates to the technical field of communication. The data transmission system comprises a virtual machine, a virtual RDMA device and a host, wherein the virtual RDMA device runs between the virtual machine and the host. Wherein the virtual machine is used for running an application; the virtual RDMA equipment is used for registering a virtual memory and a virtual RDMA connection corresponding to the virtual machine, configuring a memory mapping relation between the virtual memory and a physical memory and a connection mapping relation between the virtual RDMA connection and the physical RDMA connection, and issuing the memory mapping relation and the connection mapping relation to the host; and the host is used for transmitting the RDMA data of the application according to the memory mapping relation and the connection mapping relation. Decoupling of the front-end virtual machine and the rear-end host is realized, the expansibility of connection is improved, a data transmission system is more modularized and is easy to manage, and the overhead of the host is reduced.

The invention relates to a progressive memory delay monitoring and diagnosis method oriented to a virtual memory subsystem. The method comprises the following steps: mounting a BPF program to a plurality of key event points on a kernel; when the key event point is triggered, acquiring state information of a corresponding event; packaging the state information into an event, and writing the event into a perf ring buffer associated with the outputmap; and the user mode program asynchronously reads the packaged event from the perf ring buffer, performs classification and aggregation according to the process and the event type, generates a delay terminal log and a histogram, and outputs a diagnosis result. Through systematic architecture design, the state keeping capability and the kernel context access capability of the eBPF are combined with an event model of a virtual memory subsystem, and a set of closed-loop monitoring system oriented to a diagnosis target is constructed. High-precision and high-reliability memory operation delay measurement is realized.

A file system in a user space partition of virtual memory may be mounted by a computing device that runs a virtual machine which includes a set of storage disks. The file system in user space may then expose one or more virtual files associated with one or more storage disks that correspond to one or more loop devices configured to map files of the virtual machine to the one or more virtual files. The computing device may then receive a request to read a data block stored at the virtual machine and may identify a file and corresponding virtual file that stores the requested data block based on a set of metadata provided by the loop devices. The computing device may then determine the location of the data block stored at the virtual machine, and may read the data block from the determined location.

The invention relates to micro-architecture and instruction set architecture extensions for efficient equal area victim buffering through translation lookaside buffer partitions. Techniques are described for victim buffering through translation lookaside buffer (TLB) partitions. In some examples, a system includes: a memory; execution circuitry to generate a memory access request to a virtual memory address of the memory; the first-stage translation lookaside buffer is used for storing mapping from a virtual address to a physical address; the victim translation lookaside buffer is used for storing virtual address-to-physical address mapping evicted from the first-stage translation lookaside buffer; a second-stage translation lookaside buffer; and cache coherency circuitry to search the first level translation lookaside buffer and the victim translation lookaside buffer for corresponding physical addresses mapped to virtual memory addresses for memory access requests, and to cache the victim translation lookaside buffer for misses in the first level translation lookaside buffer and the victim translation lookaside buffer. The second level translation lookaside buffer is searched for a corresponding physical address mapped to the virtual memory address for the memory access request for a hit in the victim translation lookaside buffer, and the corresponding physical address mapped to the virtual memory address for the memory access request is provided for a hit in the victim translation lookaside buffer.

Examples are disclosed herein relating to memory paging. In some examples, a host device is configured to communicate with an expansion device. The expansion device can include first and second memory, and a device virtual memory address (DVA) table. The expansion device can store data that can be requested by the host device. The first memory is a cache for the second memory based on a page presence table (PPT). The PPT can indicate a presence of second memory pages in the first memory cache. The DVA table can include information to locate data in the first memory based on a host physical memory address of a memory request. The device physical memory address can identify a memory location at which the data is stored. The data can be provided from the expansion device to the host device in response to the memory request based on the PPT.

Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

The embodiment of the invention provides a core dump file generation method and device, electronic equipment and a medium, and relates to the technical field of data processing.The method comprises the steps that in response to abnormity of a target process, a thread causing the abnormity of the target process is determined as a target thread from threads of the target process; retrieving a virtual memory address from a register occupied by the target thread and a stack memory area of the target thread; determining a target address of a data page which belongs to a heap memory area and has mapping from the retrieved virtual memory address; and generating a core dump file containing the data page mapped by the target address. By applying the scheme provided by the embodiment of the invention, the validity of the core dump file can be improved while the size of the core dump file is reduced.

The embodiment of the invention relates to the technical field of terminal security management, and discloses a kernel management method and device based on Hypervisor, and the method comprises the steps: obtaining abnormal event information of an operating system kernel of terminal equipment; determining virtual address field information corresponding to the abnormal event according to the abnormal event information; performing virtual memory measurement on the operating system kernel according to the virtual address field information to obtain a memory measurement result; and determining whether data in the kernel of the operating system is tampered or not according to the memory measurement result. According to the embodiment of the invention, effective detection and protection of data tampering in the kernel of the operating system are realized, and the overall security and system integrity of the terminal equipment are improved.

The invention provides a memory management method and device, which can reduce the occupancy rate of a physical memory and improve the data throughput of the memory by combining the same physical memory pages, thereby improving the memory bandwidth, improving the utilization rate of a computing unit and improving the data processing performance. And the method is suitable for most high-throughput hardware, does not depend on specific hardware, and is high in generalization capability. The method comprises the following steps: firstly, acquiring input data, storing the input data in a memory, and mapping a plurality of virtual memory pages to a plurality of physical memory pages storing the input data; then, at least two virtual memory pages in the multiple virtual memory pages are mapped to a first physical memory page, that is, the at least two virtual memory pages are mapped and shot to the same physical memory page, and the data, indicated by the at least two virtual memory pages, stored in the memory are the same; and when the at least two virtual memory pages are called, indicating to read data in the first physical memory page.

A host computer includes a memory storing a proxy VM, and a host CPU. The proxy VM emulates target hardware having an incomplete design. The proxy VM includes a virtual processor for emulating a target processor. The proxy VM includes an emulated memory coupled to the virtual processor over a virtual memory bus. The emulated memory includes at least one portion storing the target code. The host CPU is configured to execute the proxy VM to emulate the target hardware. The proxy VM, upon execution by the host CPU, is configured to execute, by the virtual processor, the target code.

The invention provides a memory error simulation method and device based on a satellite-borne intelligent computing system, a medium and a simulator, and relates to the technical field of satellites. The method comprises the following steps: inputting a deep learning neural network engine into a deep learning reasoning program of a satellite-borne intelligent computing system; executing a deep learning reasoning program to read a process page table; based on the DRAM standard file, the DRAM mapping file and the address mapping relation, determining a memory active area of the deep learning neural network engine in the virtual memory model; performing construction processing on the memory active area, constructing an error injection space represented in a bitmap tree form, and determining an error information injection position in the error injection space according to particle flipping error model information and a Monte Carlo random algorithm; and performing reverse translation processing on the physical address in the virtual memory model, and determining a target virtual address of the deep learning reasoning process. And a single-particle upset memory error and a multi-particle upset memory error caused by space radiation can be effectively simulated.

A computer system and associated methods are disclosed for mitigating side-channel attacks using memory page remapping. The computer system includes a main memory and a shared cache, the shared cache implementing cache set associativity determined by a portion of memory addresses of the main memory. Multiple physical memory pages are reserved for mapping to a virtual memory page, the physical memory pages differing in the respective portions of their memory addresses determining cache set associativity. Accesses to the virtual memory page result in a mapping of one of the reserved physical memory pages to the virtual memory page, with remapping events causing different ones of the physical memory pages to become mapped. This remapping results in varying cache set associativity of elements stored in the virtual memory page over time.

The invention discloses a verification method and a verification device for a chip design scheme, and electronic equipment. The method comprises the following steps: converting C code test excitation for chip design scheme verification into a binary file; writing an instruction in the binary file into the virtual memory interval, and writing a reset vector in the binary file into the virtual PC after the reset signal of the virtual PC is reset; reading a to-be-executed instruction in the virtual memory interval according to an address pointed by a reset vector in the virtual PC in each clock signal, executing a preset verification process on a DUT of a chip design scheme based on the to-be-executed instruction, and storing data returned from the DUT in a virtual register; and after all the instructions in the virtual memory interval are read, determining a verification result of the chip design scheme according to the data in the virtual register. According to the invention, the time for developing the test excitation can be reduced.

The invention discloses a protocol conversion system which comprises a first virtual machine, a second virtual machine and a virtual machine manager, a second virtual machine communication driver, a protocol conversion module and a front-end driver are arranged in the second virtual machine, and an application program is installed in the second virtual machine and sends data to the front-end driver during operation. The front-end driver communicates with the protocol conversion module, the protocol conversion module sends data to the second inter-virtual-machine communication driver, the second inter-virtual-machine communication driver transmits the processed data to the virtual machine manager, and the processed data is transmitted to the first virtual machine after being processed by the virtual machine manager. The first virtual machine processes the data and then sends the data to the physical peripheral in the virtual machine manager, and the protocol conversion module is added between the front-end driver and the virtual memory of the virtual machine, so that data communication can be realized without resetting or writing a driver program, and the system development difficulty and maintenance cost are reduced.

Examples of the present disclosure disclose a memory system and an operation method thereof and a storage device and an operation method thereof. The memory system includes a memory device and a memory controller, the kth memory blocks in memory planes in the memory device form one super memory block, super memory blocks form one virtual memory block, the mth physical pages coupled with the nth word lines in the memory planes from a same super memory block in the virtual memory block form one virtual physical page, the virtual physical pages from super memory blocks in a same virtual memory block form one strip; and the memory controller is configured to: receive memory data that needs to be written to a strip; generate parity check data of the strip according to the memory data; and send the memory data and the parity check data to the memory device.

The embodiment of the invention provides an address mapping method and device, electronic equipment and a readable storage medium, and the method comprises the steps: determining a target state tag corresponding to a physical address of a to-be-accessed client based on a state tag region in a virtual memory space of a host machine under the condition of binary translation of a source access instruction of the client; under the condition that the target state mark is matched with a target memory access operation indicated by the source memory access instruction, determining a host machine virtual mapping address corresponding to the to-be-accessed client physical address in a host machine virtual memory space based on a direct address mapping rule; and executing a target memory access operation on a target host machine physical address corresponding to the host machine virtual mapping address. Therefore, the host machine virtual mapping address corresponding to the physical address of the to-be-accessed client is directly determined through the direct address mapping rule, retrieval traversal is not needed, the overhead in the address mapping process can be reduced, the address conversion efficiency is improved, and meanwhile the number of times of interaction between the client and the host machine is reduced.