34 results about "Active memory" patented technology

The embodiment of the invention provides a memory information processing method of a large language model and a computer program product, and relates to the technical field of large language models. The method comprises the steps of obtaining interaction request information of a target object, extracting at least one piece of memory information needing to be memorized from the interaction request information based on a large language model, performing classification and importance evaluation on each piece of memory information to obtain category information and an importance score of each piece of memory information, and according to each piece of category information, determining the importance score of each piece of memory information. And determining the expiration duration of each piece of memory information, and storing each piece of memory information, the corresponding category information, the corresponding expiration duration and the corresponding importance score into an active memory pool of the target object. Context management can be carried out by using the memory information, and the context management accuracy of a large language model in a cross-session scene is remarkably improved.

A heterogeneous neural processing system includes a first processor configured to perform encoding and decoding operations of an autoencoder, and a second processor configured to perform neural network operations of a particular task, the operations having iterative processing. The processors perform compute tasks through synchronous data exchange to implement a generative AI model. The first processor processes a feature map divided into data rows, caches the data into active memory using row-based depth-first scheduling, and selects deeper operations in the network hierarchy when processing branch inputs, outputs, and residual connections. And H reuses boundary pixels between the cache storage space segments, so that convolution and element-level operation can be executed simultaneously. A neural network adjusts the device analysis model to identify layer dependencies, applies search space constraints, performs an iterative search to generate a fusion plan, and selects an optimal plan based on external memory access and execution delays.

The invention relates to the technical field of vehicle-mounted equipment, and discloses a high-vibration environment-oriented vehicle-mounted graphic server active anti-seismic system, which comprises the following steps of: firstly, acquiring a real-time vibration data flow of a vehicle-mounted graphic server, constructing an energy spectrum, and analyzing a resonance modal cluster to generate a damping regulation and control path; analyzing a dominant resonance mode, and identifying a critical oscillation node to calculate an inertia compensation coefficient; nonlinear filtering is carried out on the vibration spectrum based on the coefficient to obtain an anti-interference frequency band set, a servo driving instruction set is generated through topological mapping, a dynamic stiffness parameter is inquired, and a parameter distribution vector is marked; then, the vector is loaded to an active memory controller, an energy dissipation state is monitored, a gain threshold value combination is adaptively adjusted, and an anti-seismic robustness index is calculated; and finally, generating vibration characteristic lines, extracting steady-state, transient and chaotic components, and constructing a multi-cascade active anti-seismic mechanism. According to the method, the anti-seismic stability of vehicle-mounted graphic calculation can be guaranteed.

A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric material, the interconnect structures including a first set of interconnect structures electrically coupled to an active region of the transistor and a second set of interconnect structures electrically coupled to the doped well, an active memory cell electrically coupled to the active region of the transistor via the first set of interconnect structures; and a dummy memory cell electrically coupled to the doped well via the second set of conductive interconnect structures. The dummy memory cell and the second set of conductive interconnect structures may provide a low resistance pathway for plasma charge to flow to the doped well, thereby minimizing plasma induced damage to the transistor.

Systems and techniques are provided for secure computing. For instances, a process can include generating a master private key; generating a set of first dummy values; dividing the master private key into a first set of shares, wherein a sum of shares of the first set of shares equals a value of the master private key; initiating portions of an active memory bank with a sequence of integer modular additions, wherein the integer modular additions comprise: masking the first set of shares of the master private key; and adding the masked first set of shares of the master private key to portions of the active memory bank using a sequence of adds that adds and mixes the masked first set of shares of the master private key with dummy values.

A memory device includes a memory cell array including a plurality of word lines, a sense amplifier circuit, and a control logic circuit. The sense amplifier circuit is configured to amplify read data obtained from active memory cells of an active word line among the plurality of word lines, and provide write data from the memory controller to the active memory cells. The control logic circuit is configured to store inverted first data in memory cells of a first word line of the plurality of word lines by inverting the first data of the memory cells of the first word line stored in the sense amplifier circuit based on activation of the first word line.

This application is directed to managing memory operations in a memory system or device (e.g., a solid-state drive (SSD)). While implementing one or more write operations on one or more active memory dies, the memory device identifies a first read request for data stored on a first memory die. The first read request is waiting next in a queue of read requests. In accordance with a determination (1) that the first memory die is distinct from the one or more active memory dies and (2) that no sufficient power is available to implement the first read request concurrently with the one or more write operations, the memory device suspends the one or more write operations according to a suspension scheme and implements the first read operation on the first memory die.

A catheter for an ultrasound system can a marker disposed on the hub. The marker is optically or magnetically readable and, when read, identifies the catheter. A drive unit can include an optical or magnetic marker reader. Alternatively or additionally, a catheter may include an active memory arrangement that can be read by an appropriate reader on the drive unit.

This application provides a conversation processing method and apparatus. The method includes: acquiring current input information from a user during the current dialogue turn between a user and a large language model, and determining the current semantic vector corresponding to the current input information; acquiring memory units corresponding to at least one historical dialogue turn in the user's memory bank; determining the memory relevance between the current dialogue turn and each historical dialogue turn based on the current semantic vector and the memory units corresponding to each historical dialogue turn; sorting each historical dialogue turn by the memory relevance, and determining a preset number of active memory units related to the current dialogue turn in the sorting result; and injecting the preset number of active memory units into the large language model, so that the large language model combines the active memory units to perform the current dialogue turn.

The embodiment of the invention provides a data processing method, computing equipment and a storage medium, the data processing method is applied to a storage engine of a database, the storage engine adopts a line number to record a write-in version number and a deletion version number of each line, and the storage engine comprises an active memory table and an inactive memory table. Comprising the steps that deletion mark data are written into the active memory table, and the deletion mark data comprise the line number and the deletion version number of the deletion data, so that under the condition that a data query operation is responded, the data visibility of the corresponding line number is determined based on the deletion mark data; if the residual space of the active memory table is smaller than or equal to a preset space threshold value, converting the active memory table into an inactive memory table; in response to a disk falling operation, writing deletion mark data in the inactive memory table into persistent storage equipment; therefore, the problem that a large number of memory resources are occupied by deleting the marked data is avoided.

The embodiments of the present application provide a data processing method, a data query method, an apparatus, a device, a medium, and a product, which can be applied to the field of computer technology. The data processing method includes: in response to a write instruction or a disk flush instruction, writing the data to be stored indicated by the write instruction to an active memory table stored in the internal memory, or writing the data to be stored indicated by the disk flush instruction to a first file stored in the first-level external memory, the active memory table stores multiple data in the order of multiple keys, the data includes a key with a volume identifier, and the first file corresponding to the active memory table includes at least one data with each of the multiple volume identifiers; in response to a merge operation between the n-1th level external memory and the nth level external memory, obtaining target volume data with a target volume identifier among the multiple volume identifiers, and writing the target volume data with the target volume identifier to the nth file corresponding to the target volume identifier stored in the nth level external memory, where n is an integer greater than 1.

The present application discloses a hybrid expert network training method, a question-answering method, related equipment, and a program product. The present application fuses the second expert layer FC2 and the Unpermute operation layer in the hybrid expert network into a first fusion layer. During the forward propagation process, only the input of the first fusion layer and the probability Probs of each token corresponding to the expert need to be saved. During the backward propagation process, the input of the first fusion layer can be used to calculate both the gradient of the first fusion layer parameters and the gradient of Probs. There is no need to additionally save the output of FC2, thus reducing the amount of active memory required to be saved. Furthermore, the Permute operation and FC1 can be fused into a second fusion layer. During the forward propagation process, only the local input subsequence is saved, and the backward propagation gradient calculation process can obtain subsequences of inputs from other devices. Compared with the existing technology, there is no need to save the complete input sequence, further reducing the amount of memory required.

The embodiment of the invention provides a data processing method and device, a data query method and device, equipment, a medium and a product, and can be applied to the technical field of computers. The data processing method comprises the steps that in response to a write-in instruction or a disk refreshing instruction, to-be-stored data indicated by the write-in instruction is written into an active memory table stored in a memory, or to-be-stored data indicated by the disk refreshing instruction is written into a first file stored in a first-level external memory, and the active memory table stores multiple pieces of data according to the sequence of multiple keys, the data comprises a key with a volume identifier, and the first file corresponding to the active memory table comprises at least one piece of data with a plurality of volume identifiers; and in response to a merging operation between the (n-1) th-level external memory and the nth-level external memory, obtaining target volume data with a target volume identifier in the plurality of volume identifiers, and writing the target volume data with the target volume identifier into an nth file which is stored in the nth-level external memory and corresponds to the target volume identifier, n being an integer greater than 1.

A data processing method, a computing device and a storage medium. The data processing method is applied to a storage engine of a database, the storage engine using a row number to record a write-in version number and a deletion version number of each row, and the storage engine comprising an active memory table and an inactive memory table. The method comprises: writing deletion mark data into an active memory table, the deletion mark data comprising a row number and a deletion version number of deleted data, so as to determine, in the case of responding to a data query operation, data visibility of the corresponding row number on the basis of the deletion mark data; if the remaining space of the active memory table is less than or equal to a preset space threshold value, converting the active memory table into an inactive memory table; and in response to a disk flushing operation, writing the deletion mark data in the inactive memory table into a persistent storage device. Thus, the problem that deletion mark data occupies a large amount of memory resources is avoided.

In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and / or memory controllers in the system when the full complement of memory is not needed.

The invention relates to the technical field of memory management, and discloses a flash memory controller and a memory management method based on the flash memory controller, according to the flash memory controller, a memory management system and a basic control system are integrated in parallel, core memory processing operation can be completed on a hardware layer without depending on a host side, repeated data transmission is reduced, and the memory management efficiency is improved. Delay, power consumption and bandwidth occupation are remarkably reduced, and the low-delay requirement of end-side equipment is met; the memory management system has an active memory management capability, can realize efficient, intelligent and collaborative memory management, and adapts to end-side and enterprise-level multi-scene requirements; the multi-modal embedding engine realizes semantic analysis and vectorization of memory data, the vector management unit and the knowledge graph management unit are bidirectionally associated to form a hybrid index to mine memory association, the memory scheduling unit coordinates interaction between each module and a host side, deep integration of a storage medium and the host side is realized, and interaction continuity and personalized depth are improved; the memory management engine can integrate dispersed memory and clean useless data.

The invention relates to an active memory method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining multi-modal data in real time, and enabling the multi-modal data to be associated with a user in a vehicle and a scene where the vehicle is located; semantic analysis is carried out on the multi-modal data to obtain scene memory data, and the scene memory data carries a corresponding timestamp; and performing feature analysis on the scene memory data to obtain long-term memory data, so that the vehicle reasones and responds to the received interaction instruction based on the long-term memory data. Therefore, the multi-modal data is locally processed on the end side in real time, so that the privacy leakage risk caused by cloud transmission is avoided, and the timeliness of memory generation is improved; meanwhile, long-term memory is constructed based on scene and feature analysis, the ability of the vehicle to understand user preferences, scenes and interaction history is enhanced, more coherent, intelligent and personalized interaction experience can be realized, and the problems of privacy and timeliness contradiction and lack of active memory ability caused by cloud deployment in the prior art are effectively relieved.

In a method for updating operating system software on a control unit with a microcontroller connected to two memory partitions, the new operating software is written to an inactive memory partition during the update, while the previous operating software continues to run on an active memory partition. For synchronization purposes, the new operating software is only written from the inactive to the active memory partition after a test phase and within a flexible timeframe.

An apparatus includes vote aggregation circuitry configured to receive a first plurality of vote signals associated with an active memory state of a volatile memory and to generate a first vote aggregation signal based on the first plurality of vote signals. The vote aggregation circuitry is further configured to receive a second plurality of vote signals associated with a retention memory state of the volatile memory and to generate a second vote aggregation signal based on the second plurality of vote signals. The apparatus further includes memory bank control circuitry coupled to the vote aggregation circuitry and configured to provide a plurality of control signals to the volatile memory based on the first vote aggregation signal and the second vote aggregation signal. The plurality of control signals indicate, for each bank of a plurality of banks of the volatile memory, a mode associated with the bank.

Disclosed are a self-supervised learning method and a self-supervised learning apparatus. The self-supervised learning method performed by the self-supervised learning apparatus comprises the steps of: connecting a feature extractor with an active memory for replacing stored representative data; and outputting a representation by mapping input data to a latent space by using the feature extractor, wherein the feature extractor is a self-supervised learning model trained to receive a class-imbalanced dataset as the input data through a basic input path, receive the representative data from the active memory, and output the representation by using the class-imbalanced dataset and the representative data.

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

Systems and techniques are provided for secure computing. For instances, a process can include generating a master private key; generating a set of first dummy values; dividing the master private key into a first set of shares, wherein a sum of shares of the first set of shares equals a value of the master private key; initiating portions of an active memory bank with a sequence of integer modular additions, wherein the integer modular additions comprise: masking the first set of shares of the master private key; and adding the masked first set of shares of the master private key to portions of the active memory bank using a sequence of adds that adds and mixes the masked first set of shares of the master private key with dummy values.

Computing systems and associated methods are described for managing error conditions associated with shared resources in a partitioned computing system. In some examples, a flush signal is generated by a controller of an expansion card or other component of the partitioned computing system responsive to detecting a communication issue between the component and a first host partition. Responsive to the flush signal, an Input / Output (I / O) fabric of the component terminates active memory transactions for the first host partition and transmits a success status signal associated with the active memory transactions to an initiator of the active memory transactions. The controller may then reset a port coupled to the first host partition to prepare the component for re-establishing a link with the first host partition.

The application provides a data persistent storage method and device, electronic equipment and storage medium. The method comprises the following steps: writing state data into a local active prewrite log and an active memory cache according to each partition key; if the written capacity of the active memory cache meets a preset capacity threshold, or the written entries of the local active prewrite log meet a preset entry threshold, determining the active memory cache as an immutable memory cache, determining the local active prewrite log as a local immutable prewrite log, creating a new local active prewrite log and a new active memory cache to continue writing state data; if there is an unexpired local immutable prewrite log, persistently storing the immutable memory cache of the local immutable prewrite log to an external storage service; if the immutable memory cache is completed persistent storage, marking the corresponding local immutable prewrite log as expired to clean up expired logs and caches. The application decouples writing and storage, and improves storage efficiency and reliability.

This application provides a memory-based human-computer interaction method, electronic device, medium, and program product, relating to the field of artificial intelligence technology. It involves acquiring multimodal interactive input information; based on the interactive scenario corresponding to the multimodal interactive input information, performing long short-term memory hierarchical storage processing, memory hybrid retrieval processing, and / or active memory forgetting processing on the multimodal interactive input information to obtain processed target memory data; and generating multimodal interactive output results based on the target memory data. Using this application, a scenario-based hierarchical, human-like memory architecture can be implemented to achieve memory-based dynamic response in human-computer interaction.

Systems, devices, and methods for managing non-power-of-two memory configurations are disclosed. A computing system includes at least one or more clients, a control unit, and a memory subsystem having a non-power-of-two number of active memory channels. The control unit simplifies the ratio of the number of active memory channels to the total number of physical memory channels to the ratio of a first number to a second number. If a first subset of physical address bits of a received memory request is greater than or equal to the first number, the control unit calculates a third number that is equal to a modulo operation of the second subset of physical address bits with respect to the first number, and uses the concatenation of the third number and the third subset of physical address bits to select a memory channel for issuing the received memory request.

A power save mode in multi-channel memory device receives a request to turn off at least one memory channel. The request may be received from a user where a user preference is received as part of the request and includes an indication of the number of memory channels to turn off. The user preference can be stored in a configuration setting and the user preference can be retrieved from the stored configuration setting to enter power save mode. When entering the power save mode, the device is rebooted. Upon restart of the device in power save mode, the device calculates a memory address hash map for the active memory channels. The device may be a system on chip and may include a mobile device operated by battery. When operating in power save mode, the power demand of the disabled memory channels is eliminated to conserve power and battery life.

This specification provides an embodiment of a method for incremental merging in a database system. The database system has a storage architecture of Log Structure Merge Tree (LSM-Tree) and includes data nodes and several compute nodes. The method is executed by a first compute node among the compute nodes and includes: retrieving first incremental data and a first commit log from an active memory table (MEMTable); the first commit log records the generation process of the first incremental data. The first incremental data is persisted to a local first data file by performing a first merging operation (compaction). The first commit log is uploaded to the data node, causing the data node to update the memory checkpoint of the first compute node.

This application discloses a processor chip and a processor chip data prefetching method, relating to the field of integrated circuit technology, and is invented to improve the prefetching efficiency of data from memory to cache. The processor chip includes: a prefetch controller, used to determine whether there is an active memory row in the memory at the current time; if an active memory row exists, it determines whether the memory is currently occupied by an access request; if the memory is not currently occupied by an access request, it sends a prefetch request to the memory controller; the memory controller is used to obtain prefetched data from the active memory row according to the prefetch request and send the prefetched data to the cache controller; and the cache controller is used to receive the prefetched data and store it in the cache. This application is applicable to prefetching memory data.