23 results about "Access line" patented technology

The utility model provides a high altitude 1000kV substation station power supply system with higher reliability relates to substation station power supply technical field. High altitude 1000kV substation station power supply system, including station transformer I, station transformer II, spare power station transformer, first busbar I section, first busbar II section and first busbar III section, the spare power station transformer is accessed from the station, and its low voltage side is connected with first busbar II section, is equipped with the tie -in circuit breaker between first busbar II section and first busbar I section and between first busbar II section and first busbar III section respectively, is equipped with the access line I and access line II of parallel setting on the working section busbar III section, is equipped with station transformer VI on the access line I, is equipped with station transformer VII on the access line II, the access line I is connected with first busbar I section, the access line II is connected with first busbar III section, and double power automatic transfer switch is equipped between the access line II and access line I.

An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

This application is directed to reduced resistivity of access lines in a memory array. A first metal layer can be formed over a via configured to couple an access line of a memory array with a corresponding driver. The first metal layer can be oxidized, and subsequently a second metal layer can be formed over the oxidized first metal layer. One or more access lines of the memory device can be formed from the second metal layer, the oxidized first metal layer, or both.

An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and / or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and / or erase operations performed on the second group of memory cells meeting a criteria.

Systems, devices, and methods of operating a memory system are described. Memory-in-process-enabled memory devices and methods of performing sum and fuse-add operations within the memory-in-process-enabled memory devices are also described. Bit positions of bits stored at one or more portions of one or more memory arrays can be accessed via data lines by activating the same or different access lines. Sense circuits operatively coupled to the data lines can be temporarily formed and measured to determine a state (e.g., a count of a number of bits that are logical "1"s) of the accessed bit positions of the data lines, and the state information can be used to determine a result of a computation.

A method for fabricating a 3D vertical array of memory cells is disclosed. The method includes forming a stack of layers of dielectric material on a substrate, including first and second layers of dielectric material alternating with each other; forming a hole through the stack of layers of dielectric material, the hole exposing the substrate; selectively removing the second material layers via the hole to form cavities between adjacent first layers of dielectric material; filling the cavities with a conductive material via the hole to form corresponding layers of conductive material; forming a first memory cell access line from the layers of conductive material; performing conformal deposition of a chalcogenide material via the hole; forming a memory cell storage element from the deposited chalcogenide material; filling the hole with a conductive material to form a corresponding second memory cell access line.

Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

A display apparatus includes: a display panel including a display layer and a touch screen layer; a flexible printed circuit board electrically connected to one side of the display panel; a driving driver on the display panel; a processor on the flexible printed circuit board; and mobile industry processor interface (MIPI) data lanes on the flexible printed circuit board and electrically connecting the processor and the driving driver to each other, wherein each of the MIPI data lanes includes a first access line and a second access line, and in at least one of the MIPI data lanes, a phase of a signal at the first access line and a phase of a signal at the second access line are configured to be different from each other, based on transmission of a low power state (LPS) signal.

Access line voltage ramp rate adjustment is described herein. An apparatus may include a memory device including a plurality of groups of memory cells and a processing device coupled to the memory device which may receive a program command to be executed on one of the plurality of groups of memory cells and determine if a program verify (PVFY) loop associated with the program command is below a threshold for a subblock of the memory device that includes the one of the plurality of groups. Responsive to a determination that the PVFY loop is not below the threshold, the program command can be executed. Responsive to a determination that the PVFY loop is below the threshold, an unselected access line voltage ramp rate for the subblock can be adjusted to a slower rate, and the program command can be executed using the adjusted unselected access line voltage ramp rate.

A storage device comprises multiple memory cells, each of which includes a resistor and a transistor connected in series between a first access line and a second access line. The first access line has at least one metal track arranged in a first of several metallization layers above a substrate, and a second metal track arranged in a second of the several metallization layers. The second access line has at least one third metal track arranged in a third of the several metallization layers, and a fourth metal track arranged in a fourth of the several metallization layers.The second metallization layer is arranged above the fourth metallization layer, the fourth metallization layer is arranged above the third metallization layer, and the third metallization layer is arranged above the first metallization layer.

A memory device includes a plurality of memory cells, each of the plurality of memory cells including a resistive element and a transistor connected in series between a first access line and a second access line. The first access line includes at least a first metal track disposed in a first one of a plurality of metallization layers over a substrate, and a second metal track disposed in a second one of the plurality of metallization layers. The second access line includes at least a third metal track disposed in a third one of the plurality of metallization layers, and a fourth metal track disposed in a fourth one of the plurality of metallization layers. The second metallization layer is disposed over the fourth metallization layer, the fourth metallization layer is disposed over the third metallization layer, and the third metallization layer is disposed over the first metallization layer.

This disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access means and vertically oriented access lines, comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack, wherein a first portion of the sacrificial material is located in a first region of the vertical stack in which first and second source / drain regions laterally separated by channel regions are formed; forming a first vertical opening using an etchant process to expose a vertical sidewall in the vertical stack adjacent to the first portion of the sacrificial material; selectively etching the first portion of the sacrificial material to form a first horizontal opening, thereby removing sacrificial material in the first region at a first horizontal distance backward from the first vertical opening; and depositing first and second source / drain materials and channel material in the first horizontal opening to form a three-node access means for memory cells in the array of vertically stacked memory cells.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and vertically oriented digit lines having a first source / drain region and a second source drain region separated by a channel region, and gates opposing the channel region, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source / drain region of the horizontally oriented access devices. The vertically oriented digit lines are formed in direct electrical contact with the first source / drain regions of the horizontally oriented access devices. A vertically oriented body contact line is integrated to form the body contact to the body region of the horizontally oriented access device and separate from the first source / drain region and the vertically oriented digit lines by a dielectric.

The application relates to an access line protection device of an optical fiber distribution box or an optical distribution box, comprising a wire arranging plate, the wire arranging plate is used for being mounted to the optical fiber distribution box or the optical distribution box, a plurality of open grooves are arranged at intervals along the length direction on the wire arranging plate, each open groove is opened along the width direction of the wire arranging plate, one end of the open groove away from the optical fiber distribution box or the optical distribution box is an open end, and the open end of the open groove is provided with a anti-withdrawal convex which prevents the optical fiber from being withdrawn from the open groove. The application ensures that the optical fiber at the wire channel of the optical fiber distribution box panel into the optical fiber distribution frame is well protected, the operation space of the optical fiber plug is ensured, the normal identification of the optical fiber label is not affected, and the visual effect of the optical fiber wire is improved.

The application discloses an analysis method and system for main distribution network full voltage level decoupling iteration, relates to the electric power field, and solves the problem of poor analysis effect of the existing main distribution network full voltage level decoupling iteration analysis method, and comprises the following steps: S1, a target main distribution network is divided into a power main network and a plurality of power distribution networks, decoupling demand analysis is performed on the power distribution network and the power main network, a power decoupling demand time ratio corresponding to each power distribution network is obtained according to an analysis result, and power grid decoupling analysis data is obtained; S2, periodic voltage stability analysis is performed on a clean energy access line corresponding to the power distribution network, voltage stability monitoring data corresponding to the power distribution network is obtained according to an analysis result; and S3, decoupling iteration operation is performed on the power distribution network according to the power grid decoupling analysis data and the voltage stability monitoring data, and the application can improve the accuracy of power distribution network decoupling operation and iteration operation.

This utility model belongs to the field of short-circuit current limiter on / off control technology, and discloses an automatic on / off optocoupler isolation circuit for a short-circuit current limiter, including a first power supply, an access switch S1, resistors R41 and R1, capacitor C1, optocoupler U1, a second power supply, resistors R2 and C2, and a circuit breaker; the external on / off contact of the circuit breaker is connected to the access switch S1 through a preset access line; in this utility model, the external on / off contact of the circuit breaker is connected to the access switch S1 through a preset access line, and the automatic on / off control of the short-circuit current limiter is realized by the closing and opening of the access switch S1, without manual intervention, thus improving the automation level and operating efficiency of the system; by introducing the optocoupler U1, effective isolation between the input signal and the output signal is achieved, which helps to protect other components in the circuit from possible interference or damage caused by the input signal.

A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source / drain regions.

The present disclosure relates to shared vertical digit lines for semiconductor devices. Systems, methods, and apparatus are provided for a vertically stacked memory cell array having horizontally oriented access devices and access lines and shared vertically oriented digit lines. The access devices have a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite the channel region. A horizontally oriented access line is coupled to the gate and separated from the channel region by a gate dielectric. The memory cells have a horizontally oriented storage node coupled to the second source / drain region of the horizontally oriented access devices. The shared vertically oriented digit line is shared between two adjacent horizontally oriented access devices and coupled to the first source / drain region of the two adjacent horizontally oriented access devices.

This application is directed to decoder architectures for memory devices. An apparatus includes a memory array having memory cells and access lines coupled with the cells, and a decoder having a first stage and a second stage. The decoder supplies a first voltage to the access lines during a first access operation and a second voltage to the access lines during a second access operation. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

The utility model discloses an anti -accidental touch's audio and video signal switch relates to audio and video signal switch technical field, including audio and video signal switch main part, inlet, audio and video signal switch main part's one side evenly is provided with the inlet, and the audio and video signal switch main part on the outside of inlet is fixed with the support. The utility model discloses being provided with elastic snap ring, it can fix to the access line, and after fixing to the upper and lower multiple sets of line, through the movement of adjusting piece in adjusting groove, the position of elastic snap ring and connecting line is adjusted, can be through horizontal moving mode to the line placement area and be adjusted, when the multiple sets of line of upper and lower sides are connected, can form the interlaced placement state between the line through the movement adjustment after fixing to the line, thereby reducing the influence between the line, and the staff is convenient to find and use simultaneously.