156 results about "Access line" patented technology

A memory circuit comprises: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sampling amplifier coupled to the first and second memory cells, respectively, via a data bit line and a reference bit line; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.

A memory device includes a memory array with a plurality of memory cells formed at respective intersections of a plurality of wordlines and a plurality of bit lines. The memory device further control logic to initiate a program operation on one or more memory cells in a first block of the memory array, the program operation comprising a program phase, a program recovery phase, and a program exit phase. The control logic further causes a positive voltage pulse having a fixed duration to be applied to at least a subset of a plurality of bitlines of the memory array during the program exit phase of the program operation and causes the positive voltage pulse having the fixed duration to be applied to an access line controlling one or more drain-side select gate devices in the first block of the memory array during the program exit phase of the program operation.

The present disclosure provides a service control method and system and a vBRAS-CP device, and relates to the field of data communication. The vBRAS-CP device acquires a user access message, and according to VLAN information or access line information in the user access message, distributes users of the same family to the same vBRAS-pUP device access, so as to be able to perform unified service control such as flow rate limiting based on the family dimension.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source / drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source / drain region and vertically oriented digit lines coupled to the first source / drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source / drain region and the vertically oriented digit lines by a dielectric.

A method used in forming memory circuitry comprising memory cells comprises forming vertically-alternating insulative tiers and memory-cell tiers. The memory cells individually comprise a horizontal transistor comprising a gate that comprises part of one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier. The access lines extend horizontally from the memory-array region into a connection region. Over a same time period and using the same processing steps, digitlines are formed in the memory-array region that individually directly electrically couple to the horizontal transistors in different ones of the memory-cell tiers and conductive-via constructions are formed in the connection region that individually directly electrically couple to individual of the access lines. Other embodiments, including structure, are disclosed.

The utility model provides a high altitude 1000kV substation station power supply system with higher reliability relates to substation station power supply technical field. High altitude 1000kV substation station power supply system, including station transformer I, station transformer II, spare power station transformer, first busbar I section, first busbar II section and first busbar III section, the spare power station transformer is accessed from the station, and its low voltage side is connected with first busbar II section, is equipped with the tie -in circuit breaker between first busbar II section and first busbar I section and between first busbar II section and first busbar III section respectively, is equipped with the access line I and access line II of parallel setting on the working section busbar III section, is equipped with station transformer VI on the access line I, is equipped with station transformer VII on the access line II, the access line I is connected with first busbar I section, the access line II is connected with first busbar III section, and double power automatic transfer switch is equipped between the access line II and access line I.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input / output (I / O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I / O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

The utility model relates to the technical field of transfer box intelligent storing and taking cabinets, in particular to a novel transfer box intelligent storing and taking cabinet which is characterized by comprising a feeding module, an industrial robot module and a conveying module, the feeding module comprises a separation net, a feeding port is formed in the bottom end of the separation net, a bearing disc is connected to the feeding port, and the industrial robot module is connected with the conveying module. A medical waste transfer box is placed on the surface of the bearing disc, the industrial robot module is composed of a carrying mechanical arm module and a driving guide rail module, and the conveying module comprises three transfer storing and taking counters which are arranged in a stacked mode. By designing the conveying module, an original linear access cabinet is folded in half, the length of an access line is reduced by half, the number of access transfer boxes is not changed, an annular assembly line mode is adopted, transfer access cabinets are arranged in three layers up and down and driven by three alternating-current motors, and four discharging ports are formed; and a sensor is arranged at each discharge port, and whether materials exist at the discharge point or not is detected in real time through the sensors.

An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

The invention relates to a method for manufacturing a platform for cellular interfacing, the platform being manufactured over a predetermined bulk substrate, the method being a top-down method.According to the invention, such a method comprises the following steps in order:creating (E10) vertical nanowires over the bulk substrate;depositing (E30) a Si layercreating (E40) the access lines for accessing the nanowires;selective silicidation (E50) of the access lines and of the nanowires;metal structuring (E60) of the access lines;depositing (E60) an insulating layer for liquid measurement;selective removal (E70) of the insulating layer on the nanoprobes.

This application is directed to reduced resistivity of access lines in a memory array. A first metal layer can be formed over a via configured to couple an access line of a memory array with a corresponding driver. The first metal layer can be oxidized, and subsequently a second metal layer can be formed over the oxidized first metal layer. One or more access lines of the memory device can be formed from the second metal layer, the oxidized first metal layer, or both.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source / drain regions.

This application relates to a memory with optimized resistance layers. A memory system can include a separate amount or type of resistive material deposited over a memory cell and a conductive via using a separate resistance layer in an access line. A first resistive material layer can be deposited over the memory cell prior to performing an array termination etch for depositing the array of conductive vias. The array termination etch can remove the first resistive material over portions of the array for depositing the conductive vias. A second resistive material layer can be deposited after the etch has occurred and the conductive vias have been formed. The second resistive material layer can be deposited over the conductive vias.

Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes a vertically-oriented contact pillar and a tiered structure proximate to the vertically-oriented contact pillar. The tiered structure includes an access line between two insulative layers and insulative fill structure. The insulative fill structure includes a tapered portion that is between the vertically-oriented contact pillar and the access line. The tapered portion may be between facing surfaces of ends of the insulative layers.

The utility model discloses a filter with a communication access protection port, comprising a filter main body, the bottom end of the filter main body is provided with a positioning pedestal for positioning the filter main body after installation; the two sides of the positioning pedestal are provided with side protection plates for protecting the connection between the signal ports at the two ends of the filter body and an external signal line, so that the port protection cavities in the rubber pads cover the outer sides of the signal input connection port and the signal output connection port for tight wrapping protection. The cylindrical positioning plug sleeve is inserted into the tightening fixing cavity of the conical structure on the signal line, and the tightening fixing cavity is continuously narrowed to enable the conical positioning plug sleeve to be shrunk and pressed at the connection part of the access line, so that the connection parts of the access line, the signal input connection port and the signal output connection port can be effectively tightened and fixed; and the access line port and the filter access port can be protected at the same time, so that the phenomena of loosening and falling cannot occur in long-time use.

To enable determination whether a telephone number to be investigated is a valid telephone number with a subscription contract.SOLUTION: A determination method includes a transmission step of transmitting, to a first IP network, transmission information indicating that a call is made to a telephone number to be investigated, the transmission information being response information including an error message from the first IP network using an optical line as an access line or a second IP network connected to the first IP network and operated by a communication network provider different from the first IP network; and a determination step of determining whether the telephone number is the telephone number validated by making a subscription contract in the second IP network or the telephone number invalidated by not making the subscription contract in the second IP network, based on response information received from the first IP network.SELECTED DRAWING: Figure 1

The invention relates to a memory device. A memory device includes a memory cell and a write circuit. The memory cell is coupled to the first access line and the second access line. The write circuit applies a first positive voltage to the first access line for a first period, applies a second positive voltage to the first access line for a second period, the second period after the first period, and applies a negative voltage to the second access line for the first period and the second period.

Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

The application relates to the technical field of AGV brush plates, and discloses an AGV brush plate with terminal outgoing lines, which comprises a brush block arranged on an AGV trolley, a brush plate arranged on the ground, a wiring mechanism, a groove arranged on the side surface of the brush plate and used for mounting the wiring mechanism, a contact mechanism arranged on the brush plate, and a buffer mechanism arranged at the bottom of the contact mechanism. The wiring mechanism comprises an access line, a sealing plug arranged on the access line, a connecting ring connected to the access line, and a positioning bolt connected to the bottom of the connecting ring. The AGV brush plate with terminal outgoing lines is installed in the groove arranged on the side surface of the brush plate through the wiring mechanism, which can provide physical protection for the cable, reduce the risk of collision and scraping of the cable in the external environment, and reduce the system failure probability; on the other hand, the cable bending demand is reduced, the problems of laborious bending and easy damage are avoided, and stable power transmission is ensured.

Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

Systems, methods, and apparatus for memory devices having shunting networks connected to access lines. In one approach, a memory device has memory cells arranged in a memory array. The memory cells are accessed using bitlines that are formed overlying the array. The bitlines are coupled to a shunting network that reduces the effective resistance of the bitlines. This improves performance when performing matrix vector multiplication using the memory array.

An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and / or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and / or erase operations performed on the second group of memory cells meeting a criteria.

A method can comprise receiving data corresponding to a sequence of write commands to write the data to a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block having a first programming characteristic; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block having a second programming characteristic. The method can further comprise writing data sequentially to the first erase blocks of the plurality of strings and the second erase blocks of the plurality of strings in an interleaved manner by: writing a first portion of the data to one or more first erase blocks of the plurality of strings; and writing, subsequent to writing the first portion of the data to the one or more first erase blocks, a second portion of the data to one or more second erase blocks of the plurality of strings.

Data storage device comprising: a memory cell arrangement (12) with a plurality of planar memory cells; a multilayer arrangement (13) of access lines (14, 15) which provides a connection between the plurality of memory cells and which at least partially overlaps with the memory cell arrangement (12); wherein the multilayer arrangement (13) of access lines (14, 15) is configured such that when a first layer (161) of access lines (14) is removed while a second layer (162) of access lines (15) arranged between the first layer (161) and the memory cell arrangement (12) remains, at least one connection is interrupted;

Memories might include a controller configured to cause the memory to develop a respective voltage level in a channel of each memory cell of a plurality of memory cells selected for a programming operation, apply a programming voltage level to a selected access line of the programming operation, determine a number of memory cells of the plurality of memory cells passing verify for each data state of a subset of data states, selectively modify values of the respective channel voltage levels in response to at least the determined number of memory cells passing verify for each of the data states of the subset of data states, and perform a subsequent programming operation using the selectively modified values of the channel voltage levels.

The invention relates to memory circuitry and methods for forming memory circuitry. A method for forming memory circuitry including memory cells includes forming vertically alternating insulating levels and memory cell levels. The memory cells individually include horizontal transistors including gates including portions of one of a plurality of horizontal conductive access lines that individually, directly and electrically couple together multiple of the gates of different ones of the horizontal transistors located in the same memory cell level. The access lines extend horizontally from the memory array region into the connection region. Within the same time period and using the same processing step, digital lines individually electrically coupled directly to horizontal transistors in different ones of the memory cell levels are formed in the memory array region, and conductive path configurations individually electrically coupled directly to individual ones of the access lines are formed in the connection region. Other embodiments, including structures, are disclosed.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source / drain regions.

The present disclosure relates to a memory configured to erase memory cells from a series-connected subset of memory cell strings of a block of memory cells. The memory may include a controller configured to cause the memory to: apply a first voltage level to each of a plurality of data lines; generating a gate induced drain leakage (GIDL) from the selected data line to a channel structure of the respective series-connected memory cell string; suppressing the generation of GIDL from the unselected data lines to the channel structures of the respective series-connected memory cell strings; and applying a second voltage level to a selected access line of a respective memory cell connected to each of the series-connected memory cell strings, where the second voltage level is configured to remove charge from its respective memory cell of the respective series-connected memory cell strings of the selected data line, and configured to suppress removal of charge from their respective memory cells of the respective series-connected memory cell strings of the unselected data lines.