211 results about "Access line" patented technology

A method can comprise applying, to program memory cells of a first erase block coupled to a first string of a memory array, a seed voltage through a sense line coupled to the first string. The method can further comprise applying, to program memory cells of the first erase block sequentially from a source side to a drain side, a respective programming voltage to access lines of the first erase block sequentially from a first access line of the first erase block to a second access line of the first erase block. The first access line can be located adjacent to one or more dummy access lines separating the first erase block from a second erase block coupled to the first string. The second access line can be located at the drain side of the first string.

A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

A memory circuit comprises: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sampling amplifier coupled to the first and second memory cells, respectively, via a data bit line and a reference bit line; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

A memory device includes a memory array with a plurality of memory cells formed at respective intersections of a plurality of wordlines and a plurality of bit lines. The memory device further control logic to initiate a program operation on one or more memory cells in a first block of the memory array, the program operation comprising a program phase, a program recovery phase, and a program exit phase. The control logic further causes a positive voltage pulse having a fixed duration to be applied to at least a subset of a plurality of bitlines of the memory array during the program exit phase of the program operation and causes the positive voltage pulse having the fixed duration to be applied to an access line controlling one or more drain-side select gate devices in the first block of the memory array during the program exit phase of the program operation.

The present disclosure provides a service control method and system and a vBRAS-CP device, and relates to the field of data communication. The vBRAS-CP device acquires a user access message, and according to VLAN information or access line information in the user access message, distributes users of the same family to the same vBRAS-pUP device access, so as to be able to perform unified service control such as flow rate limiting based on the family dimension.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source / drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source / drain region and vertically oriented digit lines coupled to the first source / drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source / drain region and the vertically oriented digit lines by a dielectric.

A memory circuit comprises a memory array, a first access circuit, and a second access circuit. The memory array may comprise a plurality of non-volatile memory cells. The non-volatile memory cells can be arranged along a plurality of first access lines and a plurality of second access lines. The first access lines and second access lines may each extend along a lateral direction across the memory array. The first access circuit can be physically disposed on a first side of the memory array in the lateral direction. The second access circuit can be physically disposed on a second side of the memory array in the lateral direction. The second side is opposite to the first side.

A method used in forming memory circuitry comprising memory cells comprises forming vertically-alternating insulative tiers and memory-cell tiers. The memory cells individually comprise a horizontal transistor comprising a gate that comprises part of one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier. The access lines extend horizontally from the memory-array region into a connection region. Over a same time period and using the same processing steps, digitlines are formed in the memory-array region that individually directly electrically couple to the horizontal transistors in different ones of the memory-cell tiers and conductive-via constructions are formed in the connection region that individually directly electrically couple to individual of the access lines. Other embodiments, including structure, are disclosed.

The utility model provides a high altitude 1000kV substation station power supply system with higher reliability relates to substation station power supply technical field. High altitude 1000kV substation station power supply system, including station transformer I, station transformer II, spare power station transformer, first busbar I section, first busbar II section and first busbar III section, the spare power station transformer is accessed from the station, and its low voltage side is connected with first busbar II section, is equipped with the tie -in circuit breaker between first busbar II section and first busbar I section and between first busbar II section and first busbar III section respectively, is equipped with the access line I and access line II of parallel setting on the working section busbar III section, is equipped with station transformer VI on the access line I, is equipped with station transformer VII on the access line II, the access line I is connected with first busbar I section, the access line II is connected with first busbar III section, and double power automatic transfer switch is equipped between the access line II and access line I.

The invention relates to the technical field of power electronics, and discloses a power supply detection control circuit and electrical equipment. When a mains supply access line sequence is correct, a comparator power supply circuit supplies power to a comparator, so that the comparator works normally, a voltage difference is generated at the two ends of a first energy storage element, and the comparator outputs a high level; and otherwise, if the live wire is reversely connected with the null line, the comparator power supply circuit stops supplying power to the comparator, the comparator cannot work, the control circuit is disconnected, and the electric load cannot be electrified. Therefore, only under the condition that the commercial power access line sequence is correct, the electric load can be accessed to the live wire to be electrified to work normally, and when the commercial power live wire and the neutral wire are reversely connected, the live wire is cut off to supply power, so that potential safety hazards caused to the electric load or a human body are avoided, the electric safety is guaranteed, and the use experience of a user is improved.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input / output (I / O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I / O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

The present invention relates to the field of power electronics technology, and discloses a power supply detection control circuit and electrical equipment. The present invention enables the comparator to operate normally by supplying power to the comparator through the comparator power supply circuit when the mains power access line sequence is correct, and generates a voltage difference at both ends of the first energy storage element, so that the comparator outputs a high level, thereby controlling the control circuit provided between the live wire access end and the power supply end of the power load to be turned on, so that the power load can be powered and operate normally. Conversely, if the live wire and the neutral wire are connected in reverse, the comparator power supply circuit stops supplying power to the comparator, the comparator cannot work, the control circuit is disconnected, and the power load will not be powered. This ensures that the power load will only be connected to the live wire and operate normally when the mains power access line sequence is correct, and cuts off the live wire power supply when the mains power live wire and the neutral wire are connected in reverse, so as to avoid potential power safety hazards to the power load or people, ensure power safety, and enhance the user experience.

The utility model relates to the technical field of transfer box intelligent storing and taking cabinets, in particular to a novel transfer box intelligent storing and taking cabinet which is characterized by comprising a feeding module, an industrial robot module and a conveying module, the feeding module comprises a separation net, a feeding port is formed in the bottom end of the separation net, a bearing disc is connected to the feeding port, and the industrial robot module is connected with the conveying module. A medical waste transfer box is placed on the surface of the bearing disc, the industrial robot module is composed of a carrying mechanical arm module and a driving guide rail module, and the conveying module comprises three transfer storing and taking counters which are arranged in a stacked mode. By designing the conveying module, an original linear access cabinet is folded in half, the length of an access line is reduced by half, the number of access transfer boxes is not changed, an annular assembly line mode is adopted, transfer access cabinets are arranged in three layers up and down and driven by three alternating-current motors, and four discharging ports are formed; and a sensor is arranged at each discharge port, and whether materials exist at the discharge point or not is detected in real time through the sensors.

Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

The invention relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device may include: a stacked structure including first access lines and first insulating layers alternately stacked and extending in a first direction; a first air gap positioned to correspond to the first insulating layer and extending in a first direction along a sidewall of the stacked structure; an electrode post extending through the stack structure; and a second air gap positioned to correspond to the first insulating layer and surround the electrode post.

An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

The invention relates to a display device and an electronic device. The display device includes: a display panel including a display layer and a touch screen layer; a flexible printed circuit board electrically connected to one side of the display panel; a driving driver on the display panel; a processor on the flexible printed circuit board; and a plurality of mobile industrial processor interface (MIPI) data channels on the flexible printed circuit board and electrically connecting the processor and the drive driver to each other, in which each of the plurality of MIPI data channels includes a first access line and a second access line, and in at least one of the plurality of MIPI data channels, the processor and the drive driver are electrically connected to each other based on transmission of a low power state (LPS) signal. The phase of the signal at the first access line and the phase of the signal at the second access line are configured to be different from each other.

The invention relates to a method for manufacturing a platform for cellular interfacing, the platform being manufactured over a predetermined bulk substrate, the method being a top-down method.According to the invention, such a method comprises the following steps in order:creating (E10) vertical nanowires over the bulk substrate;depositing (E30) a Si layercreating (E40) the access lines for accessing the nanowires;selective silicidation (E50) of the access lines and of the nanowires;metal structuring (E60) of the access lines;depositing (E60) an insulating layer for liquid measurement;selective removal (E70) of the insulating layer on the nanoprobes.

This application is directed to reduced resistivity of access lines in a memory array. A first metal layer can be formed over a via configured to couple an access line of a memory array with a corresponding driver. The first metal layer can be oxidized, and subsequently a second metal layer can be formed over the oxidized first metal layer. One or more access lines of the memory device can be formed from the second metal layer, the oxidized first metal layer, or both.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source / drain regions.

This application relates to a memory with optimized resistance layers. A memory system can include a separate amount or type of resistive material deposited over a memory cell and a conductive via using a separate resistance layer in an access line. A first resistive material layer can be deposited over the memory cell prior to performing an array termination etch for depositing the array of conductive vias. The array termination etch can remove the first resistive material over portions of the array for depositing the conductive vias. A second resistive material layer can be deposited after the etch has occurred and the conductive vias have been formed. The second resistive material layer can be deposited over the conductive vias.

Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes a vertically-oriented contact pillar and a tiered structure proximate to the vertically-oriented contact pillar. The tiered structure includes an access line between two insulative layers and insulative fill structure. The insulative fill structure includes a tapered portion that is between the vertically-oriented contact pillar and the access line. The tapered portion may be between facing surfaces of ends of the insulative layers.

The utility model discloses a filter with a communication access protection port, comprising a filter main body, the bottom end of the filter main body is provided with a positioning pedestal for positioning the filter main body after installation; the two sides of the positioning pedestal are provided with side protection plates for protecting the connection between the signal ports at the two ends of the filter body and an external signal line, so that the port protection cavities in the rubber pads cover the outer sides of the signal input connection port and the signal output connection port for tight wrapping protection. The cylindrical positioning plug sleeve is inserted into the tightening fixing cavity of the conical structure on the signal line, and the tightening fixing cavity is continuously narrowed to enable the conical positioning plug sleeve to be shrunk and pressed at the connection part of the access line, so that the connection parts of the access line, the signal input connection port and the signal output connection port can be effectively tightened and fixed; and the access line port and the filter access port can be protected at the same time, so that the phenomena of loosening and falling cannot occur in long-time use.

The invention relates to the field of power utilization monitoring, and discloses a power utilization monitoring method for a power distribution box, which is used for solving the problem of zero offset during power utilization monitoring, and comprises the following steps of: installing power monitoring equipment at an access line in the power distribution box, and acquiring data offset information of the power monitoring equipment; obtaining an offset index through evaluation according to the data offset information, carrying out zero offset judgment, collecting initial electric power data through the electric power monitoring equipment if the electric power monitoring equipment is judged to have zero drift, carrying out zero correction on the initial electric power data according to the offset index to obtain corrected electric power data, and carrying out zero correction on the corrected electric power data. The power abnormality index is calculated according to the corrected power data, power abnormality judgment is carried out according to the power abnormality index, and if power abnormality is judged, power abnormality early warning is carried out, so that the accuracy of power consumption data acquisition is effectively improved, the accuracy of an operation and maintenance strategy is improved, and the safety risk probability is reduced.

To enable determination whether a telephone number to be investigated is a valid telephone number with a subscription contract.SOLUTION: A determination method includes a transmission step of transmitting, to a first IP network, transmission information indicating that a call is made to a telephone number to be investigated, the transmission information being response information including an error message from the first IP network using an optical line as an access line or a second IP network connected to the first IP network and operated by a communication network provider different from the first IP network; and a determination step of determining whether the telephone number is the telephone number validated by making a subscription contract in the second IP network or the telephone number invalidated by not making the subscription contract in the second IP network, based on response information received from the first IP network.SELECTED DRAWING: Figure 1

The invention relates to a memory device. A memory device includes a memory cell and a write circuit. The memory cell is coupled to the first access line and the second access line. The write circuit applies a first positive voltage to the first access line for a first period, applies a second positive voltage to the first access line for a second period, the second period after the first period, and applies a negative voltage to the second access line for the first period and the second period.

A device structure includes a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate; first access lines electrically connected to a respective row of memory cells within the two-dimensional array; and a first decoder circuit including first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the first access lines.

Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.