19 results about "Associative cache" patented technology

A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.

Systems and methods for a scalable hardware cache with configurable logical ports and related thread management are described. A scalable hardware cache includes a request interface having a first logical port and a second logical port associated with a fully-associative cache memory. The first logical port is configured to receive a first set of read requests with an expected cache hit and the second logical port is configured to receive a second set of read requests with an expected cache miss. The scalable hardware cache further includes thread processing circuitry to manage a first maximum number of a first set of threads for processing the first set of read requests and a second maximum number of a second set of threads for processing the second set of read requests that can be active at a given time based on a performance metric associated with the scalable hardware cache.

Systems and methods for a scalable hardware cache with configurable logical ports and related thread management are described. A scalable hardware cache includes a request interface having a first logical port and a second logical port associated with a fully-associative cache memory. The first logical port is configured to receive a first set of read requests with an expected cache hit and the second logical port is configured to receive a second set of read requests with an expected cache miss. The scalable hardware cache further includes thread processing circuitry to manage a first maximum number of a first set of threads for processing the first set of read requests and a second maximum number of a second set of threads for processing the second set of read requests that can be active at a given time based on a performance metric associated with the scalable hardware cache.

A microprocessor includes a physically-indexed physically-tagged second-level set-associative cache. A set index and a way uniquely identifies each entry. A load / store unit, during store / load instruction execution: detects that a first and second portions of store / load data are to be written / read to / from different first and second lines of memory specified by first and second store physical memory line addresses, writes to a store / load queue entry first and second store physical address proxies (PAPs) for first and second store physical memory line addresses (and all the store data in store execution case). The first and second store PAPs comprise respective set indexes and ways that uniquely identifies respective entries of the second-level cache that holds respective copies of the respective first and second lines of memory. The entries of the store queue are absent storage for holding the first and second store physical memory line addresses.

A method and device are provided in which a controller of a storage device determines whether entries of a tag array and a floating tag array, in a cache memory of the storage device, include an entry that corresponds to an object, in a data array of the cache memory, that is to be fetched or updated. In case that the entries comprise the entry that corresponds to the object, the controller also fetches or updates the object in the data array. The entries comprise tag entries of the tag array and floating tag entries of the floating tag array. The floating tag entries are associated with objects in one or more data entries of the data array, and the objects are smaller than or equal to a data entry size of the data array.

In order to further improve the quality of texture mapping and solve the problem of large dynamic random memory bandwidth consumption and data efficiency bottleneck, the application provides a method and device for texture mapping hardware acceleration, which improves the method of output pixel texture mapping to texture pixel points, replaces the bilinear interpolation with bicubic interpolation, and designs a static memory as a multi-path group associative cache, which can set different cache layers according to different application scenarios to reduce the consumption of memory resources, and effectively reduce the redundant bandwidth. The application can flexibly configure the texture cache hierarchy size according to the required texture mapping scene, realize the hardware acceleration of texture mapping through bicubic interpolation, and is suitable for various types of three-dimensional graphics systems.

This application is directed to full-associative cache management. A memory sub-system can receive an access command to store a first data word in a storage component associated with an address space. The memory sub-system can include a full-associative cache to store the data word associated with the storage component. The memory sub-system can determine an address within the cache to store the first data word. For example, the memory sub-system can determine the address of the cache indicated by an address pointer (e.g., based on an order of the address) and determine a number of accesses associated with the data word stored in the cache address. Based on the indicated cache address and the number of accesses, the memory sub-system can store the first data word in the indicated cache address or a second cache address consecutive to the indicated cache address.

Disclosed is a dynamic random access memory (DRAM) that includes a plurality of data rows and a plurality of tag rows. The DRAM includes a communication interface to receive a first group of address bits. The DRAM includes one or more comparators to generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the plurality of tag rows. The one or more comparators are further to combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.

Adaptive system detection actions for minimizing input / output dirty data transmissions are described. In one or more implementations, a system includes: a processor; a memory configured to store data; and a cache configured to store a portion of the data stored in the memory for execution by the processor. The system also includes a cache coherency controller, the cache coherency controller including a cache line history. The cache coherency controller is configured to detect a direct memory access request from an input / output device. The direct memory access request is associated with an input / output operation involving the data. The cache coherency controller is further configured to: identify a cache line associated with the direct memory access request; and in response to the cache line history including a dirty data transfer record corresponding to the cache line, selectively transmitting a probe to the cache based on a state of the cache line.

An apparatus comprises a set associative cache, and cache replacement control circuitry to select, for a given set of the set associative cache, a victim cache entry to be replaced with a new cache entry. The victim cache entry is selected based on cache replacement selection values indicative of a relative priority for selection as the victim cache entry. In response to identifying a plurality of highest victim priority cache entries having equal cache replacement selection values indicative of equal highest priority to be selected as the victim cache entry, the cache replacement control circuitry is configured to select the victim cache entry based on a set-specific selection criterion which favours selection of a victim cache entry belonging to a preferred way for the given set, wherein the preferred way differs between at least two sets of the set associative cache.

A method, computer program product, and computer system for reading data stored in a set associative cache. A cache read instruction that did not read the cache after being previously launched is relaunched after an effective address (EA) of the instruction was ascertained. A hash of the ascertained EA (EAHash) and a class congruence class (CCC) is determined from the ascertained EA. A search is performed for a match of the EAHash and CCC of the ascertained EA to the EAHash and CCC, respectively, of an instruction whose EAHash, CCC, and set are stored in an instruction history stream. If the match is found, only read enables associated with the stored set of the match, which is a read enable of only one class of one address group in the cache, are activated. If the match is not found, all read enables of the one address group are activated.

This invention provides an on-chip FLASH prefetch accelerator, relating to the field of processor memory access optimization technology, including a cache array, an address matching unit, and a prefetch control unit. This invention utilizes a cache array composed of multiple set-associative caches to efficiently cache frequently accessed data in the on-chip FLASH and supports parallel read / write operations. The address matching unit determines whether a processor read request hits the cache. If the read request misses the cache, data needs to be read from the on-chip FLASH. The prefetch control unit loads the target data and its adjacent data into the cache array within the inherent read latency of the FLASH, completing parallel prefetching. Therefore, when a read request hits the cache array, the target data is directly retrieved from the cache array, significantly reducing the waiting latency of on-chip FLASH read access and significantly improving the overall data access efficiency and system performance of the microcontroller.

This application discloses a memory access request processing method, apparatus, cache, and computer system. It uses a temporary buffer with the same depth as the missing state holding register to cache the memory access responses corresponding to each data memory access request. It searches and pops target request entries from the missing state holding register whose readiness state is "data ready" and whose corresponding cache group is unlocked. Based on the cache index in the target request entry, it reads the memory access response corresponding to the cache index from the temporary buffer and stores the read memory access response into the cache line corresponding to the data memory access request. This method ensures that while allocating cache lines for data memory access requests, the total number of memory access responses is at most equal to the depth of the missing state holding register, making the temporary buffer depth controllable. It solves the cache group locking problem in a delayed allocation architecture for set-associative caches and avoids backpressure.

The application discloses a solid state disk address mapping method based on group associative cache, a flash memory controller and a system, and belongs to the technical field of data storage, and comprises the following steps: a cache table containing N mapping groups is established in DRAM, each mapping group contains M slot positions, and each slot position is used for storing a mapping entry recording the mapping relationship from a logical page number to a physical page number; a logical address space is evenly divided into multiple LPN segments, each LPN segment contains continuous A logical page numbers, and the logical page numbers in the same LPN segment are mapped to the same mapping group; the mapping group number to which the logical page number LPN is mapped is; in the same mapping group, dirty entries are stored in the bottom of the mapping group; on this basis, logical and physical continuous mapping pairs are compressed and combined; when the dirty entries in the mapping group reach a threshold value, batch writing is started on the corresponding writing group. The application can realize low-overhead address mapping in limited DRAM space and maintain the relatively optimal read-write performance of a solid state disk.

The application relates to a multi-path group connection cache memory and an access method and computer equipment thereof, which comprise a controller, an address management module, a data storage module and a hit judgment module; the data storage module comprises a plurality of first static random access memories, each of which comprises m storage units; each path comprises a plurality of cache lines, and the data of each cache line is divided into m categories of data sub-blocks in high-low order; m categories of data sub-blocks of each path are stored in the m first static random access memories respectively, and a plurality of data sub-blocks of the same category of each path are stored in the same storage unit; the categories of the data sub-blocks stored in the m storage units of each first static random access memory are all different; and m is greater than 0. Through the application, the technical problem of low row utilization rate of the SRAM of the DATA-SRAM in the current small-capacity Cache can be solved.

An operating method of a set-associative cache includes selecting one way group from among a first way group and a second way group with different threshold voltages based on an operation state of the set-associative cache, increasing a number of ways to which power is supplied in the selected one way group, analyzing a change in an operation state of a system including the set-associative cache as the number of ways to which the power is supplied is increased, and determining whether to further increase the number of ways to which the power is supplied based on an analyzed change in the operation state of the system.

A method (1100) includes receiving a first request for allocation of a way in an N-way set-associative cache (1102), and allocating the way for the first request in response to a cache coherency state of the way indicating that a cache line stored in the way is invalid (1104). The method also includes randomly selecting one of the ways in the set in response to none of the ways in the set having a cache coherency state indicating that the cache line stored in the way is invalid (1106). The method also includes allocating the selected way for the first request in response to a cache coherency state of the selected way indicating that another request is not pending for the selected way (1108).

This application relates to pseudo-random way selection. A method (1100) includes receiving a first request (1102) to allocate a line in an N-way set-associative cache, and allocating (1104) a way for the first request in response to a cache coherency state of the way indicating that a cache line stored in the way is invalid. The method also includes randomly selecting (1106) one of the ways in the set in response to none of the ways in the set having a cache coherency state indicating that the cache line stored in the way is invalid. The method also includes allocating (1108) the selected way for the first request in response to a cache coherency state of the selected way indicating that another request is not pending for the selected way.

A method, computer program product, and computing system for assigning a data shard associated with a machine learning application to each CPU core of a plurality of CPU cores. The data shard of a respective CPU core is loaded to a corresponding affinitized cache memory. A processing thread for the data shard is assigned to the respective CPU core. Multiple processing threads for the data shard are executed using the same respective CPU core and the corresponding cache memory.