Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Cache memory having configurable associativity

a memory and associative technology, applied in the field of microprocessor caches, can solve problems such as increasing power consumption

Inactive Publication Date: 2009-01-01
GLOBALFOUNDRIES INC
View PDF13 Cites 34 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]In one specific implementation, the cache memory may operate in a fully associative addressing mode and a direct addressing mode. When programmed to operate in the fully associative addressing mode, the cache controller may disable independent access to each of the independently acc

Problems solved by technology

However, the increased associativity may result in increased power consumption due, for example, to the increased number of tag look ups that need to be performed for each access.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Cache memory having configurable associativity
  • Cache memory having configurable associativity
  • Cache memory having configurable associativity

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013]Turning now to FIG. 1, a block diagram of one embodiment of a computer system 10 is shown. In the illustrated embodiment, the computer system 10 includes a processing node 12 coupled to memory 14 and to peripheral devices 13A-13B. The node 12 includes processor cores 15A-15B coupled to a node controller 20 which is further coupled to a memory controller 22, a plurality of HyperTransport™ (HT) interface circuits 24A-24C, and a shared level three (L3) cache memory 60. The HT circuit 24C is coupled to the peripheral device 16A, which is coupled to the peripheral device 16B in a daisy-chain configuration (using HT interfaces, in this embodiment). The remaining HT circuits 24A-B may be connected to other similar processing nodes (not shown) via other HT interfaces (not shown). The memory controller 22 is coupled to the memory 14. In one embodiment, node 12 may be a single integrated circuit chip comprising the circuitry shown therein in FIG. 1. That is, node 12 may be a chip multip...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A processor cache memory subsystem includes a cache memory having a configurable associativity. The cache memory may operate in a fully associative addressing mode and a direct addressing mode with reduced associativity. The cache memory includes a data storage array including a plurality of independently accessible sub-blocks for storing blocks of data. For example each of the sub-blocks implements an n-way set associative cache. The cache memory subsystem also includes a cache controller that may programmably select a number of ways of associativity of the cache memory. When programmed to operate in the fully associative addressing mode, the cache controller may disable independent access to each of the independently accessible sub-blocks and enable concurrent tag lookup of all independently accessible sub-blocks, and when programmed to operate in the direct addressing mode, the cache controller may enable independent access to one or more subsets of the independently accessible sub-blocks.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates to microprocessor caches and, more particularly, to cache accessibility and associativity.[0003]2. Description of the Related Art[0004]Since s computer system's main memory is typically designed for density rather than speed, microprocessor designers have added caches to their designs to reduce the microprocessor's need to directly access main memory. A cache is a small memory that is more quickly accessible than the main memory. Caches are typically constructed of fast memory cells such as static random access memories (SRAMs) which have faster access times and bandwidth than the memories used for the main system memory (typically dynamic random access memories (DRAMs) or synchronous dynamic random access memories (SDRAMs)).[0005]Modern microprocessors typically include on-chip cache memory. In many cases, microprocessors include an on-chip hierarchical cache structure that may include a level on...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F12/08
CPCG06F12/0846Y02B60/1225G06F2212/601G06F12/0864Y02D10/00
Inventor DONLEY, GREGGORY D.
Owner GLOBALFOUNDRIES INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com