50 results about "Addressing mode" patented technology

The invention discloses an ALU, a processor, a chip, equipment and a texel index calculation method, and belongs to the technical field of chips. The ALU comprises a first comparator, a first divider, a first summator and a texel adjusting unit. A first comparator to determine a first value, the first value being determined based on a smaller value of the integer portion of the input texture coordinate and the maximum offset; the first divider is used for calculating a ratio between the input offset and the first divisor to obtain a first ratio; the first summator is used for calculating the quotient of the first ratio and the sum of the first numerical value and the second numerical value to obtain a first calculation result; and the texel adjusting unit is used for determining a target texel index corresponding to the input texture coordinate according to at least one of the first calculation result and the addressing mode. According to the method, the first calculation result can be determined based on the smaller value in the two, and the value of the integer part of the input texture coordinate can be reduced within a certain limit, so that the bit width of the calculation unit is reduced.

According to the kernel indirect control flow transfer dynamic verification method based on the eBPF, an eBPF attachment point of an indirect call instruction is positioned, a verification program is dynamically attached, a source address and a target address are captured to generate a compound key, and the legality of a control flow is verified in a pre-constructed BPF hash table; and meanwhile, three indirect addressing modes of a differential strategy adaptive register, an immediate operand and a memory are adopted. Based on an eBPF technology, an EV program can be dynamically loaded into a running kernel as required during running, and the characteristic of dynamic expansion of a modern kernel can be perfectly adapted; all the capabilities are constructed on a universal software mechanism of a Linux kernel and do not depend on any hardware extension; while powerful security defense is provided, extremely low overhead during operation is realized. Benefited from an innovative hybrid verification strategy and an efficient CFG storage scheme, control flow hijacking attacks in the real world can be effectively defended with extremely low performance loss.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

The invention relates to the technical field of electric communication technology, and discloses an automatic distribution method and system for parallel DC power supply module addresses of a transformer substation, a monitor broadcasts an addressing start command through a CAN bus, and all power supply modules enter an addressing mode; starting from the first power supply module, each module is activated according to an addressing line level, sequentially distributes incremental addresses and generates topological feature codes for storage; after the last module completes addressing, the monitor sends an addressing ending command, and all the modules exit the addressing mode; when the module is replaced, the new module generates the current topological feature code according to the current addressing line state and the adjacent module identifier, and the original address is automatically recovered after the pre-stored feature library is matched. The problems that in the prior art, manual code dialing is low in efficiency, the address sequence is disordered, and replacement modules are reset are solved, and the purposes of accurate automatic addressing, intelligent topology recognition and permanent address keeping are achieved.

The present disclosure provides a signal generation circuit, a test circuit, and a memory, relating to the field of semiconductor technology. The signal generation circuit includes a counting circuit, which includes n+1 counting units cascaded in sequence, wherein the first output end of the counting unit of the previous stage is connected to the first input end of the counting unit of the next stage, and the first output end of the counting unit of the n+1 stage is connected to the first input end of the counting unit of the first stage; the counting units of the first to m stages each include a selector, each selector including a first selection signal input end; the counting units of the first to n stages are configured to: based on the selection signals received by the selectors in the counting units of the first to m stages, output a first counting signal with an n-bit step or a second counting signal with an n-bit jump. The counting signal output by the above-mentioned signal generation circuit can be used for various addressing modes such as address ascending addressing or address jump ascending addressing, which can better meet the testing requirements of the memory.

This application discloses a method, apparatus, vehicle equipment, and storage medium for allocating node addresses in a vehicle. The method includes: obtaining a node with a currently assigned address from a node set according to a first addressing mode, wherein the node set includes multiple nodes connected to a first bus of the vehicle; obtaining the address of the node based on the number of addressing instruction frames in the addressing instruction sequence, the address carried in the addressing instruction frame currently issued to the node, and the frame number of the addressing instruction frame currently issued to the node; and allocating an address to the node based on the address of the node. This method allows for precise control over node address allocation, thereby meeting preset requirements.

Disclosed techniques enable vector instruction processing. A processor core is accessed. The processor core is coupled to a memory hierarchy, and is configured to execute vector operations, scalar operations, and micro-operations. A decode unit decodes a vector memory operation. The vector memory operation is associated with a unit stride addressing mode. The decoding includes dividing the vector memory operation into one or more vector memory micro-operations. A dispatch unit sends at least one vector micro-operation within the one or more vector micro-operations to a scalar request queue within a plurality of request queues. The at least one vector micro-operation is issued to a load-store unit within the processor core. The issuing includes selecting, from the plurality of request queues, the at least one vector memory micro-operation.

The application provides a processor-oriented data transfer instruction implementation method and system, and the method comprises the following steps: step S1: a RISC special processor decodes a read memory instruction, and data of a specific length byte is moved from a memory to a plurality of specified registers according to a memory address and a register first address given in the instruction; step S2: the RISC special processor decodes a write memory instruction, and data of a specific length byte is moved from a register to a specified memory address according to a memory address and a register first address given in the instruction. The application realizes fast moving operation of multiple data, has the advantages of flexible addressing mode, and thus improves the operation efficiency of the multiple data transfer instruction, which is beneficial to the multiple data moving operation in the application of the special processor, especially in the field of network processor, and the instruction greatly improves the operation efficiency of the special processor.

The application discloses a software and hardware cooperative memory access operation optimization method and device, equipment and medium, and relates to the technical field of computers. The method comprises the following steps: traversing the operation type of a target memory reading operation corresponding to a current memory reading operation code in target code; if the operation type is a non-direct addressing mode, a cache query instruction is executed to replace the target memory reading operation; if the operation type is a direct addressing mode, a reuse distance corresponding to the current memory reading operation code is calculated, and it is determined whether the reuse distance is greater than a preset distance threshold; if the reuse distance is greater than the preset distance threshold, a preset direct memory access instruction is executed to replace the target memory reading operation; if the reuse distance is not greater than the preset distance threshold, a target cache instruction is executed to replace the target memory reading operation; and code traversal is continued until all memory reading operation codes in the target code are traversed. Thus, the cache pollution can be reduced by combining the software and hardware memory access instruction optimization method.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

The present disclosure relates to an instruction execution method and device and a processor, comprising: identifying whether an instruction to be executed comprises an extended instruction prefix; if yes, extracting a first field for mapping an operation code of the instruction to be executed from the instruction to be executed; judging whether a second field related to a variable length vector register and a third field related to a variable length mask register are extracted from the instruction to be executed according to the first field; if yes, executing the instruction to be executed according to the first field, the second field, the third field, an operation code comprised by the instruction to be executed and an addressing mode field; if not, executing the instruction to be executed according to the first field, the operation code and the addressing mode field. Thus, the portability of software can be improved and the x86 instruction can be easily extended.

The invention relates to a processor architecture realized based on an RISC-V decoupling vector access unit. The processor architecture comprises a decoding unit, a storage unit, a vector access unit, a scalar access unit, an execution management unit and a front-end fetch unit. In the processor architecture, a decoupling vector memory access unit design is adopted, a memory access instruction is split into a plurality of memory access sub-requests according to an addressing mode of the vector memory access instruction, and memory access paths of normal and abnormal vector instructions are distinguished, so that the time sequence risk of the vector memory access unit is reduced; the memory access sub-request is sent to the scalar memory access unit to access the storage unit, so that the coupling degree of the vector and the scalar memory access unit is reduced, the existing scalar memory access path is reused, and the management difficulty of storage consistency is reduced.

The present application is entitled "System and Method for Addressing Data in Memory". A digital signal processor 100 having a CPU (110) with a program counter register (121) and optionally an event context stack pointer register (122) for saving and restoring event handler context when a higher priority event preempts a lower priority event handler is disclosed. The CPU (110) is configured to use a minimized set of addressing modes, including using the event context stack pointer register (122) and the program counter register (121) to calculate addresses for storing data in memory (112, 114). The CPU (110) can also eliminate post-decrement addressing, pre-increment addressing, and post-decrement addressing, and rely only on post-increment addressing.

The invention provides an automatic addressing method and device based on an RS-485 bus, equipment and a medium. The method comprises the following steps: receiving a broadcast addressing instruction sent by a main station; the broadcast addressing instruction comprises a control command for setting an addressing register of the slave station to be 1; the slave station is in cascade connection with the master station through an RS-485 bus; performing a setting operation on an addressing register of the slave station based on the broadcast addressing instruction, and sending an automatic addressing instruction; and in response to the automatic addressing instruction, the slave station executes automatic addressing based on an addressing instruction data frame sent by the master station. According to the method, the register of the slave station is automatically set in a mode of supporting RS-485 broadcast, the addressing mode is automatic addressing, addressing of a plurality of slave station RS-485 bus systems can be effectively carried out, dependence on manual node-by-node operation is eliminated, system scale changes can be dynamically adapted, the automatic system deployment efficiency is relatively high, time and labor are saved in the implementation process, and the implementation efficiency is improved. And the labor cost and the debugging time are greatly saved.

A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.

An embodiment of the present invention provides a processing-in-memory memory device comprising: a memory bank including a memory array for receiving a memory request from a memory controller, and a PIM engine for executing processing-in-memory according to the PIM instruction; and a processing-in-memory (PIM) control unit for controlling the processing-in-memory of the PIM engine by identifying a PIM instruction corresponding to the memory request, and storing addressing mode selection information for selecting one among an indirect address and a direct address according to the identified PIM instruction, wherein when the indirect address is used, the PIM control unit uses a register value of the processing-in-memory control unit as a base register value, reads an immediate value in the PIM instruction, a register value of the PIM engine, or an offset value of the memory bank, and generates an effective address for the processing-in-memory in an indirect addressing mode.

The invention relates to an instruction execution method and device and a processor. The method comprises the steps that whether a to-be-executed instruction comprises an extension instruction prefix or not is recognized; if yes, extracting a first field used for marking operation code mapping of a to-be-executed instruction from the to-be-executed instruction; judging whether a second field related to a variable-length vector register and a third field related to a variable-length mask register are extracted from the to-be-executed instruction or not according to the first field; if the second field and the third field are extracted from the to-be-executed instruction, executing the to-be-executed instruction according to the first field, the second field, the third field and an operation code and an addressing mode field included in the to-be-executed instruction; and if the second field and the third field are not extracted from the instruction to be executed, executing the instruction to be executed according to the first field, the operation code and the addressing mode field. Therefore, the portability of software can be improved, and the x86 instruction can be easily expanded.

The application discloses a RISC-V style 8-bit reduced instruction set customization method, comprising the following steps: S1, based on the function and demand of the target application scene, a target instruction set is selected from a RISC-V32I instruction set, the data bit width, PC width, memory space and register group size of the processor are selected; S2, according to the interruption and exception types supported by the instruction set, the processing flow of the interruption and exception is determined; S3, the encoding space is reduced and the register grouping is optimized through a register coding multiplexing strategy, and the customization of the register addressing mode of the instruction set is realized; S4, each instruction is classified according to the instruction format; S5, each instruction is coded based on the format of each instruction. The customization method has a simple and efficient process, is easy to implement and deploy, does not need to be designed from zero, significantly shortens the research and development cycle, can adapt to multiple scene demands, and realizes the miniaturization of the instruction set, minimization of hardware resources and efficient design process.

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

Memory blocks often consume many switch box resources. For example, an 8-bit memory using 8-bit addressing uses at least eight address lines, eight data lines, a write-enable line, and a read-enable line. Using an auto address mode, the address and data are multiplexed on the same lines. The initial address and a stride are provided before the writing process begins. Between writes, the address is incremented by the stride. Thus, the memory block is able to determine the address for the next write based on the starting address and the stride, and does not need to receive the new address on the address lines. The auto address mode may be implemented by including a logic block within the memory block. The logic block may be programmed for purposes other than an auto address mode.

The invention discloses a host working mode determination method and device, a program product and a storage medium, applied to a host, the working mode of the host being configured as an addressing mode or a non-addressing mode, the method comprising: sending a first instruction to N nodes included in P loops to detect address registration states of the N nodes; determining M first nodes from the N nodes based on the address registration states of the N nodes; and determining a target working mode of the host based on the M first nodes. Through application of the method and the device, the problem that the working mode actually required to be used by the host supporting both the addressing mode and the non-addressing mode cannot be determined in related technologies is solved; therefore, the effect of determining the working mode which is actually required to be used by the host which supports both the addressing mode and the non-addressing mode can be achieved.

The present application discloses a register addressing method, device, electronic device and storage medium, which relate to the field of server technology, including: after receiving the starting address data sent by the master device, the slave device first determines in which address mode the starting address data is transmitted based on the starting address data, that is, determines the target address mode. Then, when it is determined based on the target address mode that the device address data corresponding to the target address mode is received, the target address can be extracted from the device address data based on the target address mode. Furthermore, when it is determined that the target address is consistent with the slave device address, it means that the slave device addressing is correct. When a register address matching the target address mode is received, subsequent operations can be performed on the function register corresponding to the register address addressing. By analyzing the starting address data and determining the target address mode, the slave device can flexibly switch the address mode, which is more convenient.

The invention provides a chip, method and device for matrix multiplication and a storage medium, and the chip comprises a first addressing module which is used for obtaining a preset format parameter and a mapping table; the first addressing module is also used for taking the mapping data matched with the preset format parameters as target mapping data; taking candidate addressing mode parameters in the target mapping data as target addressing mode parameters; the first addressing module is also used for generating a plurality of first read addresses based on the first target addressing mode and generating a plurality of second read addresses based on the second target addressing mode; reading one first matrix element based on each first read address, and reading one second matrix element based on each second read address; and the calculation module is used for calculating the plurality of first matrix elements and the plurality of second matrix elements based on the preset format parameters to obtain a target matrix. According to the technical scheme, the hardware structure is simplified, and the development efficiency of hardware is improved.

The present disclosure provides a signal generating circuit, a test circuit and a memory, and relates to the field of semiconductor technology. The signal generating circuit includes a counting circuit and a selection circuit; the counting circuit includes n counting signal output terminals; the selection circuit includes a selection signal input terminal, n first receiving terminals corresponding to binary bits, and n second receiving terminals; each first receiving terminal is connected to the counting signal output terminal located at the same binary bit; in order from low to high bits, the first m second receiving terminals are connected to the last m counting signal output terminals, and each remaining second receiving terminal is connected to the counting signal output terminal m bits lower than itself, m<n; the selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output a target signal, and the target signal can be used for multiple addressing modes such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing, etc., which can better meet the testing requirements of the memory.

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

The application discloses an ALU, a processor, a chip, a device and a texel index calculation method, and belongs to the chip technical field.The ALU comprises a first comparator, a first divider, a first adder and a texel adjustment unit.The first comparator is used for determining a first value, and the first value is determined based on the smaller one of the integer part of an input texture coordinate and a maximum offset.The first divider is used for calculating the ratio between an input offset and a first divisor to obtain a first ratio.The first adder is used for calculating the sum of the quotient of the first ratio, the first value and a second value to obtain a first calculation result.The texel adjustment unit is used for determining the target texel index corresponding to the input texture coordinate according to at least one of the first calculation result and an addressing mode.The first calculation result can be determined based on the smaller one of the two, and the value of the integer part of the input texture coordinate can be reduced within a certain limit, so that the bit width of the calculation unit is reduced.

This invention discloses an addressable test circuit and test method with multiple addressing modes, wherein: the addressing circuit connects to and controls the switching circuit, and the switching circuit connects to each unit under test in the DUT array; the addressing circuit includes an address input terminal, a decoding output terminal, and an enable control terminal, and the enable control terminal receives a prefix enable signal; the addressing circuit is configured to switch between the following two modes according to the state of the prefix enable signal: Prefix gating mode: when the prefix enable signal is at a first logic level, the decoding output terminal simultaneously generates gating signals for multiple units under test to select all units under test whose addresses are less than or equal to the input address; Precise addressing mode: when the prefix enable signal is at a second logic level, the decoding output terminal outputs only a single gating signal corresponding to the input address to select the corresponding unit under test.

A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

The invention discloses a fast routing lookup circuit which comprises a read-write control module, a mode control module, an input driving module, an output buffer and a storage and calculation integrated calculation array. The storage and calculation integrated calculation array is respectively connected with the read-write control module, the mode control module, the input driving module and the output buffer; the storage and calculation integrated processing unit is used for realizing storage and XOR operation; the read-write control module is used for reading or writing storage array information; the mode control module is used for controlling a content addressing mode; the input driving module is used for controlling the input of input routing data; and the output buffer is used for transmitting the route retrieval result. According to the invention, the problem of power consumption caused by large-scale parallel activation circuits is solved on the premise of keeping high-speed operation and storage density.