3 results about "Addressing mode" patented technology

A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

This invention discloses an addressable test circuit and test method with multiple addressing modes, wherein: the addressing circuit connects to and controls the switching circuit, and the switching circuit connects to each unit under test in the DUT array; the addressing circuit includes an address input terminal, a decoding output terminal, and an enable control terminal, and the enable control terminal receives a prefix enable signal; the addressing circuit is configured to switch between the following two modes according to the state of the prefix enable signal: Prefix gating mode: when the prefix enable signal is at a first logic level, the decoding output terminal simultaneously generates gating signals for multiple units under test to select all units under test whose addresses are less than or equal to the input address; Precise addressing mode: when the prefix enable signal is at a second logic level, the decoding output terminal outputs only a single gating signal corresponding to the input address to select the corresponding unit under test.

Memory blocks often consume many switch box resources. An 8-bit memory using 8-bit addressing uses at least eight address lines, eight data lines, a write-enable line, and a read-enable line. Using an auto address mode, the address and data are multiplexed on the same lines. The initial address and a stride are provided before the writing process begins. Between writes, the address is incremented by the stride. Thus, the memory block is able to determine the address for the next write based on the starting address and the stride, and does not need to receive the new address on the address lines. The auto address mode may be implemented by including a logic block within the memory block. The logic block may be programmed for purposes other than an auto address mode.