258 results about "Memory operation" patented technology

The invention discloses a compatible operation method for an Android camera HAL in a container based on memory access virtualization, and the method comprises the steps: taking a DMA-Buf memory heap of a Linux kernel host system as a target memory heap, taking an ION memory heap of an Android container system as a source memory heap, building a process exclusive memory management context, an FD cache table and a synchronous fence pool, and carrying out the execution of the process exclusive memory management context, the FD cache table and the synchronous fence pool; kernel registration and node binding of virtual ION equipment, pre-allocation of a first memory pool and access hook registration of kernel layer equipment are completed, and when an ION file descriptor is obtained in an HAL process, legality of a container process is verified, and context binding is initialized to the file descriptor; intercepting a memory allocation request of the HAL process, analyzing and adapting parameters, and preferentially multiplexing first memory pool resources to obtain an ION handle; when a data sharing request is processed, matching an FD cache or generating a new FD through an ION handle; when the HAL process releases the memory, resources are recycled according to a memory source, and when the HAL process exits, the context is cached or destroyed, so that cross-system memory operation compatibility is realized.

The invention provides an advanced memory performance monitoring and anomaly detection method, system and device, and relates to the technical field of memory monitoring, and the method comprises the steps: capturing a current memory operation executed by a monitored kernel and corresponding operation data through a memory delay monitoring module based on a kernel tracking point mechanism, the memory delay alarm module is used for judging whether memory delay alarm is performed for a monitored kernel; under the condition that the judgment result is yes, constructing a memory delay diagnosis event corresponding to the monitored kernel based on the operation data through a diagnosis event generation module; and through a diagnosis event distribution module, the memory delay diagnosis event is added to the to-be-processed diagnosis event queue, so that the memory diagnosis framework processes the memory delay diagnosis event contained in the to-be-processed diagnosis event queue, and a performance monitoring and anomaly detection result corresponding to the monitored kernel is obtained. According to the method, the monitoring fine granularity can be remarkably improved, and the false alarm and missing alarm conditions in the performance monitoring and abnormity monitoring process are reduced.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

Methods, systems, and apparatuses include receiving, by a memory subsystem, a read command from a host device to read data from a memory portion of the memory subsystem. It is determined that the memory portion includes a partial block. A memory bin is determined for the memory portion in response to determining that the memory portion includes the partial block. A position is determined for the memory portion. A voltage offset is applied to a read voltage for the memory portion using the memory bin and the position.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

Embodiments of the present invention provide a memory operation method, a memory, an electronic device, and a storage medium. The memory operation method comprises: in response to detecting an error in a storage array of a memory during a working state of the memory, determining an error location of the error in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-package repair process, and on the basis of the error location, performing replacement of a target storage cell at the error location with a replacement storage cell in the storage array used for the post-package repair process; and after the post-package repair process, switching the memory back to the working state, and using the replacement storage cell to replace the target storage cell for operation. The memory operation method can improve the reliability of the memory.

The present disclosure provides an execution method of an atomic memory operation and a multi-core processor. The method comprises: a first node interacts with a master node to execute the atomic memory operation, wherein the first data is generated after the execution of the atomic memory operation; the first node sends a unique permission read request to the master node; the first node receives the first data returned by the master node in response to the unique permission read request; and the first node stores the first data in the cache of the first node.

The invention discloses an operation method of a memory, the memory and a memory system, and belongs to the technical field of storage. According to the method, in the process of recovering the erasing operation of the storage block, if the erasing operation is in an erasing pulse stage, the voltage of a specific word line connected with the storage block is released in advance in response to the situation that the pause frequency of the erasing operation in the erasing pulse stage is greater than or equal to a threshold value, so that the voltage of the specific word line can enter a floating state in advance; furthermore, the voltage of the specific word line can be increased along with the increase of the ACS (and / or BL) voltage in advance, and the voltage difference between the specific word line and the ACS (and / or BL) in the current recovery erasure operation process is reduced, so that the voltage difference is prevented from exceeding the threshold voltage of the specific unit, the weak erasure of the specific unit in the current recovery erasure operation process can be avoided, and the recovery erasure efficiency of the specific unit is improved. And the frequency of weak erasure of the specific unit in the erasure operation process is reduced, so that the reliability and the performance of the memory can be improved.

A management technique for high bandwidth memory is disclosed. A processing management circuit (PMC) has a main executing circuit and a main memory and is configured to manage at least one processor operation performed by at least one of a first processing element (PE) or a second PE. A shared memory is configured to be shared by the PMC, the first PE, and the second PE. A memory management circuit (MMC) is configured to manage a memory operation on the shared memory based on a memory access by at least one of the PMC, the first PE, or the second PE. The at least one processor operation includes at least one of a program launch, a program execution, and an interrupt delivery.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

In some implementations, a memory apparatus may transmit, to a host system, capability information indicating one or more supported memory operations of the memory apparatus. The memory apparatus may receive, from the host system, configuration information indicating one or more performance limits for at least one supported memory operation of the one or more supported memory operations.

Systems and techniques include identifying a network layer for performing a memory operation, identifying a subset of a plurality of configuration bit clusters of a non-volatile distributed memory that are mapped to the identified network layer using a cluster mapping, in response to identifying the subset of the plurality of configuration bit clusters, activating the subset of the plurality of configuration bit clusters, loading network component data from the subset of the plurality of configuration bit clusters into a local buffer, and applying the network component data to the network layer for performing the memory operation.

Methods, apparatus, systems, and articles of manufacture are disclosed for improving data transfer for heterogeneous programs. An example apparatus includes instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to determine a runtime associated with executing a code object by a heterogeneous electronic device based on at least one of a location of a memory object or a data transfer penalty, the data transfer penalty associated with access of the memory object in response to execution of the code object, identify a memory operation for the memory object based on the runtime, and generate an executable file based on the memory operation, the executable file, when executed, to cause execution of the code object by at least one of first hardware or second hardware of the heterogeneous electronic device based on the memory operation.

A memory, a memory operation method, and a storage device are provided. The memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition. In this way, an on-die ECC may be employed to pre-identify an error occurring in the memory, and after an error uncorrectable by the on-die ECC is identified, an error checking signal is generated to record error address information in a timely manner, thereby facilitating subsequent correction of the error and improving accuracy of the memory.

The application provides a memory operation method and a memory chip. The method comprises the following steps: obtaining an operation depth; wherein the operation depth is determined in wafer testing and stored in a storage unit; the operation depth represents a threshold voltage change level of the storage unit after operation; when the operation is performed, the operation depth is used for depth checking until the operation depth is reached. The application can accurately test the operation depth of the memory chip, and then guide the actual operation by using the operation depth, so as to achieve the purpose of accurately controlling the operation effect, and the problem that the threshold voltage of the storage unit becomes complex and uncontrollable can be avoided.

The application discloses an operating method of a memory, a memory and a memory system. When a reset operation is performed on a target storage unit in a plurality of storage units, a first voltage sequentially increasing in value is applied to a target word line coupled with the target storage unit in a first stage of the reset operation, and a second voltage is applied to a target bit line coupled with the target storage unit, then a second stage of the reset operation is performed after the first stage, a third voltage is applied to the target word line, and a fourth voltage is applied to the target bit line, wherein the voltage value of the third voltage is greater than or equal to the voltage value of the first voltage, and the voltage value of the fourth voltage is greater than the voltage value of the second voltage, so that the voltage difference between the two ends of the storage unit is greatly reduced in the reset operation, the "surge" current introduced by the voltage mutation is effectively reduced, and the reliability of the memory device is improved.

The invention provides an operation method of a memory, the memory and a memory system, and is applied to the technical field of semiconductors. The operation method of the memory comprises the following steps: acquiring a current environment temperature; the current environment temperature is used for indicating the temperature of the current environment of the memory. And receiving to-be-stored data, and when the current environment temperature belongs to the first temperature range, writing the to-be-stored data into the first storage area. And when the current environment temperature belongs to the second temperature range, writing the to-be-stored data into the second storage area. According to the embodiment, the accuracy and reliability of data reading under different temperature conditions are improved.

The application provides an image processing method, device and electronic equipment, the method comprising: dividing a to-be-processed image into a plurality of sub-blocks; processing the plurality of sub-blocks using a plurality of CUDA (Compute Unified Device Architecture) streams, each CUDA stream in the plurality of CUDA streams comprising: a calculation operation and a memory operation, and a sub-block in the plurality of sub-blocks being processed asynchronously between the calculation operation in a first CUDA stream and the memory operation in a second CUDA stream; and splicing and fusing the processing results of the plurality of sub-blocks to obtain a processing result of the to-be-processed image. In the implementation process of the above scheme, the multi-core resources of the GPU are fully utilized through the asynchronous processing between the calculation operation and the memory operation in different CUDA streams, the idle time of the processing unit is reduced, the resource utilization rate of the CUDA stream is maximized, and therefore the overall processing efficiency of the high-resolution image is improved.

Embodiments of the present application provide a memory operation method, a memory and a storage system. The memory comprises a plurality of storage surfaces and a peripheral circuit coupled with the storage surfaces. The peripheral circuit comprises a buffer device coupled between a first storage surface and a second storage surface. The buffer device is configured to read first data from the first storage surface and transmit the first data to the second storage surface, or read second data from the second storage surface and transmit the second data to the first storage surface. The first storage surface and the second storage surface are any two storage surfaces of the plurality of storage surfaces.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a column selection control circuit that combines outputs of the state machine and the set of registers to trigger an appropriate column during an appropriate clock cycle, available at a start of a corresponding clock cycle. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

Aspects of the present disclosure configure a system component, such as memory sub-system controller, to detect read errors in one or more memory cells using a plurality of read thresholds. The controller selects, for inspection, a target valley of a plurality of valleys associated with an individual memory component of the set of memory components. The controller reads the target valley using a first read threshold to obtain a first set of data and reads the target valley using a second read threshold to obtain a second set of data. The controller compares the first set of data to the second set of data and performs one or more memory operations on the target valley in response to comparing the first set of data to the second set of data.

The present disclosure provides a semiconductor device, system, and an operating method thereof. The semiconductor device includes a peripheral circuit and an array of memory cells. The array of memory cells is coupled to the peripheral circuit, and includes a storage zone and a compute-in-memory zone. The compute-in-memory zone includes a plurality of memory banks, the storage zone and any one of the memory banks includes a plurality of memory blocks. The plurality of memory banks are configured to perform a compute-in-memory operation. The plurality of memory blocks in the storage zone are configured to perform a memory operation.

Disclosed embodiments provide techniques for improved performance in processing vector instructions. A processor core is accessed. The processor core is coupled to a memory hierarchy, and the processor core includes one or more vector execution units (VUs), and one or more load store units (LSUs). The processor core includes a vector register file (VRF). The VRF includes multiple vector registers, and each vector register includes multiple vector elements. Vector elements that have a source or destination in contiguous memory are identified. Load store units (LSUs) take advantage of the contiguous memory condition by executing a vector load or vector store operation as a single memory access, requiring a reduced number of clock cycles. The single memory access satisfies each memory operation for each vector element within the vector register file.

The embodiment of the application discloses a kind of method and device for monitoring memory bandwidth, it is related to computer field.The method comprises: the memory bandwidth size that process group is accessed volatile memory is used in the preset period is obtained by processor core, and after the memory operation that process group executes in the preset period is counted, the memory bandwidth size that process group is accessed non-volatile memory is used is calculated according to memory bandwidth size and the memory operation of counting.It is realized to monitor the memory bandwidth of non-volatile memory with process group as granularity, and then the memory bandwidth size of non-volatile memory is used as the basis for limiting the memory bandwidth of non-volatile memory.

This application is directed to managing memory operations in a memory system or device (e.g., a solid-state drive (SSD)). While implementing one or more write operations on one or more active memory dies, the memory device identifies a first read request for data stored on a first memory die. The first read request is waiting next in a queue of read requests. In accordance with a determination (1) that the first memory die is distinct from the one or more active memory dies and (2) that no sufficient power is available to implement the first read request concurrently with the one or more write operations, the memory device suspends the one or more write operations according to a suspension scheme and implements the first read operation on the first memory die.

In some implementations, a memory apparatus may transmit, to a host system, capability information indicating one or more supported memory operations of the memory apparatus. The memory apparatus may receive, from the host system, configuration information indicating one or more current limits for at least one supported memory operation of the one or more supported memory operations.

The invention discloses a running-state-oriented memory fault risk assessment and adaptive diagnosis method and system, and relates to the technical field of memory running management.The method comprises the steps that S1, running-state memory monitoring data are collected and preprocessed; s2, generating a cross-layer difference triple set, performing difference direction judgment on a cross-layer difference triple, and identifying cross-layer inconsistent fragments; s3, constructing a cross-layer risk index set, performing cross-layer fault risk quantitative analysis on each inconsistent fragment, performing risk grade division based on a quantitative analysis result, and generating a corresponding risk grade label; and S4, carrying out risk response operation on the inconsistent fragments, carrying out response stability evaluation, and generating a final risk response result set. The problem that in the prior art, cross-layer difference sources cannot be accurately recognized in a multi-layer memory access link, so that running state fault risk judgment is prone to being interfered by access jitter and affected by virtualization scheduling offset is solved.

During execution of software a processing unit issues asynchronous operations such that there are multiple asynchronous operations, such as memory operations, in flight (that is, pending execution completion) from a single set of instructions, such as a wavefront or warp. In some cases, the processing unit executes other operations while the multiple asynchronous operations are pending. Performance monitor circuitry records information, such as asynchronous operation count information, register file scoreboard information, and the like, that allows a software engineer to identify which of a plurality of asynchronous operations caused a stall.

The present disclosure provides a memory operation method, a memory and a storage system, and relates to the technical field of memories. The method comprises the following steps: in a process of performing a target operation on a memory, obtaining a current temperature and a historical temperature of the memory, the target operation comprising at least one of an erase operation, a programming operation and a reading operation; determining whether a temperature variation of the memory is greater than a preset temperature threshold according to the current temperature and the historical temperature; in response to determining that the temperature variation of the memory is greater than the preset temperature threshold, determining whether a data transmission channel of the memory is currently idle; and in response to determining that the data transmission channel of the memory is currently idle, performing a first interface impedance calibration operation on the memory according to the current temperature. The method realizes interface impedance calibration when the data transmission channel is idle in the process of performing the target operation on the memory.

The invention discloses an anomaly detection method, which is applied to an anomaly detection system, and comprises the following steps: obtaining operation information of memory operation of an AI framework in an AI model running process from a host of a computing server, and obtaining operation information of memory operation of at least one heterogeneous operator from acceleration equipment of the computing server, recording a mapping relationship between the framework API of the AI framework and the at least one heterogeneous operator, executing anomaly detection for the heterogeneous operator according to the operation information of the memory operation of the AI framework and the operation information of the memory operation of the at least one heterogeneous operator, obtaining an anomaly detection result, and when it is indicated that an anomaly is detected, executing the anomaly detection for the heterogeneous operator. And determining an abnormal API according to a mapping relationship between the framework API of the AI framework and the at least one heterogeneous operator. According to the method, the operation information of the memory operation of the AI framework and the heterogeneous operator is cooperated, the missing information at the operator side is supplemented, comprehensive anomaly detection is performed based on the supplemented information, the anomaly can be positioned and repaired without the cooperation of experts in multiple fields, and the detection efficiency is improved.