673 results about "Memory operation" patented technology

A system and method for implementing a convergent intelligence fabric (CIF) for distributed artificial intelligence operations. The CIF architecture integrates tensor-theoretic foundations, probabilistic cache management, precision-aware memory operations, quantum-resistant security, and neural-based optimization within a unified framework. The system orchestrates asynchronous, multi-hop data flow among computational resources while maintaining data security through per-block encryption and identity-based access control. Key components include a universal multi-model KV cache subsystem, agent-parallel disaggregation pipelines, reinforcement learning-based orchestration, and neuromorphic memory integration. Advanced implementations incorporate graphon-enhanced memory for sparse graph sequences, multi-modal cognitive persistent memory, and quantum-resistant asynchronous multi-domain trust protocols. The system enables efficient cross-agent collaboration, sophisticated knowledge sharing, and secure cross-domain operations while optimizing computational resources and maintaining strict privacy guarantees across distributed AI deployments.

The invention discloses a compatible operation method for an Android camera HAL in a container based on memory access virtualization, and the method comprises the steps: taking a DMA-Buf memory heap of a Linux kernel host system as a target memory heap, taking an ION memory heap of an Android container system as a source memory heap, building a process exclusive memory management context, an FD cache table and a synchronous fence pool, and carrying out the execution of the process exclusive memory management context, the FD cache table and the synchronous fence pool; kernel registration and node binding of virtual ION equipment, pre-allocation of a first memory pool and access hook registration of kernel layer equipment are completed, and when an ION file descriptor is obtained in an HAL process, legality of a container process is verified, and context binding is initialized to the file descriptor; intercepting a memory allocation request of the HAL process, analyzing and adapting parameters, and preferentially multiplexing first memory pool resources to obtain an ION handle; when a data sharing request is processed, matching an FD cache or generating a new FD through an ION handle; when the HAL process releases the memory, resources are recycled according to a memory source, and when the HAL process exits, the context is cached or destroyed, so that cross-system memory operation compatibility is realized.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

The invention relates to the technical field of GPUs, in particular to a GPU virtualization video memory management method and device, a storage medium and a program product. The method comprises the steps that a virtual machine transmits a page table root address corresponding to a target application program running in the virtual machine to a host machine; the virtual machine calls the non-memory operation type API in response to the target application program, intercepts calling of the non-memory operation type API and forwards the calling to the host machine; and in the host machine, accessing a video memory area corresponding to a target application program based on the page table root address through the drive of the non-memory operation type API, executing an instruction of the non-memory operation type API, and returning a processing result of the instruction of the non-memory operation type API to the virtual machine. According to the method and the device, the rear-end driver in the host machine can directly access the video memory resources allocated by the virtual machine, so that the resource utilization rate and the task execution efficiency are improved.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

The invention discloses an anomaly detection method and device, electronic equipment and a computer program product. The method comprises the steps that operation information generated by executing a memory operation instruction is collected through a monitoring hook inserted into a webpage assembly language module in advance, the webpage assembly language module is an executable unit written by using a webpage assembly language byte code, and the webpage assembly language byte code at least carries the memory operation instruction; and performing anomaly detection on the operation information by using a preset anomaly detection condition. According to the method and the device, the technical problem of poor accuracy of performing anomaly detection on the WASM module in the prior art is solved.

The invention relates to an automatic memory protection method and device, computer equipment and a storage medium, and the automatic memory protection method comprises the steps: responding to a real-time memory read-write instruction, and determining a target memory address corresponding to the memory read-write instruction; determining a pre-stored tag value corresponding to the target memory address and an actual tag value currently embedded in a memory block pointed by the target memory address; and when it is detected that the pre-stored tag value is not matched with the actual tag value, stopping a memory operation associated with the memory read-write instruction. Through the method and the device, the problem that the data-oriented attack cannot be effectively prevented is solved, the data-oriented attack is effectively prevented, and the memory security and the system operation efficiency are improved.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

The invention relates to the technical field of embedded systems, in particular to a memory management method for dynamic allocation of an operating system and a storage medium, and dynamic memory management is realized by transforming a memory allocation interface and an operation interface of the operating system. A memory applicant adds a flag bit when initiating a demand application, an operating system executes allocation operation according to the flag bit, when the flag bit indicates that the demand is determined, allocation is performed according to a specified length, and when the flag bit indicates that the demand is not determined, a fixed-length memory block is allocated firstly. And when the memory operation is executed, detecting the idle state of the subsequent memory block according to the memory head flag bit, and expanding the original memory block or redistributing and copying data. According to the method, the memory waste can be remarkably reduced, the memory use efficiency under resource-limited scenes such as an embedded scene and the like is improved, the system flexibility is enhanced through configuration file adjustment and a flag bit strategy while stable operation of a program is guaranteed, and memory management and maintenance are facilitated in combination with detailed memory information records.

Techniques for an on-memory die voltage regulator is disclosed. In the illustrative embodiment, a voltage regulator on a memory die is enabled upon receipt of a memory operation. The illustrative voltage regulator includes an analog controller that controls a shunt current based on a current output voltage of the voltage regulator. The illustrative voltage regulator also includes a digital controller that controls several switches based on the input voltage that control an effective resistance of part of the voltage regulator.

The invention relates to a progressive memory delay monitoring and diagnosis method oriented to a virtual memory subsystem. The method comprises the following steps: mounting a BPF program to a plurality of key event points on a kernel; when the key event point is triggered, acquiring state information of a corresponding event; packaging the state information into an event, and writing the event into a perf ring buffer associated with the outputmap; and the user mode program asynchronously reads the packaged event from the perf ring buffer, performs classification and aggregation according to the process and the event type, generates a delay terminal log and a histogram, and outputs a diagnosis result. Through systematic architecture design, the state keeping capability and the kernel context access capability of the eBPF are combined with an event model of a virtual memory subsystem, and a set of closed-loop monitoring system oriented to a diagnosis target is constructed. High-precision and high-reliability memory operation delay measurement is realized.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

A storage device includes a memory device including a first memory region configured to store autonomous driving analysis data and a controller configured to control a memory operation of the memory device, wherein the controller includes a management circuit configured to monitor a plurality of pieces of target information related to autonomous driving, predict a shortage of the first memory region, and perform an operation to increase a free space of the first memory region based on a result of the prediction.

A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

The invention provides an advanced memory performance monitoring and anomaly detection method, system and device, and relates to the technical field of memory monitoring, and the method comprises the steps: capturing a current memory operation executed by a monitored kernel and corresponding operation data through a memory delay monitoring module based on a kernel tracking point mechanism, the memory delay alarm module is used for judging whether memory delay alarm is performed for a monitored kernel; under the condition that the judgment result is yes, constructing a memory delay diagnosis event corresponding to the monitored kernel based on the operation data through a diagnosis event generation module; and through a diagnosis event distribution module, the memory delay diagnosis event is added to the to-be-processed diagnosis event queue, so that the memory diagnosis framework processes the memory delay diagnosis event contained in the to-be-processed diagnosis event queue, and a performance monitoring and anomaly detection result corresponding to the monitored kernel is obtained. According to the method, the monitoring fine granularity can be remarkably improved, and the false alarm and missing alarm conditions in the performance monitoring and abnormity monitoring process are reduced.

The embodiment of the invention provides a memory optimization method and device, electronic equipment and a storage medium. After a target program runs, memory running information is obtained; according to the memory operation information, a memory load level is obtained, and the memory load level represents the memory load level of the memory demand of the target program; according to the memory load level, a target optimization strategy is executed, the target optimization strategy comprises at least two conditional execution sub-optimization strategies, the sub-optimization strategies are used for releasing cache data of the corresponding type in the memory, and execution conditions of the sub-optimization strategies correspond to the memory load level. By judging the memory load level for the memory demand of the target program and executing the target optimization strategy based on the memory load level, dynamic type memory recovery based on the memory load level is realized, the problems of slow program loading speed, program lagging and the like caused by excessive memory recovery and untimely memory recovery are avoided, and the memory recovery efficiency is improved. And the use experience of the application program is improved.

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

The invention relates to a clock transfer circuitry for a multi-chip RAM. Apparatus and methods include a first memory chip including a first memory bank, a command input configured to receive a command and a chip identifier, and a decoder configured to determine whether the command is to use a clock on a second memory chip when the command matches a predetermined condition. The apparatus and method also include a second memory chip including a second memory bank and a clock receiver configured to receive the clock from the first memory chip for memory operations on the second memory chip. The first memory chip acts as a base chip for a memory chip stack including the first memory chip and the second memory chip. When the command matches the predetermined condition, the first memory chip is configured to send the chip identifier to the second memory chip to the clock receiver to activate the clock receiver prior to transmitting the command to the second memory chip.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

Dynamic memory operations are described herein. According to the techniques, a system includes a stacked memory and one or more memory monitors configured to monitor a condition of the stacked memory. The system manager is configured to receive a monitored condition of the stacked memory from the one or more memory monitors and dynamically adjust operation of the stacked memory based on the monitored condition. In one or more embodiments, a system includes a memory and at least one register configured to store a ranking of each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of a respective portion in the memory. The memory controller is configured to dynamically refresh portions in the memory at different times based on a ranking of each of a plurality of portions of the memory stored in the at least one register.

The invention discloses a method and device for accessing hardware equipment to a model reasoning acceleration framework and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: setting a bidirectional decoupling middle layer between target hardware equipment and the model reasoning acceleration framework, a unified memory operation interface and a unified kernel function execution interface of different hardware devices are arranged in a middle layer, and kernel functions of the different hardware devices are registered to a model reasoning acceleration framework through the middle layer, so that the kernel functions of the model reasoning acceleration framework are separated from a system during hardware running. Different hardware devices can realize access to the model reasoning acceleration framework through the intermediate layer, and the codes, operators and even model structures of the model reasoning acceleration framework do not need to be adjusted to adapt to different hardware devices, so that the problem of poor universality of the model reasoning acceleration framework in related technologies is solved, and the universality of the model reasoning acceleration framework is improved. The technical effect of improving the universality of the model reasoning acceleration framework is achieved.

A system includes a first network device and a second network device. The first network device is to send over a network a command that specifies a value and instructs that the value be appended to a set of values in a memory. The second network device is to receive the command over the network, and to execute the command by appending the value to the set of values.

The invention discloses a memory and storage equipment, the memory comprises a storage array, an interface module, a decoding circuit and a first-in first-out storage module, the interface module multiplexes command address information and data information in a transmission user instruction; the decoding circuit is connected between the interface module and the first-in first-out storage module; the first-in first-out storage module is arranged between the storage array and the decoding circuit, the storage array executes memory operation based on the current user instruction to be in an occupied state, and the first-in first-out storage module temporarily stores command address information in the analyzed next user instruction in response to the next user instruction received by the interface module; and after the occupation state of the storage array is released, the first-in first-out storage module takes out command address information in the temporarily stored analyzed next user instruction and sends the command address information to the storage array for execution. When the storage array is occupied, the user instruction can still be received continuously, execution of the user instruction cannot be delayed, and high-frequency data transmission is achieved.

Methods, systems, and apparatuses include receiving, by a memory subsystem, a read command from a host device to read data from a memory portion of the memory subsystem. It is determined that the memory portion includes a partial block. A memory bin is determined for the memory portion in response to determining that the memory portion includes the partial block. A position is determined for the memory portion. A voltage offset is applied to a read voltage for the memory portion using the memory bin and the position.

The invention provides a memory operation method and device, equipment, a storage medium and a program product, and the method can comprise the steps that a memory operation request for a memory is obtained, the memory operation request is used for requesting memory allocation or requesting memory release, the memory comprises a plurality of memory blocks, and the memory blocks correspond to at least two memory granularities; determining memory block information corresponding to at least one memory granularity, wherein the memory block information comprises a memory granularity value, a memory block state and memory block use information; and processing the memory operation request according to the memory block information corresponding to the at least one memory granularity so as to allocate or release the memory. And the flexibility of operating the memory is improved.

The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.

Various embodiments include techniques for processing memory operations in a computing system. The computing system includes a central processing unit (CPU) and an auxiliary processor, such as a parallel processing unit (PPU). The PPU can be divided into multiple partitions. Although the partitions are included in a single PPU, the CPU can track the partitions as if the partitions are independent devices rather than different portions of a single device. When two different partitions generate memory operations that access the same memory address in CPU memory address space, the two partitions employ two different data paths. The CPU can use path information for the two different paths to identify which partition generated each memory operation. As a result, the CPU can maintain data consistency and memory coherency in a system where a PPU is divided into multiple partitions.

Provided herein are systems and methods for implementing a field-deployable quantum memory. The quantum memory device includes a device housing configured to be rack-mounted and a quantum memory module disposed within the device housing and configured to perform a memory operation including storing an input qubit and retrieving the stored qubit for output. The quantum memory device may also include a filter module disposed within the device housing and configured to filter an output of the quantum memory module.

Embodiments disclosed herein are directed to a non-volatile storage system comprising a non-volatile memory including non-volatile storage elements and control circuitry. The control circuitry is configured to: perform a first read operation to access device parameter information for a first memory operation associated with a first storage region type, the device parameter information associated with the first storage region type stored in a first block of a plurality of blocks; perform the first memory operation, using the device parameter information associated with the first storage region type; perform a second read operation to access device parameter information for a second memory operation associated with a second storage region type, the device parameter information associated with the second storage region type stored in a second block of the plurality of blocks; and perform the second memory operation, using the device parameter information associated with the second storage region type.