826 results about "Memory operation" patented technology

A system and method for implementing a convergent intelligence fabric (CIF) for distributed artificial intelligence operations. The CIF architecture integrates tensor-theoretic foundations, probabilistic cache management, precision-aware memory operations, quantum-resistant security, and neural-based optimization within a unified framework. The system orchestrates asynchronous, multi-hop data flow among computational resources while maintaining data security through per-block encryption and identity-based access control. Key components include a universal multi-model KV cache subsystem, agent-parallel disaggregation pipelines, reinforcement learning-based orchestration, and neuromorphic memory integration. Advanced implementations incorporate graphon-enhanced memory for sparse graph sequences, multi-modal cognitive persistent memory, and quantum-resistant asynchronous multi-domain trust protocols. The system enables efficient cross-agent collaboration, sophisticated knowledge sharing, and secure cross-domain operations while optimizing computational resources and maintaining strict privacy guarantees across distributed AI deployments.

The invention discloses a compatible operation method for an Android camera HAL in a container based on memory access virtualization, and the method comprises the steps: taking a DMA-Buf memory heap of a Linux kernel host system as a target memory heap, taking an ION memory heap of an Android container system as a source memory heap, building a process exclusive memory management context, an FD cache table and a synchronous fence pool, and carrying out the execution of the process exclusive memory management context, the FD cache table and the synchronous fence pool; kernel registration and node binding of virtual ION equipment, pre-allocation of a first memory pool and access hook registration of kernel layer equipment are completed, and when an ION file descriptor is obtained in an HAL process, legality of a container process is verified, and context binding is initialized to the file descriptor; intercepting a memory allocation request of the HAL process, analyzing and adapting parameters, and preferentially multiplexing first memory pool resources to obtain an ION handle; when a data sharing request is processed, matching an FD cache or generating a new FD through an ION handle; when the HAL process releases the memory, resources are recycled according to a memory source, and when the HAL process exits, the context is cached or destroyed, so that cross-system memory operation compatibility is realized.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

The invention relates to the technical field of GPUs, in particular to a GPU virtualization video memory management method and device, a storage medium and a program product. The method comprises the steps that a virtual machine transmits a page table root address corresponding to a target application program running in the virtual machine to a host machine; the virtual machine calls the non-memory operation type API in response to the target application program, intercepts calling of the non-memory operation type API and forwards the calling to the host machine; and in the host machine, accessing a video memory area corresponding to a target application program based on the page table root address through the drive of the non-memory operation type API, executing an instruction of the non-memory operation type API, and returning a processing result of the instruction of the non-memory operation type API to the virtual machine. According to the method and the device, the rear-end driver in the host machine can directly access the video memory resources allocated by the virtual machine, so that the resource utilization rate and the task execution efficiency are improved.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

The invention discloses an anomaly detection method and device, electronic equipment and a computer program product. The method comprises the steps that operation information generated by executing a memory operation instruction is collected through a monitoring hook inserted into a webpage assembly language module in advance, the webpage assembly language module is an executable unit written by using a webpage assembly language byte code, and the webpage assembly language byte code at least carries the memory operation instruction; and performing anomaly detection on the operation information by using a preset anomaly detection condition. According to the method and the device, the technical problem of poor accuracy of performing anomaly detection on the WASM module in the prior art is solved.

The invention relates to an automatic memory protection method and device, computer equipment and a storage medium, and the automatic memory protection method comprises the steps: responding to a real-time memory read-write instruction, and determining a target memory address corresponding to the memory read-write instruction; determining a pre-stored tag value corresponding to the target memory address and an actual tag value currently embedded in a memory block pointed by the target memory address; and when it is detected that the pre-stored tag value is not matched with the actual tag value, stopping a memory operation associated with the memory read-write instruction. Through the method and the device, the problem that the data-oriented attack cannot be effectively prevented is solved, the data-oriented attack is effectively prevented, and the memory security and the system operation efficiency are improved.

The invention discloses a memory operation method, a memory, electronic equipment and a storage medium. The memory operation method comprises the following steps: in response to an error detected in a memory array of the memory in a working state of the memory, determining an error position of the error in the memory array; after the memory enters the idle state, the memory is controlled to start a post-package repair process, and according to the error position, a target memory unit at the error position is replaced with a replacement memory unit used for the post-package repair process in the memory array; and after the post-package repair process, the memory is switched back to the working state, and the replacement memory unit is used for replacing the target memory unit for operation. The memory operation method can improve the reliability of the memory.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

The invention relates to the technical field of embedded systems, in particular to a memory management method for dynamic allocation of an operating system and a storage medium, and dynamic memory management is realized by transforming a memory allocation interface and an operation interface of the operating system. A memory applicant adds a flag bit when initiating a demand application, an operating system executes allocation operation according to the flag bit, when the flag bit indicates that the demand is determined, allocation is performed according to a specified length, and when the flag bit indicates that the demand is not determined, a fixed-length memory block is allocated firstly. And when the memory operation is executed, detecting the idle state of the subsequent memory block according to the memory head flag bit, and expanding the original memory block or redistributing and copying data. According to the method, the memory waste can be remarkably reduced, the memory use efficiency under resource-limited scenes such as an embedded scene and the like is improved, the system flexibility is enhanced through configuration file adjustment and a flag bit strategy while stable operation of a program is guaranteed, and memory management and maintenance are facilitated in combination with detailed memory information records.

Techniques for an on-memory die voltage regulator is disclosed. In the illustrative embodiment, a voltage regulator on a memory die is enabled upon receipt of a memory operation. The illustrative voltage regulator includes an analog controller that controls a shunt current based on a current output voltage of the voltage regulator. The illustrative voltage regulator also includes a digital controller that controls several switches based on the input voltage that control an effective resistance of part of the voltage regulator.

The invention relates to a progressive memory delay monitoring and diagnosis method oriented to a virtual memory subsystem. The method comprises the following steps: mounting a BPF program to a plurality of key event points on a kernel; when the key event point is triggered, acquiring state information of a corresponding event; packaging the state information into an event, and writing the event into a perf ring buffer associated with the outputmap; and the user mode program asynchronously reads the packaged event from the perf ring buffer, performs classification and aggregation according to the process and the event type, generates a delay terminal log and a histogram, and outputs a diagnosis result. Through systematic architecture design, the state keeping capability and the kernel context access capability of the eBPF are combined with an event model of a virtual memory subsystem, and a set of closed-loop monitoring system oriented to a diagnosis target is constructed. High-precision and high-reliability memory operation delay measurement is realized.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

The invention discloses a storage circuit and a random access memory. The storage circuit comprises a control chip and a storage chip, wherein the storage chip is connected with the control chip; wherein one of the control chip and the storage chip comprises a redundancy repairing module, and the control chip is configured to obtain information of a damaged storage unit in the storage chip according to a preset triggering requirement; the redundancy repair module is configured to store the information of the damaged storage unit and send a redundancy replacement address to the storage chip based on the information of the damaged storage unit in response to the storage operation instruction so as to execute the corresponding storage operation. By means of the mode, the storage circuit can repair the damaged storage unit in the storage chip in real time through the redundancy repair module in the use process of the random access memory, so that the stability of the random access memory is improved, and the possibility that the random access memory reads and writes data mistakenly is reduced.

The invention provides a method adaptive to fast calculation of big data indexes. The method comprises the following steps: synchronizing data needing to be treated into a hive cluster; converting the configuration of the page into an SQL statement through an SQL converter; the atomic indexes, the derived indexes, the composite indexes and the user-defined indexes are converted into SQL statements through an SQL converter; and calculating the index data by using a manner of integrating trino with hive. According to the scheme, the method capable of being adaptive to fast calculation of the big data indexes is provided, the problem that performance is insufficient when an existing index calculation method executes complex index calculation is solved, index calculation efficiency is improved, and the calculation efficiency is improved through step description in the embodiment. Rapid calculation can be achieved in index calculation, and friendly interaction experience is improved. The calculation method completely depends on memory operation, the performance is effectively improved, the problem of large disk I / O consumption caused by shuffle of a hive bottom layer is solved, and server resource consumption is reduced.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

A storage device includes a memory device including a first memory region configured to store autonomous driving analysis data and a controller configured to control a memory operation of the memory device, wherein the controller includes a management circuit configured to monitor a plurality of pieces of target information related to autonomous driving, predict a shortage of the first memory region, and perform an operation to increase a free space of the first memory region based on a result of the prediction.

A method of operating a storage device which communicates with a host device, the method including: detecting a first power signal provided from the host device; determining whether a time interval between the detection of the first power signal and a most recent shutoff of the first power signal exceeds a reference time interval; generating a dummy delay signal in response to determining that the time interval exceeds the reference time interval; and managing a first subsequent memory operation based on the dummy delay signal.

A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

The invention provides an advanced memory performance monitoring and anomaly detection method, system and device, and relates to the technical field of memory monitoring, and the method comprises the steps: capturing a current memory operation executed by a monitored kernel and corresponding operation data through a memory delay monitoring module based on a kernel tracking point mechanism, the memory delay alarm module is used for judging whether memory delay alarm is performed for a monitored kernel; under the condition that the judgment result is yes, constructing a memory delay diagnosis event corresponding to the monitored kernel based on the operation data through a diagnosis event generation module; and through a diagnosis event distribution module, the memory delay diagnosis event is added to the to-be-processed diagnosis event queue, so that the memory diagnosis framework processes the memory delay diagnosis event contained in the to-be-processed diagnosis event queue, and a performance monitoring and anomaly detection result corresponding to the monitored kernel is obtained. According to the method, the monitoring fine granularity can be remarkably improved, and the false alarm and missing alarm conditions in the performance monitoring and abnormity monitoring process are reduced.

Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.

Systems and techniques include identifying a network layer for performing a memory operation, identifying a subset of a plurality of configuration bit clusters of a non-volatile distributed memory that are mapped to the identified network layer using a cluster mapping, in response to identifying the subset of the plurality of configuration bit clusters, activating the subset of the plurality of configuration bit clusters, loading network component data from the subset of the plurality of configuration bit clusters into a local buffer, and applying the network component data to the network layer for performing the memory operation.

Root-trusted guest memory page management is described. A root-trusted guest is loaded by a hardware platform and authenticated. The root-trusted guest is configured to manage memory operations of different guests via special privileges that permit the root-trusted guest to execute memory operations using a guest's private memory page. To do so, a guest page table includes a novel “T-bit” in each entry, which indicates whether the root-trusted guest or a different guest owns the associated memory page. Each entry in the guest page table for the root-trusted guest additionally includes a “C-bit” that indicates whether the corresponding memory page is a protected page. Combined C-bit and T-bit values for a page table entry dictate whether operations performed as part of handling a guest's memory request are offloaded from the hardware platform to the root-trusted guest.

The embodiment of the invention provides a memory optimization method and device, electronic equipment and a storage medium. After a target program runs, memory running information is obtained; according to the memory operation information, a memory load level is obtained, and the memory load level represents the memory load level of the memory demand of the target program; according to the memory load level, a target optimization strategy is executed, the target optimization strategy comprises at least two conditional execution sub-optimization strategies, the sub-optimization strategies are used for releasing cache data of the corresponding type in the memory, and execution conditions of the sub-optimization strategies correspond to the memory load level. By judging the memory load level for the memory demand of the target program and executing the target optimization strategy based on the memory load level, dynamic type memory recovery based on the memory load level is realized, the problems of slow program loading speed, program lagging and the like caused by excessive memory recovery and untimely memory recovery are avoided, and the memory recovery efficiency is improved. And the use experience of the application program is improved.

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

The invention relates to a clock transfer circuitry for a multi-chip RAM. Apparatus and methods include a first memory chip including a first memory bank, a command input configured to receive a command and a chip identifier, and a decoder configured to determine whether the command is to use a clock on a second memory chip when the command matches a predetermined condition. The apparatus and method also include a second memory chip including a second memory bank and a clock receiver configured to receive the clock from the first memory chip for memory operations on the second memory chip. The first memory chip acts as a base chip for a memory chip stack including the first memory chip and the second memory chip. When the command matches the predetermined condition, the first memory chip is configured to send the chip identifier to the second memory chip to the clock receiver to activate the clock receiver prior to transmitting the command to the second memory chip.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

Dynamic memory operations are described herein. According to the techniques, a system includes a stacked memory and one or more memory monitors configured to monitor a condition of the stacked memory. The system manager is configured to receive a monitored condition of the stacked memory from the one or more memory monitors and dynamically adjust operation of the stacked memory based on the monitored condition. In one or more embodiments, a system includes a memory and at least one register configured to store a ranking of each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of a respective portion in the memory. The memory controller is configured to dynamically refresh portions in the memory at different times based on a ranking of each of a plurality of portions of the memory stored in the at least one register.

The invention discloses a storage device and an electronic system. The storage device comprises a storage controller and N memories, wherein N is a natural number; the storage controller is connected with the N memories, and each memory comprises a reserved space and a storage space for data storage; wherein in the running process of the memory, the memory controller detects whether a fault block exists in the storage space or not, if yes, whether the reserved space has enough unallocated space or not is judged, and if yes, a target space in the reserved space is used for replacing the fault block to serve as a data storage space. According to the invention, a storage scheme with both cost and reliability is provided.