457 results about "Memory operation" patented technology

The invention discloses a compatible operation method for an Android camera HAL in a container based on memory access virtualization, and the method comprises the steps: taking a DMA-Buf memory heap of a Linux kernel host system as a target memory heap, taking an ION memory heap of an Android container system as a source memory heap, building a process exclusive memory management context, an FD cache table and a synchronous fence pool, and carrying out the execution of the process exclusive memory management context, the FD cache table and the synchronous fence pool; kernel registration and node binding of virtual ION equipment, pre-allocation of a first memory pool and access hook registration of kernel layer equipment are completed, and when an ION file descriptor is obtained in an HAL process, legality of a container process is verified, and context binding is initialized to the file descriptor; intercepting a memory allocation request of the HAL process, analyzing and adapting parameters, and preferentially multiplexing first memory pool resources to obtain an ION handle; when a data sharing request is processed, matching an FD cache or generating a new FD through an ION handle; when the HAL process releases the memory, resources are recycled according to a memory source, and when the HAL process exits, the context is cached or destroyed, so that cross-system memory operation compatibility is realized.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

The invention relates to a progressive memory delay monitoring and diagnosis method oriented to a virtual memory subsystem. The method comprises the following steps: mounting a BPF program to a plurality of key event points on a kernel; when the key event point is triggered, acquiring state information of a corresponding event; packaging the state information into an event, and writing the event into a perf ring buffer associated with the outputmap; and the user mode program asynchronously reads the packaged event from the perf ring buffer, performs classification and aggregation according to the process and the event type, generates a delay terminal log and a histogram, and outputs a diagnosis result. Through systematic architecture design, the state keeping capability and the kernel context access capability of the eBPF are combined with an event model of a virtual memory subsystem, and a set of closed-loop monitoring system oriented to a diagnosis target is constructed. High-precision and high-reliability memory operation delay measurement is realized.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

The invention provides an advanced memory performance monitoring and anomaly detection method, system and device, and relates to the technical field of memory monitoring, and the method comprises the steps: capturing a current memory operation executed by a monitored kernel and corresponding operation data through a memory delay monitoring module based on a kernel tracking point mechanism, the memory delay alarm module is used for judging whether memory delay alarm is performed for a monitored kernel; under the condition that the judgment result is yes, constructing a memory delay diagnosis event corresponding to the monitored kernel based on the operation data through a diagnosis event generation module; and through a diagnosis event distribution module, the memory delay diagnosis event is added to the to-be-processed diagnosis event queue, so that the memory diagnosis framework processes the memory delay diagnosis event contained in the to-be-processed diagnosis event queue, and a performance monitoring and anomaly detection result corresponding to the monitored kernel is obtained. According to the method, the monitoring fine granularity can be remarkably improved, and the false alarm and missing alarm conditions in the performance monitoring and abnormity monitoring process are reduced.

The embodiment of the invention provides a memory optimization method and device, electronic equipment and a storage medium. After a target program runs, memory running information is obtained; according to the memory operation information, a memory load level is obtained, and the memory load level represents the memory load level of the memory demand of the target program; according to the memory load level, a target optimization strategy is executed, the target optimization strategy comprises at least two conditional execution sub-optimization strategies, the sub-optimization strategies are used for releasing cache data of the corresponding type in the memory, and execution conditions of the sub-optimization strategies correspond to the memory load level. By judging the memory load level for the memory demand of the target program and executing the target optimization strategy based on the memory load level, dynamic type memory recovery based on the memory load level is realized, the problems of slow program loading speed, program lagging and the like caused by excessive memory recovery and untimely memory recovery are avoided, and the memory recovery efficiency is improved. And the use experience of the application program is improved.

The invention relates to a clock transfer circuitry for a multi-chip RAM. Apparatus and methods include a first memory chip including a first memory bank, a command input configured to receive a command and a chip identifier, and a decoder configured to determine whether the command is to use a clock on a second memory chip when the command matches a predetermined condition. The apparatus and method also include a second memory chip including a second memory bank and a clock receiver configured to receive the clock from the first memory chip for memory operations on the second memory chip. The first memory chip acts as a base chip for a memory chip stack including the first memory chip and the second memory chip. When the command matches the predetermined condition, the first memory chip is configured to send the chip identifier to the second memory chip to the clock receiver to activate the clock receiver prior to transmitting the command to the second memory chip.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

A system includes a first network device and a second network device. The first network device is to send over a network a command that specifies a value and instructs that the value be appended to a set of values in a memory. The second network device is to receive the command over the network, and to execute the command by appending the value to the set of values.

Methods, systems, and apparatuses include receiving, by a memory subsystem, a read command from a host device to read data from a memory portion of the memory subsystem. It is determined that the memory portion includes a partial block. A memory bin is determined for the memory portion in response to determining that the memory portion includes the partial block. A position is determined for the memory portion. A voltage offset is applied to a read voltage for the memory portion using the memory bin and the position.

The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.

The invention discloses a malicious code detection method and device for a third-party tool, a medium and a product. The method comprises the following steps: acquiring code data of a third-party tool; static analysis is carried out on the code data of the third-party tool to obtain static features, and the static features comprise at least one of cross-language call graph features, multi-version control flow graph difference features and local entropy values; the code data of the third-party tool is dynamically analyzed, dynamic characteristics are obtained, and the dynamic characteristics comprise at least one of an API calling sequence, memory operation information and a taint propagation path; based on a pre-trained detection model, the static features and the dynamic features are detected, a detection result of the code data of the third-party tool is obtained, and the detection result is used for indicating whether the code data of the third-party tool belongs to malicious codes or not. According to the technical scheme, collaborative analysis can be carried out on the code data through the static features and the dynamic features, and the detection accuracy of malicious codes is improved.

The invention relates to the field of artificial intelligence chips, and provides a memory aging test method, device and equipment, a storage medium and a program product.The method comprises the steps that according to the number of kernels of a processor to be tested, the memory space of the processor is divided into a plurality of memory address blocks to be distributed to the kernels of the processor; performing permutation and combination on the plurality of memory test algorithms to generate a plurality of first algorithm sequences; issuing the first algorithm sequence to a processor core by adopting a rotary full distribution mechanism; and each kernel runs the issued first algorithm sequence based on the allocated memory address block, and executes the aging test task. By permutation and combination of the memory test algorithms and issuing of the memory test algorithms to the kernels for operation and execution of the aging test task by adopting a rotation type full distribution mechanism, it can be ensured that memory address blocks of different kernels operate different algorithms at the same moment, the complexity of a memory operation scene is improved, and the efficiency is improved. And the test result can effectively guide the screening and quality control of the memory bank.

A non-volatile memory comprises a non-volatile memory structure that includes non-volatile memory cells. The non-volatile memory adjusts a ramp rate of a voltage signal applied to the non-volatile memory structure as part of a memory operation for the non-volatile memory cells. The adjusting the ramp rate is performed during the ramping up of the voltage signal and is based on voltage magnitude of the voltage signal at a particular time during the ramping up of the voltage signal.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

According to the communication system, the communication method and the communication device provided by the invention, when a member participating in set communication waits to use remote data of other members and local data of the member to perform calculation operation, a transmission unit not only acquires the remote data instead of the member, but also acquires local data of the member; the local data is read for the member according to the storage address described by the receiving request of the member, and the calculation operation is carried out on the remote data and the local data, so that the number of memory operations involved in the integrated communication process and the number of interactions among different transmission units are reduced, and transmission resources are saved; and the time delay for executing the calculation operation is reduced, and the execution efficiency of the set communication is improved.

Techniques for checking memory operations are disclosed. A processing unit is accessed, comprising compute slices, control unit, local memory disambiguation units (LMDUs), and a global MDU (GMDU). Each slice includes an execution unit and is coupled to successor and predecessor slices. Each slice is coupled to an LMDU. Each LMDU is coupled to the GMDU. A first slice executes a first slice task. The task includes a load instruction and address. The slice issues the load to an LMDU, saving load information in a memory operation table (MOT). For a not fully serviced load instruction, the LMDU sends the load information to the GMDU, storing load information in a global MOT (GMOT). The GMOT detects address aliasing between the load address and a previously issued address saved in the GMOT. The GMOT forwards memory information from previously issued memory instructions to the MOT to satisfy the load instruction.

A storage device may include a non-volatile memory device including a plurality of memory blocks, and processing circuitry configured to determine whether data associated with a memory operation received from a host device is infected with ransomware, the determining whether the data is infected with ransomware including, determining a first detection result value by calculating a distribution of bit values in the data, and outputting a second detection result value by detecting a similarity of the memory operation received from the host device with a memory operation transmitted by the processing circuitry to the non-volatile memory device in response to the first detection result value being less than or equal to a first threshold.

Embodiments of the present invention provide a memory operation method, a memory, an electronic device, and a storage medium. The memory operation method comprises: in response to detecting an error in a storage array of a memory during a working state of the memory, determining an error location of the error in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-package repair process, and on the basis of the error location, performing replacement of a target storage cell at the error location with a replacement storage cell in the storage array used for the post-package repair process; and after the post-package repair process, switching the memory back to the working state, and using the replacement storage cell to replace the target storage cell for operation. The memory operation method can improve the reliability of the memory.

A light detection and ranging (LIDAR) detector circuit includes a memory device and at least one control circuit. The memory device includes a non-transitory storage medium configured to store data indicating a detection event in a corresponding memory bin. The at least one control circuit is configured to receive a detection signal from one or more photodetector elements, identify the presence or absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and, in response to the identification of the presence or absence of a detection event, respectively, perform one of a first memory operation or a second memory operation to update the data in the corresponding memory bin. Related circuits and operating methods are also discussed.

The present disclosure provides an execution method of an atomic memory operation and a multi-core processor. The method comprises: a first node interacts with a master node to execute the atomic memory operation, wherein the first data is generated after the execution of the atomic memory operation; the first node sends a unique permission read request to the master node; the first node receives the first data returned by the master node in response to the unique permission read request; and the first node stores the first data in the cache of the first node.

Methods, systems, and devices for manual dynamic word line start voltage (MDWLSV) prediction and a self-adapting cache program for memory operations are described. In some examples, a memory device may receive a sequence of write commands for a memory block, and the memory device may monitor an interval between two consecutive write commands in the sequence. The memory device may compare the interval to a threshold interval. The memory device may utilize a first programming mode associated with a combination of a set feature (SF) and a get feature (GF) for MDWLSV prediction if the interval exceeds the threshold. The memory device may utilize a second programming mode associated with the SF for MDWLSV prediction if the interval is less than the threshold. The described techniques may provide for the host device to transmit commands for MDWLSV prediction in advance by transmitting the MDWLSV commands via a previous write command.

A memory device and method of operation are provided. The memory device includes memory cells connected to word lines and arranged in strings. The memory cells are configured to hold threshold voltages corresponding to memory states. Each of the strings has a drain-side select gate transistor on a drain-side of the one of the strings, the one of the strings including a top drain-side select gate transistor connected to a bit line and coupled to the memory cells of the one of the strings. A control device is coupled to the word lines and the bit lines and configured to, during a memory operation, apply an unselected top voltage to unselected ones of the top drain-side select gate transistors. The control device is further configured to, during the memory operation, simultaneously apply a selected top voltage to selected ones of the top drain-side select gate transistors. The unselected top voltage is intentionally different, electrically, from the selected top voltage.

The invention discloses an operation method of a memory, the memory and a memory system, and belongs to the technical field of storage. According to the method, in the process of recovering the erasing operation of the storage block, if the erasing operation is in an erasing pulse stage, the voltage of a specific word line connected with the storage block is released in advance in response to the situation that the pause frequency of the erasing operation in the erasing pulse stage is greater than or equal to a threshold value, so that the voltage of the specific word line can enter a floating state in advance; furthermore, the voltage of the specific word line can be increased along with the increase of the ACS (and / or BL) voltage in advance, and the voltage difference between the specific word line and the ACS (and / or BL) in the current recovery erasure operation process is reduced, so that the voltage difference is prevented from exceeding the threshold voltage of the specific unit, the weak erasure of the specific unit in the current recovery erasure operation process can be avoided, and the recovery erasure efficiency of the specific unit is improved. And the frequency of weak erasure of the specific unit in the erasure operation process is reduced, so that the reliability and the performance of the memory can be improved.

The present disclosure provides systems, methods, and apparatuses of a memory system for operating at least a portion of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core to schedule a first memory operation for a first portion of a clock cycle of a memory clock, and includes a second core to schedule a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

The application belongs to the technical field of integrated circuits, and particularly relates to a read margin enhanced storage array, a 9T storage and calculation circuit, a multiply-accumulate operation circuit, an in-memory operation circuit based on the 9T storage, and a CIM chip based on the 9T storage. The 9T storage and calculation circuit comprises a basic 6T storage unit and a calculation unit composed of three additional NMOS tubes N5, N6 and N7. The multiply-accumulate operation circuit is further designed on the basis of the aforementioned 9T storage and calculation circuit. The multiply-accumulate operation circuit comprises a calculation array, a current mirror circuit, an input circuit, a current monitoring array and an output circuit according to the function division. Based on the new architecture of the multiply-accumulate operation circuit and the traditional SRAM circuit, the application further provides an in-memory operation circuit based on the 9T storage, and the CIM circuit has the functions of data reading / writing, holding and multiply-accumulate operation. The application solves the problems of the 6T storage only having the data storage function, the operation logic of the existing multiply-accumulate operation circuit being complex, and the operation efficiency being low.

A management technique for high bandwidth memory is disclosed. A processing management circuit (PMC) has a main executing circuit and a main memory and is configured to manage at least one processor operation performed by at least one of a first processing element (PE) or a second PE. A shared memory is configured to be shared by the PMC, the first PE, and the second PE. A memory management circuit (MMC) is configured to manage a memory operation on the shared memory based on a memory access by at least one of the PMC, the first PE, or the second PE. The at least one processor operation includes at least one of a program launch, a program execution, and an interrupt delivery.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

In some implementations, a memory apparatus may transmit, to a host system, capability information indicating one or more supported memory operations of the memory apparatus. The memory apparatus may receive, from the host system, configuration information indicating one or more performance limits for at least one supported memory operation of the one or more supported memory operations.