300 results about "Base address" patented technology

The invention discloses an extension equipment function configuration method and device, computer equipment and a storage medium, and relates to the technical field of data processing. According to the method, a hardware and firmware collaborative dynamic configuration framework is constructed, and a receiving queue is adopted at an extension equipment end to trigger a central processing unit firmware processing mechanism; in combination with virtualization design of a shadow configuration space and a shadow register, dynamic reconstruction of configuration parameters and an address mapping strategy during operation is realized; a host end supports configuration space access, base address register remapping and memory data transmission interaction through a transaction generation and routing mechanism driven by an event type. Hardware solidification limitation of traditional extension equipment is broken through through software and hardware decoupling design, the problems that function extension capacity is insufficient, resource dynamic allocation is difficult and protocol updating and virtualization scenes cannot be adapted are solved, and the technical effects of improving configuration reconstruction efficiency and address space utilization rate and supporting virtual function creation are achieved. And the adaptability of the equipment in cloud computing and edge computing environments is enhanced.

The invention relates to the technical field of chip verification, in particular to a general register model generation method and system, and the method comprises the steps: obtaining various types of register description files; calling corresponding analytic functions according to different file types based on the various types of register description files, and extracting register information from the various types of register description files; the register information comprises a base address of a register model, a register name, a register offset address, a register attribute, a register domain name, an initial address of a register domain, a bit width of the register domain, an attribute of the register domain and a default value of the register domain; performing error detection on the register information, and performing classification processing on detected errors according to error levels; generating a corresponding register model file based on the processed register information; and the generated register model files are integrated into the top-layer file to obtain the integrated register model, so that the file compatibility is improved, and the cost is reduced.

The invention relates to a firmware upgrading method and electronic equipment. The method comprises the following steps: in a first stage of upgrading, constructing upgrading meta-information according to a current partition table and a to-be-upgraded firmware data storage area base address obtained by calculating to-be-upgraded firmware meta-information, and according to a block list description file, updating the to-be-upgraded firmware data storage area base address; in the first-stage upgrade, a partition table file with a preset name in a firmware upgrade package under a preset firmware upgrade package path of an encrypted preset user data partition and all to-be-upgraded firmware mirror image files are stored in an address space determined by a base address of a to-be-upgraded firmware data storage area; and determining a to-be-upgraded firmware data storage space end address and a to-be-upgraded firmware data moving base address according to the guide communication partition address space change mark, and copying data in an address space determined by the to-be-upgraded firmware data storage space end address to the to-be-upgraded firmware data moving base address. According to the invention, under the condition of user data partition encryption, the firmware with any change of the partition table can be safely and reliably upgraded.

The invention provides an accelerator and a request processing method, which can be applied to the technical field of computers. The accelerator comprises: a computing unit configured to send an access request to a target virtual address to a memory management unit; the memory management unit comprises an address translation buffer module, and the memory management unit is configured to respond to the received access request and search a corresponding physical page number in the address translation buffer module according to the target virtual address so as to determine a physical address; wherein the address translation buffer module comprises a plurality of buffer units, and the address translation buffer module is configured to determine a target buffer unit from the plurality of buffer units according to a virtual base address in a target virtual address; and based on address identification information in the target virtual address, searching a physical page number corresponding to the target virtual address from physical page numbers corresponding to the at least two different virtual base addresses stored in the target buffer unit to determine a physical address.

The invention discloses a tracking data processing method, a medium, a main routing node and a sub routing node, relates to the technical field of communication, and discloses the tracking data processing method which is applied to the main routing node and comprises the following steps: configuring a target base address of a storage space for storing tracking data under the condition that the tracking data provided by the sub routing node is received; converting the tracking data into a routing protocol format to obtain routing tracking data; and routing the routing tracking data to a storage space indicated by the target base address. The processing efficiency of the tracking data is effectively improved.

The embodiment of the invention discloses a system startup memory detection method and device, equipment and a storage medium, and the method comprises the steps: calculating the maximum value of a Hypervisor early virtual address mapping range according to the initial address of Hypervisor operation before a final page table takes effect; when the dynamic allocation pool is utilized to allocate the memory page, determining a virtual address range of the allocated memory page by utilizing a base address of the allocated memory page, and detecting whether the virtual address range of the allocated memory page exceeds a maximum value of a Hypervisor early virtual address mapping range or not; and when the maximum value of the Hypervisor early virtual address mapping range is exceeded, outputting an error prompt, and returning a memory error. Compared with a traditional estimation mode, the probability that estimation is inaccurate due to the fact that dynamic allocation changes is reduced, the memory errors can be accurately detected in advance before the system crashes, and a developer can conveniently locate the reason of crashes.

The embodiment of the invention discloses a PCIe encryption card low-power-consumption implementation method and system based on ASPM, and the method comprises the steps: switching the low-power-consumption and working mode of a PCIe encryption card through alternately employing low-power-consumption state interruption and base address register or address conversion unit matching interruption, namely, when a power management module of a PCIe controller detects that the power management module is in an idle state; the PCIe controller generates a low-power-consumption state interrupt signal to the central processing unit and each algorithm module of the PCIe encryption card, in a low-power-consumption state interrupt service program, the central processing unit and each algorithm module enter a low-power-consumption mode, and when the PCIe interface receives an upper host command, the central processing unit and each algorithm module enter a low-power-consumption mode. The PCIe controller generates a base address register interrupt signal or an address conversion unit matching interrupt signal to the central processing unit and each algorithm module, the central processing unit and each algorithm module are awakened, the low-power-consumption mode is quitted, and firmware carries out encryption and decryption command analysis processing on a host command data packet. According to the scheme, the power consumption of the PCIe encryption card can be controlled to be lower.

The present application relates to the field of data processing, and disclosed are a network card device and a data transmission system, which are used for solving the problem whereby data transmission occupies the access bandwidth of a host memory. The network card device comprises a storage module; a descriptor queue address register; a calculation high-speed link hard core module, which is used for transmitting data sent by a host to a first data storage area, transmitting a descriptor sent by the host to a first descriptor storage area, and transmitting a trigger instruction sent by the host to a network data processing module; and the network data processing module, which is used for acquiring a base address from the descriptor queue address register when receiving the trigger instruction, reading a target descriptor in the first descriptor storage area based on the base address and the trigger instruction, reading target data corresponding to the target descriptor in the first data storage area, and outputting the target data to a network. The present application can reserve the access bandwidth of a host memory for other functions running on the host to use, so that the overall operation efficiency of the host is improved.

The invention provides a processor supporting data multiplexing and instruction multiplexing, which is used for supporting multiplexing of operands and instructions of a previous calculation task in a later-executed calculation task, and realizes operand multiplexing and instruction multiplexing based on configuration information stored by a host control module connected with the processor. The processor comprises a configuration information caching module used for storing a storage offset and a storage offset use mark which are acquired from configuration information and correspond to each instruction in each calculation task; the base address dynamic generation module is used for storing a data cache index address of each calculation task and generating a real base address of each instruction in each calculation task; and the calculation module is used for acquiring an operand to execute each calculation task based on the real base address of each instruction in each calculation task generated by the base address dynamic generation module.

A memory access request is initiated by a first peripheral device. The memory access request includes a virtual address. A host physical address (HPA) associated with the virtual address is determined. An identifier of a base address register (BAR) associated with the HPA is determined by the first peripheral device. The memory access request is transmitted using the identifier of the BAR to a second peripheral device.

Systems and methods for supporting generic pointers in hardware of a graphics processing unit (GPU) are provided. In various examples, a GPU includes multiple sub-cores each having a processing resource and a load / store pipeline. The processing resource is operable to receive a memory access message including a generic pointer. The processing resource is further operable to output a load or store operation to the load / store pipeline based on the memory access message, in which an address for the load or store operation is determined based on a base address of a named memory type of a plurality of named memory types referenced by the generic pointer and an offset into a memory of the named memory type. The load / store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.

The embodiment of the invention provides a memory management method and related equipment, which are used for improving the persistence efficiency of memory access. Comprising the following steps: distributing a unique logic reference identifier for each object in the memory management system as a logic reference; dividing the plurality of objects according to the sequence of the logic reference identifiers, and storing the objects in one or more object groups; establishing a global ordered index table; wherein the global ordered index table comprises boundary information, and the boundary information comprises a maximum logic reference identifier and a physical base address; in response to an access request for the target logic reference identifier, executing primary addressing in the global ordered index table, and positioning a candidate object group containing the target logic reference identifier through a lower bound search algorithm; and executing secondary addressing in the candidate object group, calculating and obtaining the physical offset of the target object in the candidate object group according to the difference between the target logic reference identifier and the initial logic reference identifier of the corresponding candidate object group, and generating a target physical address.

The invention discloses a PCIe switch capable of modifying hardware configuration. The PCIe switch comprises at least one port, a message manager, a security manager and a configuration management module. Wherein each port is connected with a root complex, an application program runs on the root complex, the message managers are mapped in base address registers of the ports in a one-to-one correspondence mode and used for information exchange between the root complex and the security manager, and the security manager is in communication connection with the message managers and used for analyzing, verifying and replying messages of the root complex. And the configuration management module is in communication connection with the security manager, and configures the PCIe switch based on the configuration information. According to the PCIe switch, batch data transmission and information interaction between the root complex and the PCIe switch can be realized, and only the application subjected to authorization verification has the authority to modify the configuration, so that the PCIe switch can modify the configuration according to the application requirement on the root complex, and the PCIe switch is high in flexibility, safe, reliable and easy to expand.

Embodiments of apparatuses and methods for copying and operating on matrix elements are described. In embodiments, an apparatus includes a hardware instruction decoder to decode a single instruction and execution circuitry, coupled to hardware instruction decoder, to perform one or more operations corresponding to the single instruction. The single instruction has a first operand to reference a base address of a first representation of a source matrix and a second operand to reference a base address of second representation of a destination matrix. The one or more operations include copying elements of the source matrix to corresponding locations in the destination matrix and filling empty elements of the destination matrix with a single value.

Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

The invention provides a PCIe (Peripheral Component Interconnect Express) endpoint device communication method, device and equipment based on software defined interconnection. The implementation scheme comprises the following steps: acquiring a communication request between endpoint devices; based on the bound queue pair relationship, applying for a point-to-point memory in a base address register space exposed by the receiving end, and determining a destination address corresponding to the communication request; according to the communication request and the destination address, the work queue element is issued to the bound queue pair, so that the endpoint device corresponding to the queue pair executes data handling; and generating a completion event associated with the communication request based on interruption information sent by the endpoint equipment, and pushing the completion event into a completion queue, so that a user reads and judges a transmission result through an event acquisition interface. According to the scheme, an end-to-end communication path can be communicated through a unified queue and event interface, the overall efficiency is improved while the bottom layer difference is shielded, high performance and low delay are ensured, reliability and restorability are enhanced, and good parallel expansion capacity is achieved.

The embodiment of the invention provides a memory address mapping method, a memory management unit, electronic equipment and a storage medium. The memory address mapping method comprises the following steps: receiving a virtual address from a current process; determining an address field table and an address field attribute table according to the identification information of the current process; base address information is searched from an address field table according to a first virtual address field included in the virtual address, the base address information is used for indicating a base address of a target physical address space segment, and the target physical address space segment is a physical address space segment where a physical address mapped with the virtual address is located; searching offset information from an address field attribute table according to a second virtual address field included in the virtual address, wherein the offset information is used for indicating the offset of a physical address mapped with the virtual address in a target physical address space field; and determining a physical address mapped with the virtual address according to the base address information and the offset information. According to the scheme, the efficiency of mapping the virtual address into the physical address can be improved.

The invention provides a thread block data prefetching method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The thread block data prefetching method comprises the steps that a data prefetching thread bundle corresponding to a next thread block is created; the data prefetching thread bundle is used for calculating a data initial base address of each thread bundle in the next thread block; executing each thread bundle in the current thread block and executing the data prefetching thread bundle, and determining a data initial base address of each thread bundle in the next thread block; and obtaining operation data corresponding to the next thread block based on the data initial base address of each thread bundle in the next thread block. According to the method and the device provided by the invention, the data pre-fetching of the cross-thread block boundary is realized, and the efficiency and the accuracy of the data pre-fetching are improved.

A memory device, an operating method thereof and an electronic device are provided. The memory device includes a memory array, an address generator, a data register, and a processing unit. The address generator is configured to receive an instruction and a base address of the instruction from a host, and sequentially generate a target address for performing an operation of the instruction by sequentially adding an offset to the base address. The data register is configured to store data values corresponding to one or more of the target addresses. The processing unit is configured to perform one or more of the operations of the instruction based on the data value.

Systems and methods for automatically managing tunnels in a network. The methods comprise: detecting, by a router of the network, that a tunnel is needed for communicating a packet to at least one member of a multicast group of another network; selecting, by the router, a base address from a set of unused base addresses; communicating, from the router, an auto-tunnel create message including the base address which was previously selected; receiving, by the router, a tunnel create ACK message sent from another router of the network upon the another router's verification that base address is unused; creating the tunnel using the base address for the router and another base address for the another router; encapsulating the packet; and communicating the encapsulated packet from the router to the another router using the tunnel which was created.

When a graphics processor is executing a pipeline stage that generates a respective data element for each of a plurality of work items, the generated data elements are stored by storing one or more groups of N data elements in respective work item packets. When storing a data element for a work item, an identifier for the work item configured such that a first part of the work item identifier indicates an offset for the group of N data elements that the data element for the work item belongs to relative to a base address, and a second, different part of the work item identifier indicates the relative position of the data element for the work item within the group of N data, is used to determine a memory address at which to store the data element for the work item.

The present invention discloses an FPGA-based SATA data DMA transmission system and method. The system utilizes a register configuration module, a first FIFO storage module, a second FIFO storage module, a DMA state machine module, a SATA controller module, and an MB bus to AXI bus conversion module. The register configuration module is configured to send startup and read / write operation instructions to the DMA state machine module and receive a "busy" signal; send startup and read / write operation instructions and user data length to the SATA controller module and receive a "SATA_done" signal; the first FIFO storage module is configured to store discrete user memory space base addresses and corresponding space sizes; the DMA state machine module is configured to monitor the status of the DMA state machine; the second FIFO storage module is configured to store SATA read / write data; and the SATA controller module is configured to implement SATA interface functions. The present invention improves transmission rate and CPU performance.

Disclosed embodiments relate to look up table operations implemented in a digital data processor. A look up table read instruction recalls data elements of a specified data size from table(s) and stores recalled data elements in successive slots in a destination register. Disclosed embodiments promote data elements to a larger size with selected sign or zero extension. A source operand register stores vector offsets from a table start address. A destination operand stores the results of the look up table read. The look up table instruction implies a base address register and a configuration register. The base address register stores a table base address. The configuration register sets various look up table read operation parameters.

The invention provides a processor, a method for executing an instruction on a processor and a computer. The processor comprises at least one single-instruction multiple-thread processing units. The single-instruction multiple-thread processing unit includes a plurality of warps for executing an instruction; a shared register group, which includes a plurality of general-purpose registers shared by the plurality of warps; and a predicate base address register, which is configured to: correspond to the plurality of warps; and indicate a base address for a subset of the plurality of general-purpose registers that serves as a predicate register for the warp in the shared register group, wherein: the warp performs a predicated execution for an instruction in view of a predicate value in the subset of the plurality of general-purpose registers that serves as the predicate register for the warp.

The application provides a computer system and a multi-server shared storage system, which can be applied to the technical field of server storage. The computer system comprises: a computer system, a non-volatile memory and a plurality of servers which are electrically connected; an arbitration module is used for determining a target server according to a plurality of access signals of the plurality of servers, and sending an authorization signal to the target server and a bus buffer module; the bus buffer module is used for connecting a transmission bus between the target server and the non-volatile memory according to the authorization signal; in the case that a chip select signal in a flash signal is at an effective level, an access address is obtained from the flash signal, the access address is configured by using a configuration partition base address to obtain a target access address, signal conversion is performed on the target access address, a target flash signal is obtained and sent to the non-volatile memory, so that the non-volatile memory manages data stored in a storage partition corresponding to the target access address.

The invention relates to the technical field of dynamic instrumentation, in particular to a method and system for dynamically instrumenting a swan NEXT Native layer function. The method comprises the following steps: obtaining a process identifier of a target application process, and reading a corresponding memory mapping file to obtain a loading base address and a file path of a Native layer ELF shared object; an ELF file corresponding to the file path is read, and an index relation table of the target function symbol name of each item in the PLT section, the PLT item and the file offset of the PLT section is established; adding the loading base address and the file offset of the PLT section to calculate the initial address of the memory of the PLT section; and calculating the memory absolute address of the PLT entry of the target function according to the PLT entry of the to-be-intercepted function in the index relation table. According to the method, the index relationship between the symbol and the address is established by analyzing the memory mapping file and the ELF shared object file of the target process, and accurate function interception is realized at the PLT entry level.

Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

The invention relates to the technical field of data storage, and particularly discloses an AWG waveform data storage method based on a DDR architecture, which comprises the following steps: waveform data storage configuration: performing logic hierarchical division on a DDR storage space, and configuring header information descriptors containing data length information for each waveform sub-block, classified storage and identification of test excitation waveform data are realized; and dynamic waveform scheduling: after the upper computer issues the initial base address of the unified waveform data block, the FPGA calculates the initial address of the waveform data of each channel according to the initial base address, and transmits the waveform data of each channel to the corresponding DAC unit in parallel in combination with the length of the waveform data to generate a test excitation waveform. The DDR storage space is logically divided into multi-channel independent areas, multi-waveform sub-blocks are divided in each area, and a special header information descriptor is matched, so that pre-storage and quick positioning of multiple test excitation waveforms are realized, and the limitation that a traditional scheme only supports a single test mode is solved.

The invention discloses a method, a product and a medium used in an AI accelerator chip, and the method comprises the steps: statically dividing a plurality of physical buffer areas in a shared memory of the AI accelerator chip according to a preset pipeline stage, and locking a base address of each physical buffer area in the plurality of physical buffer areas; analyzing calculation and memory allocation logic of operator blocks of the AI model, and inserting a synchronization token on one or more intermediate representation nodes of the AI model based on an analysis result, the synchronization token inserted into any intermediate representation node contains information about a synchronization dependency relationship of hardware operation represented by the intermediate representation node in a physical pipeline executed by a hardware engine in the AI accelerator chip; and generating a hardware instruction stream based on the intermediate representation of the AI model, and interleaving and rearranging instruction blocks in the hardware instruction stream based on a synchronization token inserted on one or more intermediate representation nodes.

The present invention discloses a fault repair method, device, electronic device and storage medium. The method comprises: if it is in the current extensible firmware interface pre-initialization stage, then obtaining the base address of the preset base address register of the H2B device; obtaining the fault address information and the first information check value according to the base address; wherein the fault address information and the first information check value are stored in the preset storage location corresponding to the preset base address register; performing a preset check operation on the fault address information to obtain the second information check value, and determining whether to perform the fault repair operation according to the first information check value and the second information check value. By running the technical solution provided by the embodiment of the present invention, fault handling is performed without entering the SMM mode; and it can avoid the problem that when the fault address information changes after storage, the fault handling cannot be performed, or the fault is not handled correctly if the fault address information is still used, thereby improving the accuracy and effectiveness of fault handling.