45 results about "Base address" patented technology

Disclosed are a method, product, and medium for use in an AI accelerator chip, the method comprising: statically dividing a plurality of physical buffers in a shared memory of the AI accelerator chip according to a preset number of pipeline stages, and locking a base address of each of the plurality of physical buffers; parsing computation and memory allocation logic of an operator block of an AI model, and inserting a synchronization token on one or more intermediate representation nodes of the AI model based on a result of the parsing, the synchronization token inserted on any one of the intermediate representation nodes containing information about a synchronization dependency relationship in a physical pipeline in which a hardware engine of the AI accelerator chip performs a hardware operation represented by the intermediate representation node; and generating a hardware instruction stream based on the intermediate representation of the AI model, and interleaving and rearranging instruction blocks in the hardware instruction stream based on the synchronization token inserted on the one or more intermediate representation nodes.

This invention discloses a data aggregation auxiliary device, system, and data aggregation method. The PCIe controller of the aggregation auxiliary device receives UALink data packets from an external processor through each UALink port and forwards them to the converter, identifying the source ID corresponding to the UALink port. When aggregating the first UALink data packet, the converter parses the UALink data packet to extract the sector index and payload data, and stores the payload data in the payload buffer. Based on the corresponding source ID, the converter looks up the associated PCIe base address and sector size in a pre-built protocol conversion table. Combining the sector index, the converter calculates the corresponding PCIe target address, generates the PCIe TLP header data, and stores it in a register. When aggregating the next UALink data packet, the header data in the register is reused, significantly reducing the header overhead on the PCIe bus.

A system, processing apparatus, and method of operation of a processing apparatus are disclosed. The system includes a central processing unit, a first processing apparatus, and a second processing apparatus, and the first processing apparatus: (i) reads raw data from a first memory, (ii) reads pre-processing information from a first base address register, (iii) performs a pre-processing operation on the raw data using the pre-processing information to generate result data, and (iv) transfers the result data to the second processing apparatus without going through an external processor.

The present disclosure provides a method for PCIE data transmission. The method includes: determining whether the length of a PCIE data packet to be transmitted is less than a preset length; when it is determined that the length of the PCIE data packet is less than the preset length, performing data transmission on the PCIE data packet by means of a space of a base address register and a protocol converter; and when it is determined that the length of the PCIE data packet is greater than or equal to the preset length, performing data reading / writing on the PCIE data packet in a DMA manner. Therefore, the utilization rate of a PCIE bandwidth is improved, and the running reliability of a host is improved.

The application discloses a kind of embedded equipment multi-network interface MAC address allocation method and terminal;The application starts the bootstrap loader of embedded system, reads the MAC address stored in advance, and write the MAC address in dtb file;Start kernel, when loading dsa driver, obtain the MAC address in the dtb file as MAC base address, carry out preset processing to the MAC base address, obtain continuous, mutually different and the same number of network interface MAC address as the number of network interface, write each network interface MAC address in the structure body of corresponding network interface respectively, and carry out network interface initialization;Start file system;The application passes through the bootstrap loader of embedded system and imports kernel into kernel by MAC base address, and kernel is handled to base address, it is guaranteed that the MAC address of each network interface is different, and when in kernel state, address allocation is carried out to each network interface and subsequent network interface initialization is carried out, it is guaranteed that each network interface is in normal state, and can normally carry out service processing.

Metadata generally refers to data that describes, or gives information about, other data. Metadata can be used for a wide variety of purposes, including for ensuring the safety of memory accesses. For example, to prevent memory safety errors, metadata, which indicates the base address and size of the data, can be used to validate memory access requests as prerequisite to allowing the memory access. While there are many useful applications of metadata, including for memory safety as mentioned above, the underlying metadata storage and retrieval processes that have been developed to date suffer from various problems. The present disclosure provides an object-level metadata locator, which can allow for an internal object layout to be maintained and which can scale to an arbitrary number of objects while requiring lower memory overhead than that required in the prior art.

This application relates to the field of communication terminal technology, and provides a multi-task queue management method, a multi-task queue management device, a terminal device, a chip, and a chip module. The method includes: each subtask control unit determining the validity of a subtask arbitration request signal and a subtask arbitration request masking signal based on a subtask trigger signal, a subtask priority value, and the current state of the processed subtask, and outputting these to a multi-task arbitration control unit, so that the multi-task arbitration control unit selects the highest-priority valid subtask from the multi-task queue as the target subtask; outputting the target subtask's configuration parameter read signal and the subtask configuration parameter storage base address to a subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask. This method enables hardware to support software configuration of high-priority subtasks interrupting the currently processed subtask, thus ensuring the processing efficiency of high-priority subtasks.

The application discloses an address remapping device, method and processor, and the device comprises: a first calculation module which takes the complement of the low L bits of an original logical address to obtain a complement result; a second calculation module which dynamically obtains an offset correction value which keeps the order of an output channel group according to the original logical address; a third calculation module which determines the base address offset across the input channel group; a fourth calculation module which performs summation and one addition operation on the complement result and the offset correction value, and extracts the low L bits to obtain a local logical address; and finally, an address composition module which adds the local logical address and the base address offset to generate a target logical address corresponding to the original logical address. In the memory access path, the application can efficiently realize the 180° rotation of the convolution kernel at the hardware level through additional processing of the address, so as to fundamentally eliminate the efficiency loss caused by the software rotation.

Systems and methods for automatically managing tunnels in a network. The methods comprise: detecting, by a router of the network, that a tunnel is needed for communicating a packet to at least one member of a multicast group of another network; selecting, by the router, a base address from a set of unused base addresses; communicating, from the router, an auto-tunnel create message including the base address which was previously selected; receiving, by the router, a tunnel create ACK message sent from another router of the network upon the another router's verification that base address is unused; creating the tunnel using the base address for the router and another base address for the another router; encapsulating the packet; and communicating the encapsulated packet from the router to the another router using the tunnel which was created.

This invention relates to the field of marine water sample detection and control technology, and discloses an automated control system for stratified marine water sample collection, including parameter acquisition, feature recognition, spatial retrieval, and sampling control modules. The feature recognition module uses pressure feedback to convert the medium property sequence into differential features and extracts dynamic control boundaries to offset the heave and oscillation of the controlled detection components. The spatial retrieval module constructs a three-dimensional parametric surface based on the dynamic control boundaries and discretizes it to generate an octree topology space. It establishes a hash map index table that corresponds to the trigger state and the memory addressing base address. By addressing the base address with a single instruction, the algebraic calculation process is eliminated, and the trigger delay jitter caused by the calculation is eliminated. This invention realizes the transformation from fixed depth triggering to active physical and chemical boundary tracking control mode, eliminates instruction lag and decouples spatial fluctuation interference, and ensures that the sampling action is accurately locked to the physical and chemical boundary.

The application relates to the technical field of computers, and discloses a memory configuration information reporting method and device, computer equipment and a storage medium, the method comprises the following steps: in the case that configuration data sets of a target device are acquired, acquiring device information of the target device from the configuration data sets; acquiring a device identifier of the target device in the device information, determining a device starting address of the target device according to the device identifier, and obtaining a memory base address of the target device according to the device starting address and address offset information; acquiring an instruction according to the memory base address and memory configuration information, accessing the target device and acquiring memory configuration information of the memory under the target device; and uploading the memory configuration information to an operating system. The application solves the problem that it is difficult to report Type17 information and other configuration information of the memory under an external PCIe device to the operating system.

The application provides a virtual information processing method, device and storage medium. The method comprises the following steps: a host system creates a virtual device instance, allocs hardware resources and a continuous memory area for the virtual device instance, generates and stores first configuration information corresponding to a physical hardware control register area and second configuration information indicating the memory area, and transmits a real physical base address of the memory area to the virtual device instance; after a virtual machine binds the virtual device instance, the virtual machine completes zero-copy data processing according to the real physical base address, the first configuration information and the second configuration information. Through virtual device instantiation, independent memory allocation and direct transmission of a physical base address, the virtual machine can directly initiate a hardware DMA operation, the data copying overhead is saved, a single physical hardware can be safely shared by multiple virtual machines, and the I / O performance of a virtualization environment and the hardware utilization rate are improved.

The application relates to the technical field of code conversion of data communication, and discloses a coding conversion processing method of controller communication signals, which comprises the following steps: generating a current bit difference vector by performing bitwise exclusive OR on a current serial input code stream vector and a history cache vector, determining a highest active bit boundary index and a lowest active bit boundary index by scanning and counting the current bit difference vector, calculating a feature word length, right-shifting the current bit difference vector by the lowest active bit boundary index, extracting a feature active section vector by truncation, searching a base address pointer, adding an offset to calculate a target physical storage address, reading a jump parameter according to the target physical storage address, and outputting a fixed-length conversion word stream. Through the cooperation of bidirectional boundary truncation and direct addressing, the application eliminates mapping collision and multi-round search time delay, fixes the code conversion overhead as constant single-period addressing, and ensures zero jitter of decoding delay.

This application provides a unified adaptation method for multi-vendor switches and an SDN controller, including: allocating CMA physical pages for each switch model; establishing a model page table and a shadow bitmap byte array; the model page table records the CMA physical page base address of the switch model; and each bit of each byte in the array represents the existence status of the encoding / decoding context of each firmware version within the corresponding CMA physical page; when an encoding / decoding context of a firmware version for a switch model is generated, it is written to the corresponding slot in the CMA physical page, and the corresponding bit is set to valid; in response to a packet from the target switch, the model identifier and firmware version number are extracted; the target CMA physical page base address is obtained from the model page table based on the model identifier, the firmware version number is read from the shadow bitmap byte array, and the context address is calculated to obtain the encoding / decoding context. This application can avoid memory fragmentation, ensure the resident nature of the context in memory, and achieve fast context determination and latency addressing.

The present application relates to the technical field of address translation request scheduling, and particularly relates to an address translation request aggregation scheduling method and system. The present application maintains a pending request filter table, each table entry corresponding to a 4KB address range, recording address translation requests that have been sent but have not received responses. When a new request is received, the 4KB base address to which the virtual address belongs is calculated and the filter table is queried: if there is a corresponding table entry, the request is added to the associated waiting queue, and the new request is not sent; if there is no corresponding table entry, the new request is sent and a new table entry is created. Thus, during the waiting response period, subsequent requests in the same address range are aggregated, the number of repeated requests is reduced from N times to 1 time, the root complex load is significantly reduced, redundant transactions are reduced, and the hardware overhead is extremely low.

This application provides a method, apparatus, and storage medium for dynamically adjusting the base address register of a PCIe endpoint device, relating to the field of computer technology. In this method, when the host system powers on or resets, the microcontroller controls the reset signal of the PCIe endpoint device according to a preset timing sequence, enabling the endpoint device to be in a configurable state before the host system performs standard PCIe enumeration. While the endpoint device is in this configurable state, the microcontroller dynamically adjusts the address space size parameter of the base address register through a debug interface. After the address space size parameter of the base address register is modified, the host system performs device enumeration and allocates resources according to the modified address space size parameter of each endpoint device. This method achieves dynamic adjustment and optimization of the PCIe device address space capability, improving the flexibility of system resource allocation and device compatibility.

An apparatus includes processor circuitry having an execution pipeline configured to execute instructions within an instruction stream, the instruction stream including a first instance of an instruction executable to compute an address for accessing a data array. The first instance of the instruction may specify a set of operands, the set of operands including a pointer to a base address of the data array, an index into the data array, and a size of a data element within the data array. In response to receiving the first instance of the instruction, the execution pipeline may be configured to perform an arithmetic operation including multiplication of the index and the size to generate a result for the address. In response to the arithmetic operation generating an overflow condition, the execution pipeline may be further configured to perform a first correction action preventing access to the data array.

This invention relates to metadata management for abnormal shutdowns of a memory subsystem. It maintains a logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure. The L2P data structure includes entries mapping logical addresses to physical addresses. The P2L data structure includes data items mapping physical addresses to logical addresses. Each P2L data item also includes a data movement status, a base address, and a boundary indicator. A movement operation is detected, indicating that data referenced by a logical address will be moved from a source physical address to a target physical address. In response to detecting the movement operation, the data movement status associated with the source physical address in the P2L data structure is updated.

This application relates to an instruction processing method and apparatus, a processor, an electronic device, and a readable storage medium. The method includes: when the addresses of a first memory access instruction and a second memory access instruction overlap, obtaining first address information of the first memory access instruction and second address information of the second memory access instruction; determining a merging base address and a merging address offset for a merge instruction between the first and second memory access instructions based on the first and second address information; and processing the first and second memory access instructions based on the merging base address and the merging address offset. This method can improve the scenario applicability of the instruction merging scheme.

The application discloses a kind of based on FPGA's NVMe host controller hardware unloading device, include: MicroBlaze initialization configuration module, for initialization configuration to system after power on;I / O queue processing module, for command segmentation, encapsulation, distribution and doorbell register maintenance etc.;Master AXI bus control module, for the doorbell value is packed into AXI data package and is submitted to NVMe SSD;From AXI bus control module, for SSD read-write transaction is converted into SQE / PRP reading, data read-write, CQE writing and interrupt submission etc. Operation;Data buffer DMA module, for data in data buffer according to base address and length is read-write handling.The based on FPGA's NVMe host controller hardware unloading device of the application, NVMe protocol stack is unloaded by FPGA hardware, uses hardware to realize NVMe protocol stack in, such as queue management, data transmission and interrupt processing, to optimize resource allocation, break through the performance bottleneck of existing software implementation NVMe protocol stack scheme, more fully utilize the bandwidth of NVMe SSD.

The application discloses a high-efficiency communication method for cross-protocol conversion, which comprises the following steps: receiving a UALink data packet sent by a source UALink port receiving processor and identifying a source ID of the source UALink port; analyzing the UALink data packet to extract a target PCIe port ID and a sector index therein; searching a PCIe base address and a sector size associated with the source ID in a pre-established protocol conversion table; combining the extracted sector index to calculate a corresponding PCIe target address; generating head data of a PCIe transaction layer data packet containing the target address and storing the head data into a register; if a plurality of continuous UALink data packets received correspond to the same target PCIe port ID, repeatedly using the head data in the register for data encapsulation to obtain a PCIe data packet; and sending the PCIe data packet to a memory through a PCIe port corresponding to the PCIe port ID.

This invention relates to the field of digital information transmission technology and discloses a four-way protocol conversion method for photovoltaic equipment, comprising: an Ethernet control chip receiving the original protocol message of the photovoltaic power station and writing it into the source protocol receive buffer; using a memory offset pointer to match the message delimiter to determine the dynamic byte offset of the payload data; constructing a three-segment descriptor chain based on the offset, including the physical base address of the target protocol header, the physical base address of the payload data, and the base address of the checksum; and a distributed direct memory access controller extracting and aggregating heterogeneous data across physical memory pages according to the descriptor chain to generate continuous target protocol frames. This invention uses data pointer routing to replace byte copying, eliminates the physical reassembly process at the end of the protocol conversion, reduces the transmission latency of concurrent scheduling instructions, ensures the exchange efficiency of heterogeneous digital information streams, and enhances the response performance of the station-end communication system.

This invention discloses an address mapping method and apparatus based on a non-transparent bridge and a mapping lookup table cache, relating to the field of address mapping technology. The method includes: receiving an access request from a first bus domain through a non-transparent bridge module; decomposing the target address into a page number and an intra-page offset through an address resolution module, and extracting access attributes; querying a mapping lookup table cache module based on the page number to determine the extraction method for the page-level mapping item; verifying the extracted page-level mapping item and access attributes; if a cache miss occurs but the verification passes, cache backfilling is performed; generating a local target address based on the target page base address and intra-page offset in the page-level mapping item; and forwarding the access request to a second bus domain connected to the non-transparent bridge module through an access forwarding module. This invention, after the access request enters the non-transparent bridge module, extracts the page number based on the request address and obtains the target address information through a lookup table, enabling rapid redirection of the access address.

A system includes a central processing unit; a first processing device; and a second processing device, and the first processing device (i) reads original data from the first memory, (ii) reads pre-processing information from the first base address register, (iii) executes a pre-processing operation on the original data using the pre-processing information to generate result data, and (iv) transmits the result data to second processing device without detouring via an external processor.

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.

The application relates to the chip technical field and proposes a memory access method and device, a chip and a computer readable storage medium, the method comprises the following steps: in response to a reset request, obtaining memory configuration information, the memory configuration information at least comprises a memory decoding mode bit and a memory access effective bit; based on the memory configuration information, determining an address decoding mapping relationship between a core and a memory block; according to the address decoding mapping relationship and the virtual address of the core, controlling the core to initiate memory access. According to the application, the mapping relationship between different memory blocks in the virtual addresses corresponding to various cores is determined based on the memory configuration information, and the core is controlled to initiate memory access according to the mapping relationship, so that the base address information of the memory block required by the core to be accessed and the offset address corresponding to the core do not need to be considered, programs can be compiled according to the base address of the system memory block, the difficulty of software compilation is reduced, the probability of bus conflict caused by improper configuration is reduced, and the efficiency of memory access is improved.

Embodiments of the present application disclose a page table creation method, a processor verification method, a device and an electronic device, and relate to the technical field of processor verification, and are invented to improve the efficiency of processor verification. The method comprises the following steps: determining a virtual address range to be converted according to a maximum access memory address required by a preset test code; applying for an address space required by each level of page table according to the virtual address range; initializing each level of page table to fill a base address of a next level of page table into a page table entry of a previous level of page table, and filling high bits of a virtual address into a page table entry of a last level of page table; wherein the high bits of the virtual address are bit positions of the virtual address except for page-in offset bit positions. The present application is suitable for verifying a processor.

The application provides a virtual machine data read-write method, which comprises the following steps: obtaining a data read-write request sent by a pass-through device, wherein the data read-write request comprises a virtual machine physical address of to-be-read-and-written data, the pass-through device is an external device of a virtual machine corresponding to the pass-through device; obtaining a device control table corresponding to the pass-through device according to the pass-through device, obtaining a virtual machine identifier and an input-output page table base address of the virtual machine through the device control table, and obtaining a configured input-output page table according to the input-output page table base address; obtaining a host physical address corresponding to the virtual machine physical address and encryption information of the host physical address according to the input-output page table, wherein the encryption information represents the encryption condition of a memory space corresponding to the host physical address; constructing an address data read-write request according to the encryption information, the virtual machine identifier and the host physical address, and sending the address data read-write request to a memory. The virtual machine data read-write method provided by the application can improve the security of data transmission.

The present disclosure provides a data transmission method, relates to the technical field of computers, in particular to the fields of data processing and heterogeneous computing technology, and the method comprises the following steps: in response to receiving a computing task for a device end, determining a target array structure called by the device end; obtaining descriptor information corresponding to the target array structure; extracting a base address and a shape parameter describing the target array structure from the descriptor information; constructing a device kernel function according to the base address and the shape parameter of the target array structure; and starting the computing task for the device end based on the device kernel function. The present disclosure also provides a data access method and device, an electronic device and a storage medium.