189 results about "Base address" patented technology

The invention provides an accelerator and a request processing method, which can be applied to the technical field of computers. The accelerator comprises: a computing unit configured to send an access request to a target virtual address to a memory management unit; the memory management unit comprises an address translation buffer module, and the memory management unit is configured to respond to the received access request and search a corresponding physical page number in the address translation buffer module according to the target virtual address so as to determine a physical address; wherein the address translation buffer module comprises a plurality of buffer units, and the address translation buffer module is configured to determine a target buffer unit from the plurality of buffer units according to a virtual base address in a target virtual address; and based on address identification information in the target virtual address, searching a physical page number corresponding to the target virtual address from physical page numbers corresponding to the at least two different virtual base addresses stored in the target buffer unit to determine a physical address.

The invention provides a processor supporting data multiplexing and instruction multiplexing, which is used for supporting multiplexing of operands and instructions of a previous calculation task in a later-executed calculation task, and realizes operand multiplexing and instruction multiplexing based on configuration information stored by a host control module connected with the processor. The processor comprises a configuration information caching module used for storing a storage offset and a storage offset use mark which are acquired from configuration information and correspond to each instruction in each calculation task; the base address dynamic generation module is used for storing a data cache index address of each calculation task and generating a real base address of each instruction in each calculation task; and the calculation module is used for acquiring an operand to execute each calculation task based on the real base address of each instruction in each calculation task generated by the base address dynamic generation module.

The embodiment of the invention provides a memory management method and related equipment, which are used for improving the persistence efficiency of memory access. Comprising the following steps: distributing a unique logic reference identifier for each object in the memory management system as a logic reference; dividing the plurality of objects according to the sequence of the logic reference identifiers, and storing the objects in one or more object groups; establishing a global ordered index table; wherein the global ordered index table comprises boundary information, and the boundary information comprises a maximum logic reference identifier and a physical base address; in response to an access request for the target logic reference identifier, executing primary addressing in the global ordered index table, and positioning a candidate object group containing the target logic reference identifier through a lower bound search algorithm; and executing secondary addressing in the candidate object group, calculating and obtaining the physical offset of the target object in the candidate object group according to the difference between the target logic reference identifier and the initial logic reference identifier of the corresponding candidate object group, and generating a target physical address.

The invention discloses a PCIe switch capable of modifying hardware configuration. The PCIe switch comprises at least one port, a message manager, a security manager and a configuration management module. Wherein each port is connected with a root complex, an application program runs on the root complex, the message managers are mapped in base address registers of the ports in a one-to-one correspondence mode and used for information exchange between the root complex and the security manager, and the security manager is in communication connection with the message managers and used for analyzing, verifying and replying messages of the root complex. And the configuration management module is in communication connection with the security manager, and configures the PCIe switch based on the configuration information. According to the PCIe switch, batch data transmission and information interaction between the root complex and the PCIe switch can be realized, and only the application subjected to authorization verification has the authority to modify the configuration, so that the PCIe switch can modify the configuration according to the application requirement on the root complex, and the PCIe switch is high in flexibility, safe, reliable and easy to expand.

Embodiments of apparatuses and methods for copying and operating on matrix elements are described. In embodiments, an apparatus includes a hardware instruction decoder to decode a single instruction and execution circuitry, coupled to hardware instruction decoder, to perform one or more operations corresponding to the single instruction. The single instruction has a first operand to reference a base address of a first representation of a source matrix and a second operand to reference a base address of second representation of a destination matrix. The one or more operations include copying elements of the source matrix to corresponding locations in the destination matrix and filling empty elements of the destination matrix with a single value.

The invention provides a PCIe (Peripheral Component Interconnect Express) endpoint device communication method, device and equipment based on software defined interconnection. The implementation scheme comprises the following steps: acquiring a communication request between endpoint devices; based on the bound queue pair relationship, applying for a point-to-point memory in a base address register space exposed by the receiving end, and determining a destination address corresponding to the communication request; according to the communication request and the destination address, the work queue element is issued to the bound queue pair, so that the endpoint device corresponding to the queue pair executes data handling; and generating a completion event associated with the communication request based on interruption information sent by the endpoint equipment, and pushing the completion event into a completion queue, so that a user reads and judges a transmission result through an event acquisition interface. According to the scheme, an end-to-end communication path can be communicated through a unified queue and event interface, the overall efficiency is improved while the bottom layer difference is shielded, high performance and low delay are ensured, reliability and restorability are enhanced, and good parallel expansion capacity is achieved.

The application provides a computer system and a multi-server shared storage system, which can be applied to the technical field of server storage. The computer system comprises: a computer system, a non-volatile memory and a plurality of servers which are electrically connected; an arbitration module is used for determining a target server according to a plurality of access signals of the plurality of servers, and sending an authorization signal to the target server and a bus buffer module; the bus buffer module is used for connecting a transmission bus between the target server and the non-volatile memory according to the authorization signal; in the case that a chip select signal in a flash signal is at an effective level, an access address is obtained from the flash signal, the access address is configured by using a configuration partition base address to obtain a target access address, signal conversion is performed on the target access address, a target flash signal is obtained and sent to the non-volatile memory, so that the non-volatile memory manages data stored in a storage partition corresponding to the target access address.

The invention relates to the technical field of dynamic instrumentation, in particular to a method and system for dynamically instrumenting a swan NEXT Native layer function. The method comprises the following steps: obtaining a process identifier of a target application process, and reading a corresponding memory mapping file to obtain a loading base address and a file path of a Native layer ELF shared object; an ELF file corresponding to the file path is read, and an index relation table of the target function symbol name of each item in the PLT section, the PLT item and the file offset of the PLT section is established; adding the loading base address and the file offset of the PLT section to calculate the initial address of the memory of the PLT section; and calculating the memory absolute address of the PLT entry of the target function according to the PLT entry of the to-be-intercepted function in the index relation table. According to the method, the index relationship between the symbol and the address is established by analyzing the memory mapping file and the ELF shared object file of the target process, and accurate function interception is realized at the PLT entry level.

The invention relates to the technical field of data storage, and particularly discloses an AWG waveform data storage method based on a DDR architecture, which comprises the following steps: waveform data storage configuration: performing logic hierarchical division on a DDR storage space, and configuring header information descriptors containing data length information for each waveform sub-block, classified storage and identification of test excitation waveform data are realized; and dynamic waveform scheduling: after the upper computer issues the initial base address of the unified waveform data block, the FPGA calculates the initial address of the waveform data of each channel according to the initial base address, and transmits the waveform data of each channel to the corresponding DAC unit in parallel in combination with the length of the waveform data to generate a test excitation waveform. The DDR storage space is logically divided into multi-channel independent areas, multi-waveform sub-blocks are divided in each area, and a special header information descriptor is matched, so that pre-storage and quick positioning of multiple test excitation waveforms are realized, and the limitation that a traditional scheme only supports a single test mode is solved.

The invention discloses a method, a product and a medium used in an AI accelerator chip, and the method comprises the steps: statically dividing a plurality of physical buffer areas in a shared memory of the AI accelerator chip according to a preset pipeline stage, and locking a base address of each physical buffer area in the plurality of physical buffer areas; analyzing calculation and memory allocation logic of operator blocks of the AI model, and inserting a synchronization token on one or more intermediate representation nodes of the AI model based on an analysis result, the synchronization token inserted into any intermediate representation node contains information about a synchronization dependency relationship of hardware operation represented by the intermediate representation node in a physical pipeline executed by a hardware engine in the AI accelerator chip; and generating a hardware instruction stream based on the intermediate representation of the AI model, and interleaving and rearranging instruction blocks in the hardware instruction stream based on a synchronization token inserted on one or more intermediate representation nodes.

The application discloses a file unshelling method and electronic equipment, and relates to the technical field of computer security, and comprises the following steps: inserting a probe at a target system call of a kernel, and injecting the probe into a target program; identifying a suspiciously shelled process through the target program; monitoring a memory permission change behavior performed by the suspiciously shelled process through the target program, and counting a permission change frequency of a memory region, an entropy value of the memory region and a call chain depth; when it is confirmed that the suspiciously shelled process is in an unshelling stage according to the permission change frequency, the entropy value and the call chain depth, writing data decrypted by the suspiciously shelled process into a target buffer through the target program; reading the data from the target buffer in a user mode, and recombining the data into a memory image according to a base address and a dirty page bitmap and writing the memory image back to a file. The method can avoid I / O bottlenecks caused by full memory dumping, reduce invalid data in the user mode, and reduce CPU occupation and memory bandwidth.

Disclosed are a method, product, and medium for use in an AI accelerator chip, the method comprising: statically dividing a plurality of physical buffers in a shared memory of the AI accelerator chip according to a preset number of pipeline stages, and locking a base address of each of the plurality of physical buffers; parsing computation and memory allocation logic of an operator block of an AI model, and inserting a synchronization token on one or more intermediate representation nodes of the AI model based on a result of the parsing, the synchronization token inserted on any one of the intermediate representation nodes containing information about a synchronization dependency relationship in a physical pipeline in which a hardware engine of the AI accelerator chip performs a hardware operation represented by the intermediate representation node; and generating a hardware instruction stream based on the intermediate representation of the AI model, and interleaving and rearranging instruction blocks in the hardware instruction stream based on the synchronization token inserted on the one or more intermediate representation nodes.

Embodiments of the present application relate to the technical field of computers, and provide a data prefetching method and apparatus, an electronic device, and a readable storage medium. The method comprises: determining a stride memory access instruction in a program to be processed, using an index value of the stride memory access instruction as a first index value, and updating, in a first record table, a record entry corresponding to a destination register of the determined stride memory access instruction from an initial value to the first index value; for any other memory access instruction in said program, when a target record entry of the other memory access instruction is not the initial value, determining the other memory access instruction as an instruction to be prefetched, and on the basis of the target record entry of the instruction to be prefetched, determining a base instruction corresponding to the instruction to be prefetched; and on the basis of the base instruction and a base address of the instruction to be prefetched, determining a prefetch address of the instruction to be prefetched, and prefetching data to be prefetched corresponding to the prefetch address into a cache, so as to implement data prefetching for indirect array-type memory access instructions.

Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

This invention provides an accelerator, a multi-accelerator system, and a data transmission method, applicable to the field of computer technology. The accelerator includes: a computing unit configured to generate communication instructions, each including a communication address and communication data; a communication module configured to receive the communication instructions from the computing unit, determine a buffer partition corresponding to the target accelerator based on the communication address in the communication instructions, and obtain a base address for the buffer partition; if the communication address is determined to be within an address window determined by the base address, store the communication data from the communication instructions in the buffer partition; in response to a triggered transmission condition, send the base address and multiple communication data stored in the buffer partition to a packet module; and a packet module configured to package the received multiple communication data based on the base address and send them to the target accelerator.

The embodiment of the invention discloses a Jailhome interrupt controller matching method and device, a server and a medium, and belongs to the technical field of interrupt. Comprising the following steps: acquiring GICR physical addresses, and generating a GICR physical address list; traversing the GICR physical address list, and recording the first GICR physical address; calculating a difference value between the adjacent first GICR physical address and second GICR physical address; judging whether the physical address of the first GICR and the physical address of the second GICR are continuous address spaces or not; when the address space is not the continuous address space, recording a second GICR physical address, and generating a GICR base address array; reading a GICR base address array, and mapping the GICR base address array into a GICR virtual base address array; and matching the GICR with a CPU (Central Processing Unit). Correct matching of the GICR and the CPU can be achieved, and accurate interruption of routing is achieved.

The invention discloses a processor, electronic equipment and a security service calling method, and belongs to the technical field of computers. A first register in the processor configured to store a base address of a security service jump table; a second register configured to store a plurality of index ranges, the plurality of index ranges pointing to different regions of the security service jump table; the secure operating system unit is configured to receive a calling instruction of a target security service and obtain a base address according to the calling instruction; determining a target index range of the calling instruction in the plurality of index ranges; and acquiring a jump address of the target security service according to the base address and the target index range, and executing the target security service according to the jump address of the target security service. By storing the plurality of jump addresses of the security service in the ePMP protection area, the security service can be newly added by expanding the number of the jump addresses in the ePMP area, and the extension flexibility of the security service can be improved.

This invention discloses a data aggregation auxiliary device, system, and data aggregation method. The PCIe controller of the aggregation auxiliary device receives UALink data packets from an external processor through each UALink port and forwards them to the converter, identifying the source ID corresponding to the UALink port. When aggregating the first UALink data packet, the converter parses the UALink data packet to extract the sector index and payload data, and stores the payload data in the payload buffer. Based on the corresponding source ID, the converter looks up the associated PCIe base address and sector size in a pre-built protocol conversion table. Combining the sector index, the converter calculates the corresponding PCIe target address, generates the PCIe TLP header data, and stores it in a register. When aggregating the next UALink data packet, the header data in the register is reused, significantly reducing the header overhead on the PCIe bus.

A system, processing apparatus, and method of operation of a processing apparatus are disclosed. The system includes a central processing unit, a first processing apparatus, and a second processing apparatus, and the first processing apparatus: (i) reads raw data from a first memory, (ii) reads pre-processing information from a first base address register, (iii) performs a pre-processing operation on the raw data using the pre-processing information to generate result data, and (iv) transfers the result data to the second processing apparatus without going through an external processor.

The application discloses an IoT firmware loading base address determination method based on pointer reference addresses, comprising the following steps: S1, dividing a complete file into pieces in a logical manner, and taking the starting position of each file piece as a file pointer locate[i]; S2, reading data with a fixed length from the pointer locate[i] of the current file piece by using a multithreading mechanism, and distinguishing data blocks from code blocks by using entropy values; S3, calculating the information entropy of binary data, adding the entropy values to an entropy value table entropy, and calculating the string address in the firmware file and the string address referenced by the pointer; S4, calculating the number of corresponding pointer reference addresses in the string address table, outputting the obtained result in descending order, and bringing the result into reverse analysis of the firmware to determine the base address. According to the number of pointer reference string addresses, the application realizes the identification of the firmware loading base address, and is suitable for the loading base address identification of firmware of various architectures.

The invention provides a page table preheating method and device, electronic equipment and a storage medium. The method is applied to a first processing device, the first processing device achieves memory management through a multi-level page table, and the method comprises the steps that under the condition that first instruction information used for page table preheating is received, the target page table level in the multi-level page table is determined according to the preheating level of the first instruction information; the first instruction information comprises a preheating level, a preheating base address and the number of preheating page tables; a page table preheating request is generated according to the preheating base address and the number of the preheating page tables, and the page table preheating request comprises a target base address of a target page table to be preheated in the target page table level; and under the condition that the target base address does not exist in the first cache space of the target page table level, performing page table translation processing on the target base address in the page table preheating request to obtain a page table translation result of the target base address, and storing the page table translation result in the first cache space. According to the embodiment of the invention, the system performance can be improved.

Certain aspects of the present disclosure provide techniques and apparatus that may be used to efficiently train address generation components of an indirect memory prefetcher (IMP). In some cases, logical shift operators and comparators may be used to determine an unknown size and base address used to generate a prefetch address.

Systems, methods, apparatuses, and computer program products for zero-copy symmetric multicast communication buffers for offload operations. A method may include receiving an instruction for performing a collective operation across a plurality of processing elements. The method may also include determining an offset of the first virtual address from a first base address associated with the first set of contiguous virtual addresses. The method may further include translating the first virtual address to a corresponding multicast virtual address based on the offset. Further, the method may include causing the collective operation to be performed based at least on the multicast virtual address.

The invention provides a data transmission method and device, a core particle and a graphics processor. The method comprises the following steps: receiving a first data access request sent by a local computing unit; wherein the first data access request comprises a plurality of access addresses; if it is judged that the plurality of access addresses do not belong to the local GSM space, calculating and obtaining a maximum addressing range based on the plurality of access addresses; if it is judged that the maximum addressing range is smaller than a preset value, address compression is conducted on the multiple access addresses, and multiple access compression addresses and base addresses are obtained; and generating a second data access request based on the plurality of access compression addresses and the base address, and forwarding the second data access request. The device is used for executing the method. According to the data transmission method and device, the core particle and the graphics processor provided by the embodiment of the invention, the plurality of access addresses are compressed, so that the transmitted data volume is reduced, and the data transmission efficiency is improved.

The embodiment of the invention provides a file caching method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: acquiring a request for caching a file, wherein the request for acquiring the cache file comprises a target name of a first cache file and an offset of the first cache file; obtaining a target base address from the index table according to the target name of the first cache file; determining a target index tree and an address of a second cache file in the target index tree in a memory pool according to the offset of the first cache file and the target base address; and performing read-write operation on the second cache file according to the address of the second cache file in the memory pool in the target index tree. The method is used for achieving the effects of dynamically expanding the capacity of the memory pool and caching data for multi-node sharing.

The present disclosure provides a method for PCIE data transmission. The method includes: determining whether the length of a PCIE data packet to be transmitted is less than a preset length; when it is determined that the length of the PCIE data packet is less than the preset length, performing data transmission on the PCIE data packet by means of a space of a base address register and a protocol converter; and when it is determined that the length of the PCIE data packet is greater than or equal to the preset length, performing data reading / writing on the PCIE data packet in a DMA manner. Therefore, the utilization rate of a PCIE bandwidth is improved, and the running reliability of a host is improved.

The embodiment of the invention provides a video memory access method, device, equipment and system and a computer storage medium. The method comprises the steps that a data access request sent by a first GPU is acquired, the data access request is used for accessing a video memory space of a second GPU, and the data access request comprises a virtual address of the first GPU; based on the data access request, a video memory window mapping table and an access page table are determined, and the video memory window mapping table comprises a mapping relation between a memory mapping input / output MMIO address of a base address register and a video memory address of the second GPU; the access page table comprises a mapping relation between the virtual address of the first GPU and the MMIO address; and accessing the video memory space of the second GPU based on the access page table and the video memory window mapping table. According to the embodiment of the invention, the direct access operation between the GPU video memories is effectively realized, and the data transmission delay is effectively reduced.

The invention discloses an RAG-based address information standardization processing method and apparatus. The method comprises the steps of determining first address information in text description information based on a large model; determining a first address vector corresponding to the first address information based on the RAG; determining a first similarity between the first address vector and at least one standard address vector in a standard address base, and determining at least one second address vector matched with the first address vector according to the first similarity; generating a cue word according to standard address information corresponding to at least one second address vector in a standard address library, and determining the second address information in the text description information based on the cue word and the large model; determining the semantic similarity between the second address information and at least one piece of address information with complete hierarchy, and determining third address information matched with the second address information according to the semantic similarity; and performing hierarchical completion on the second address information according to the third address information to obtain the target address information, thereby providing preconditions for accurate intelligence analysis.

This application discloses a page table generation method, apparatus, and electronic device for processor paging verification, relating to the field of processor technology, and is invented to simplify the page table generation process and reduce the cost of verification design. The method includes: obtaining the base address of the first-level page table of the current user process; determining the page frame number in each page table entry of the last-level page table based on the base address and each virtual address in the virtual address range of the current user process; the page table having a mapping relationship between the virtual address range and the physical address verification space; and updating the page frame number in the first page table entry of the last-level page table to the second page table entry of the last-level page table to generate a new page table. This application is applicable to processor paging verification.

The present disclosure relates to a method of accessing a n-dimensional tensor of elements in a memory by a computer system. The multidimensional tensor comprises two-dimensional arrays, herein referred to as pages, each page being configured to comprise a predefined number of one-dimensional arrays of elements, herein referred to as sticks. The method includes linearly loading page per page of the tensor, and doing the following for each page: loading the non-empty sticks of the page from the memory using a base address of the page and determining a base address for the subsequent page using the number of loaded sticks and using an address offset indicative of potential empty sticks of the page. In case the number of loaded pages reaches a chunk size, the chunk page counter may be reinitialized and the linear loading may be continued with a subsequent page.