774 results about "Base address" patented technology

An Internet directory system and method that is based on user telephone number addressing. The system includes an interactive white and yellow pages directory that is based on telephone numbers. Thus, a user's telephone number is a unique identifier used to key other information within the directory. The telephone number may also be used as the primary component of an email address, domain name, or web site URL for the user. The use of a telephone number as the primary component of an e-mail address or domain name greatly simplifies the process of locating a user. E-mail addresses and domain names may be readily found using standard telephone information services, such as "411", as well as other telephone-based methods for obtaining telephone directory information. This Internet directory system and method brings all communication methods and directory services together using one searchable key, a user's telephone number. The directory entry page may be created, edited and updated by the subscriber using simple html editing or using a voice telephone call or via fax, without the use of a personal computer. Thus, the present invention provides an open directory model wherein the end users construct the directory, and the directory is "living", i.e., dynamically changeable and updateable. The power of the directory is thus placed in the users' hands. The telephone based Internet directory system of the present invention also provides addressing for unified messaging as well as locality in addressing.

Methods and systems are provided for providing network services using at least one processor, such as a network operations center that interfaces a base network. The network operations center may receive information identifying a user authorized to administer a first processor, which may be separate from the network operations center, and a base address that is routable in the base network. The network operations center may provide through the base network code and information for self-configuring the first processor as a gateway that interfaces the base network at the base address. The first processor may execute the provided code to self-configure itself as the gateway based on the provided information. The network operations center may then provide through the base network to the first processor additional information enabling at least one tunnel through the base network to a second processor, which may also be separate from the network operations center, when the first and second processors each provide to the network operations center a consent for enabling the tunnel.

Methods and systems are provided for enabling a virtual network between a first processor and a second processor using at least one additional processor separate from the first processor and the second processor. In one embodiment, the at the at least one additional processor may determine a first virtual address and a first base address for the first processor such that the first virtual address is routable through the virtual network and the first base address is routable through a base network and determine a second virtual address and a second base address for the second processor such that the second virtual address is routable through the virtual network and the second base address is routable through the base network. The at least one additional processor may provide the first virtual address and the first base address to the first processor and the second virtual address and the second base address to the second processor. Moreover, the virtual network may be enabled over the base network based on the first virtual address, the first base address, the second virtual address, and the second base address.

A bookmark transfer mechanism allows a user to transfer bookmark information from a primary computer to an alternate computer to customize a bookmarks menu on a web browser displayed on the alternate computer. The alternate computer prompts the user for a base address which is used by the web browser on the alternate computer to locate the primary computer where bookmark information is stored. The base address should correspond to a primary computer that has been configured for automatic download of bookmark information. Once the primary computer is located, the alternate computer transfers the base address and prompts the user for security information. The alternate computer then delivers the security information to the primary computer. The primary computer then authenticates the security information. If the security information is not valid, the primary computer delivers an error message to the alternate computer indicating that access to the primary computer has been denied. If the security information is valid, the primary computer transfers the bookmark information to the alternate computer. If necessary, the alternate computer translates the received bookmark information to the proper web browser format and updates the bookmarks menu on the web browser to include the transferred bookmark information. The bookmark information may be either temporarily or permanently incorporated into the web browser.

A hash function used for content addressing is different from the hash function used for content verification. Adding a file to a database involves storing both hash function values in a table as pair. Verifying the integrity of a file believed to be a duplicate in a database, or when retrieving a file, makes use of the verification hash function. Files can be continuously checked. A multi-level database can be used. A second hash function can be added to an existing system. A verification hash function can be upgraded and more than one content verification hash function can be used. In a variation, a random number generator is used instead of a hash function for content addressing; the verification hash function is also used. Files addressed using a random number are added or retrieved from a database and their verification hash values are checked. Time stamps and digital signatures are used for security.

An on-line reorganization facility (ORF) uses index data-spaces that point to other data-spaces, referred to as data data-spaces, to efficiently track and coordinate information about the data-elements in an original data-space operated upon by a reorganization process. A relative base address of a data-element in an index data-space can be derived from a relative base address of a data-element in an original data-space, and vice versa. An index data-space data-element contains a location of a data-element in a data data-space that tracks change information related to a corresponding data-element in the original data-space. Tracked changes are later applied to the newly reorganized data-space to assure consistency and integrity of the data. Tracked changes include the location in the original data-space where the change occurred and a flag indicting the type of change.

A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a multiple memory pages. The memory management unit includes a security check receiving a physical address within a selected memory page, and security attributes of the selected memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain an additional security attribute of the selected memory page. The security check unit generates a fault signal dependent upon the security attributes of selected memory page and the additional security attribute of the selected memory page. The security attributes of the selected memory page may include a user/supervisor (U/S) bit and a read/write (R/W) bit as defined by the ×86 processor architecture. The one or more security attribute data structures may include a security attribute table directory and one or more security attribute tables. The security attribute table directory may include multiple entries, and each entry of the security attribute table directory may include a present bit and a security attribute table base address field. A central processing unit (CPU) is described including the memory management unit (MMU), and a computer system is disclosed including the CPU. A method is described for providing access security for a memory used to store data arranged within multiple memory pages.

In one embodiment, an input/output memory management unit (IOMMU) comprises a control register configured to store a base address of a set of translation tables and control logic coupled to the control register. The control logic is configured to respond to an input/output (I/O) device-initiated request having an address within an address range of an address space corresponding to a peripheral interconnect. One or more operations other than a memory operation are associated with the address range, and the control logic is configured to translate the address to a second address outside of the address range if the translation tables specify a translation from the address to the second address, whereby a memory operation is performed in response to the request instead of the one or more operations associated with the address range.

A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be to transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction address is stored in the RISC branch link register. The general-purpose registers (GPR's) are also merged together, allowing a CISC program to pass data to a RISC program merely by writing one of its GPR's, switching control to the RISC program, and the RISC program reading one of its GPR's that is merged with and corresponds to the CISC GPR that was written to by the CISC program.

A method and apparatus is provided to populate a caller's information to a host-based address book automatically or by a single click on a virtual button included in a popup window or by a series of simple commands.

An online system and a method for a web-based address book that allows collaborative updating and synchronization of the listed persons' contact information. The method includes creating profile templates for each person within a group and storing these profile templates in a central database. Next, populating the profile templates with publicly available basic information and then publishing the public profile information in the web-based address book. Users login into the address book website, update their own profile information and upload their personal address book. The system then cross-correlates and matches contact information retrieved from users' personal address books to the contact information listed in other persons' profiles.

Disclosed is a system for dynamically assigning alias addresses to base addresses referencing an I/O device, such as a direct access storage device (DASD). In the system, at least one base control block indicates a base address and a plurality of alias control blocks indicate a plurality of alias addresses. Each control block is associated with an address for addressing an I/O device. A processing unit, such as a host computer system, processes at least one alias control block associated with the I/O device and determines a base control block associated with the I/O device with which the alias control blocks are associated. The processing unit then binds at least one alias control block to the determined base control block. The bound base and alias control blocks provide different addresses to address the same I/O device. Further, the bound base and alias addresses address the same I/O device for subsequent I/O operations until the processing unit detects a reassignment of the association of base and alias addresses.

A memory block with any source alignment is streamed into general-purpose registers (GPRs) as aligned data using a streaming load instruction. A streaming store instruction reads the aligned data from the GPRs and writes the data into memory with any destination alignment. Data is streamed from any source alignment to any destination alignment. Memory accesses are aligned to memory lines. The data is rotated using the offset within a memory line of the base address. The rotated data is stored in a scratch register for use by the next streaming load instruction. Rotated data just read from memory is combined with rotated data in the scratch register read by the last streaming load instruction to generate result data to load into the destination GPR. Streaming condition codes are set when the block's end is detected to disable future streaming instructions. Aligned memory accesses at full bandwidth read the un-aligned block.

A method and system for filtering and/or handling operating system (OS) runtime exceptions using firmware-based components. OS-based exception handling components and corresponding pointers, as applicable, are set up in a conventional manner during the OS load. The OS-based components are then physically or logically relocated (moved from a physical to virtual address in one embodiment, re-referencing a base address for the OS-based components in another embodiment) and physically or logically replaced with corresponding firmware-based exception filters/handler components. In response to a runtime exception, the execution stream (i.e., instruction pointer) is vectored to a firmware-based exception filter/handler that performs exception filtering and/or handling for the exception. Upon completion, the execution stream may be re-vectored to a corresponding OS-based exception handler. A firmware-based exception filter/handler may be used to augment an OS-based exception handler, or replace it.

Disclosed is an Internet-based address book that enables individuals (“users”) or (“members”) to use people (“contacts”) from their address book for event planning, purchasing gifts, marketing, and anything else anyone dreams up. The system includes the following modules: an address book whose information can be utilized by any client for any purpose, a full-fledged event planner suitable for planning formal events such as weddings, a marketing module that allows people to refer products and information to people who would be interested, and a recipient transaction module that makes recipient-based transactions such as gifts and money transfer assessable and convenient. Features of the event planner include automatic generation and reprinting of invitations, placement cards, and thank-you cards with proper etiquette. Features of the marketing module includes the ability (a) to restrict the contacts that can be marketed to based on demographics, negative feedback, missing requisite information, or other reasons, (b) to reward users that market merchandise to their contacts with a discount on the merchandise itself, and (c) to bundle all the marketing sent by all users to one contact and deliver it as a single consolidated information package. Features of the recipient transactions module include the ability to (a) send one person a gift through postal mail or email, (b) send many people a gift, and (c) allow many people to purchase a single gift together.