2721 results about "Memory block" patented technology

The invention relates to the technical field of PC (Personal Computer) terminal AI (Artificial Intelligence) computing, and discloses a method and a system for dynamically scheduling generative AI heterogeneous computing resources of a PC terminal. The system comprises a resource state acquisition module, a scheduling graph generation module, a resource fluctuation entropy analysis module and a scheduling decision engine module. The resource state acquisition module captures running state parameters of a GPU kernel, a CPU thread and a memory block in real time, and generates a resource state feature tensor through normalization processing; the scheduling atlas generation module analyzes and computes the node connection topology, extracts the correlation between the devices, and constructs a multi-dimensional scheduling atlas; the resource fluctuation entropy analysis module separates the load feature vectors, calculates the entropy of each calculation unit and generates a heterogeneous resource entropy matrix; and the scheduling decision engine module jointly analyzes the atlas and the matrix, identifies bottleneck node resource competition characteristics, generates a dynamic scheduling instruction set, adapts to generative AI task requirements, and ensures efficient and stable operation of the task.

The invention relates to the technical field of data transmission, and provides a data transmission method and device, electronic equipment, a storage medium and a program product.The method comprises the steps that resources needed by RDMA are initialized, and the initialization process comprises the steps of creating a registration memory of the RDMA and creating a plurality of work queue pairs according to different data transmission logics of a target data packet to be transmitted, each work queue pair corresponds to one data transmission logic; dividing a data buffer area in the registered memory into memory blocks with preset sizes; writing the to-be-transmitted target data packet into a data buffer area by taking a memory block as a unit; and selecting the corresponding target working queue based on the data transmission logic of the to-be-transmitted target data packet, and sending the to-be-transmitted target data packet in the data buffer area to an opposite end, or receiving data of the opposite end to the data buffer area. According to different data transmission logics, different working queues are selected to complete operation on the logic channels serving as data transmission, multiple pieces of data are transmitted in parallel, and transmission delay is reduced.

A data storage device includes a first partition having memory blocks of a first type and a second partition having memory blocks of a second type. The second partition also includes hybrid memory blocks. A storage balancing system monitors a state of each partition and determines whether to initiate a garbage collection process. The storage balancing system also determines whether hybrid memory blocks, if included in the garbage collection process, are replaceable by allocating memory blocks of the second type as new hybrid memory blocks. If the storage balancing system determines the hybrid memory blocks are not replaceable, the storage balancing system dynamically determines a ratio of memory blocks of the first type and hybrid memory blocks to include in the garbage collection process.

A memory device and a method of operating the memory device include setting a read voltage to be applied to a selected word line among word lines connected to a memory block and setting a first pass voltage to be applied to an adjacent word line adjacent to the selected word line among the word lines. The method also includes applying the first pass voltage to the adjacent word line and applying the read voltage to the selected word line. The first pass voltage is set higher than a reference pass voltage when the read voltage is lower than a reference voltage. The first pass voltage is set lower than the reference pass voltage when the read voltage is higher than the reference voltage.

A memory system, an operation method thereof and a readable storage medium are provided according to examples of this disclosure. The memory system including: a memory device including a plurality of memory blocks, each of which including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; a memory controller coupled to the memory device and configured to: acquire a read retry voltage with both a first-type read retry table and a second-type read retry table; control the memory device to perform a read retry operation with the read retry voltage.

Systems and methods for efficient memory management during ray tracing are described. A ray tracing system assigns a memory stack to a ray. The ray, when intersection tested against objects of a node, accesses data that is stored in the memory stack. When data is to be consumed from the memory stack by the ray, the ray tracing system uses a memory pointer associated with the ray to locate the requested data. When data is to be stored to the memory stack, the memory allocation circuitry stores data in a free memory block and uses a linked list to link the memory block with other memory blocks storing additional data for the ray.

The present application belongs to the technical field of data processing and relates to a network message processing method and apparatus, and a computer device and a storage medium. The method comprises: on the basis of a received target network message, acquiring a target memory block from a pre-constructed shared memory pool, so as to generate a message memory; on the basis of a network-interface-card driver, performing first identification processing on the target network message, so as to obtain a target network message descriptor; on the basis of the target network message descriptor, performing second identification processing on the message memory, so as to obtain a first socket buffer; and performing parsing processing on the first socket buffer by means of a network protocol stack, and on the basis of a parsing processing result, reading network message data from a virtual memory corresponding to the message memory, so as to complete the processing of the network message. In the present application, on the basis of a constructed shared memory pool, zero-copy network packet reception can be realized during network message processing, thereby avoiding performance loss caused by the memory copy of messages.

The invention relates to an edge duplicate removal and privacy protection entrusted audit management method and system for the Internet of Things. The method comprises the following steps: an Internet of Things device issues an audit task announcement, and a target fog node obtains a delegation key by negotiating with the device; the equipment performs block and partition processing on original data, encrypts the original data by using an AES (Advanced Encryption Standard) by using an MLE key and sends the encrypted data to a target fog The fog node uses the delegation key to generate a block label, and the block label is compared with a storage block label to remove repeated blocks; in the auditing stage, the fog node generates a random challenge and sends the random challenge to the cloud server, the cloud server generates a corresponding integrity proof and sends the integrity proof to the target fog node for validity verification, and the target fog node creates an auditing log and uploads the auditing log to the block chain for the Internet of Things device to view. The original data is encrypted by using the MLE key, so that the data privacy is protected; by entrusting label calculation, deduplication operation and auditing to the fog node, offline auditing of the equipment can be realized, and the calculation burden of the equipment can be reduced.

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

The present application relates to the field of cloud technology, and discloses a metadata access method and apparatus, a device, and a storage medium. According to the method, a global metadata cache scheme is used, and relates to a three-layer architecture, i.e., a global cache file, a cache description array, and a memory block; storage areas can be divided according to the data length of metadata in a shared memory; and when target metadata needs to be acquired for a target process, metadata can be queried layer by layer according to the three-layer architecture until target address information of target metadata that has been cached is obtained, and the target address information is returned to the target process for realizing the access of the target metadata. In this way, the metadata required by all the working processes can be accessed by means of the method, so that metadata caches of the working processes do not need to be respectively maintained by the working processes, thereby reducing the repeated metadata cache between the working processes, reducing the occupied memory resources, reducing the transmission resource occupation of the repeated metadata, and improving the resource utilization rate.

The embodiment of the invention provides an early failure test method for flash memory particles, a controller and a storage medium, and the method comprises the steps: placing the flash memory particles in a test space, and adjusting the space temperature of the test space to a first test temperature; performing multiple rounds of testing on the flash memory particles according to different block states, target modes and target read-write behaviors at the first test temperature, and writing test data into a test result; reducing the space temperature from the first test temperature to a second test temperature; performing multiple rounds of testing on the flash memory particles according to different block states, target modes and target read-write behaviors at a second test temperature, and writing test data into a test result; and writing the test result into a bad block table, wherein the bad block table is used for recording the position information, the failure reason and the reliability level of the failure storage block. According to the embodiment of the invention, the blocks with poor performance are screened out by means of multiple rounds of experiments in different scenes, different modes and different read-write behaviors, so that the quality reliability of products is improved.

The invention discloses a number-theory transformation structure of concurrency constant geometry, which uses two polynomial storage blocks to store polynomials, namely a left storage block MembL and a right storage block MembR, each of the left storage block MembL and the right storage block MembR consists of four 1024 * 24 single-port SRAMs (Static Random Access Memory), and n is an integer multiple greater than or equal to 16; and parallel computing of the two butterfly arithmetic units is realized through the four multiplexers, and position transformation of input and output data of the BFU is controlled. To be compatible with multiple algorithms, there is a need for an additional number-theoretical transform constant memory to store a pre-computed twiddle factor to provide a required twiddle factor access bandwidth. According to the method, data independence between polynomial storage blocks is utilized, a modular arithmetic unit of a two-concurrence BFU is designed, and the polynomial multiplication performance is improved by more than one time under the condition that the area increase is limited.

A metadata access method, apparatus, and computer-readable storage medium for efficient metadata retrieval through cache management. The method receives metadata query requests including target index information from processes and performs matching operations on a global cache file containing records with index information and slot identifiers. Each cache description array corresponds to memory blocks caching metadata. Upon successful matching, the target cache description array is accessed using the target slot identifier. The data state of target metadata is determined from the cache description array, and target address information indicating the location of the target memory block in shared memory is obtained and returned to the requesting process, enabling efficient shared memory-based metadata access.

The invention relates to the technical field of printing task scheduling, in particular to a printing task scheduling method and system based on a main control chip and a terminal, and the method comprises the steps of initial task classification, dynamic priority adjustment, task queue recombination, resource allocation execution, termination mechanism triggering and the like. The high-priority task response speed is optimized through system load monitoring and a waiting time coefficient, and a real-time task pool and an elastic buffer pool are divided to improve the scheduling efficiency. According to the method, the real-time task pool and the elastic buffer pool are divided through an algorithm of'dynamic memory pool partitioning + task life cycle binding ', and the memory blocks are pre-allocated according to the task types, so that the real-time performance and the scheduling efficiency of the high-concurrency printing tasks are improved, rapid response of high-priority tasks can be realized, delay of key tasks is reduced, and the efficiency of the high-concurrency printing tasks is improved. The resource utilization rate and the scheduling fairness are improved, and the method is suitable for high-concurrency printing scenes.

In an example method of operating a nonvolatile memory device, an erase command and a block address designating a target memory block from a plurality of memory blocks are received. Whether the target memory block is an open block including at least one erased word-line is determined based on the erase command and the block address. A pre-program voltage having a first voltage level is applied to word-lines of the target memory block during pre-program period of a erase loop based on the target memory block being a closed block including only programmed word-lines. A pre-program voltage having a second voltage level greater than the first voltage level is applied to a portion of a region, including the at least one erased word-line, of the target memory block during the pre-program period based on the target memory block being the open block.

Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.

Blockchain environments may mix-and-match different encryption, difficulty, and / or proof-of-work schemes when mining blockchain transactions. Each encryption, difficulty, and / or proof-of-work scheme may be separate, stand-alone programs, files, or third-party services. Blockchain miners may be agnostic to a particular coin's or network's encryption, difficulty, and / or proof-of-work schemes, thus allowing any blockchain miner to process or mine data in multiple blockchains. GPUs, ASICs, and other specialized processing hardware components may be deterred by forcing cache misses, cache latencies, and processor stalls. Hashing, difficulty, and / or proof-of-work schemes require less programming code, consume less storage space / usage in bytes, and execute faster. Blockchain mining schemes may further randomize byte or memory block access, further improve cryptographic security.

The embodiment of the invention provides a memory management method and electronic equipment, which are applied to wearable equipment. When a first application in the wearable device is started, a plurality of memory areas are allocated to the first application in advance according to the first configuration information. Each memory area corresponds to a preset capacity, a plurality of memory blocks are arranged in the memory area, and the memory capacity of the memory blocks is equal to the preset capacity. In the running process of the first application, when the memory is applied, appropriate memory blocks can be matched from a plurality of memory areas, and address information of the memory blocks is returned. The capacity of the memory block is greater than or equal to the capacity required for applying for the memory, and the memory block is in an idle state. Therefore, by planning and managing the memory in advance, the memory address information can be returned at an extremely high speed when the first application applies for the memory. Particularly, under the scenes that equipment hardware resources are limited and the first application frequently applies for the memory in a short time, the time consumed by memory application can be remarkably shortened, and the application running efficiency is improved.

The invention relates to an automatic memory protection method and device, computer equipment and a storage medium, and the automatic memory protection method comprises the steps: responding to a real-time memory read-write instruction, and determining a target memory address corresponding to the memory read-write instruction; determining a pre-stored tag value corresponding to the target memory address and an actual tag value currently embedded in a memory block pointed by the target memory address; and when it is detected that the pre-stored tag value is not matched with the actual tag value, stopping a memory operation associated with the memory read-write instruction. Through the method and the device, the problem that the data-oriented attack cannot be effectively prevented is solved, the data-oriented attack is effectively prevented, and the memory security and the system operation efficiency are improved.

The embodiment of the invention provides a reliability testing method for flash memory particles, a readable storage medium and computing equipment, the flash memory particles are divided into a plurality of storage blocks, each storage block comprises a plurality of word lines arranged in sequence, and the method performs the following operations for each storage block: erasing data in the storage block; data are written into the storage pages connected with the word lines at intervals of any number of word lines from a starting word line, and the starting word line is a word line which is not selected; reading the data from the storage page connected with the word line in which the data is written and verifying the data; if the error data proportion is larger than or equal to the error bit threshold value, the storage block is marked as a bad block, and if the error data proportion is smaller than the error bit threshold value, the step of erasing the data in the storage block is skipped to be executed. According to the method, the bad block screening capability in the reliability test is improved by changing the data writing mode.

A contact center system. The contact center system comprises a node comprising a plurality of modules (e.g., microservices), each module comprising a shared memory module (e.g., shared memory library), wherein the shared memory module is configured to: obtain a shared memory key; obtain a shared memory segment identifier (smhid) using the shared memory key, the shared memory segment identifier identifying a shared memory segment; use the shared memory segment identifier to attach to the shared memory segment, wherein, for each of a plurality of memory block sizes, the shared memory segment stores information pertaining to a recycle list, and the plurality of memory block sizes comprises a first memory block size and a second memory block size that is greater than the first memory block size.

Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory blocks, each including a plurality of memory cells configured to store data, and a memory controller in communication with the memory device and configured to 1) determine a write mode of a memory block of the memory device to be either a first write mode in which one data bit is stored in a memory cell of a memory block or a second write mode in which a plurality of data bits is stored in a memory cell based on a temperature of the storage device and a number of read reclaim operations that have been performed in the memory block and 2) control the memory device to perform a write operation in the determined write mode.

Provided are a universal flash storage (UFS) device for preventing a replay attack, a method of operating the same, and a UFS system. The UFS device including: a memory including a replay protection memory block (RPMB) region, the RPMB region including one or more index fields storing a second write failure index; and a memory controller including at least one controller memory storing one or more instructions, wherein the memory controller is configured to execute the one or more instructions to cause the UFS device to: receive, from an external device, an RPMB write request including a first write failure index, meta information, and a first message authentication code generated based on the first write failure index and the meta information, and determine whether to perform an authentication operation on the external device based on the first write failure index and the second write failure index.

The invention relates to a data processing method and device, computer equipment, a computer readable storage medium and a computer program product. After first matrix data is obtained, tensor data to be processed are obtained, and the tensor data are distributed to a plurality of calculation units; calculating a local feature value corresponding to the target calculation unit according to the local tensor data allocated to the target calculation unit; dividing the target calculation unit into data blocks corresponding to the number of the plurality of calculation units; according to the serial number of the data block, mapping the local feature value recorded in each data block to a target storage block of a target memory until the local feature value in each calculation unit is distributed to the corresponding storage block in the target memory, and obtaining a global feature value table; according to the global feature value table, feature value calculation is carried out to determine the target feature value, conflict-free parallel calculation is achieved, the utilization rate of calculation resources is increased, and the data processing efficiency is improved.

The invention discloses a multi-view collaborative 3D Gaussian splash optimization method and system, and the method comprises the steps: constructing a multi-level heterogeneous video memory pool, and dynamically dividing a video memory in 3D Gaussian reconstruction into a view exclusive memory block and a global shared memory pool; a mixed rendering-gradient pipeline is designed, and hardware-level pipeline parallelism in 3D Gaussian reconstruction is realized through a double-buffer asynchronous switching mechanism based on a CUDA Warp-level parallel primitive fusion forward rendering and back propagation thread group; performing multi-view gradient joint optimization, screening an effective gradient path in 3D Gaussian reconstruction based on the visibility mask matrix, and performing projection error weighted fusion on a multi-view gradient tensor; and implementing a multi-modal densification decision, generating a 3D Gaussian candidate splitting position in 3D Gaussian reconstruction through Monte Carlo sampling, calculating a joint optimization objective function by combining a multi-view projection residual error and a gradient contribution factor, and finally realizing 3D Gaussian reconstruction. According to the invention, high-precision and low-delay large-scale scene real-time rendering and training can be realized.

The invention belongs to the technical field of routers, and particularly relates to an efficient SRAM (Static Random Access Memory) cache allocation and management system of an on-chip network router, which comprises an input decoding module, a buffer module, a data writing module, an SRAM module and a data reading module, the data writing module is used for writing the data packet into the SRAM module according to a chain table number distribution and recovery strategy; the SRAM module is used for storing the data packet in a specified memory block according to a memory allocation and recovery strategy; the data reading module is used for reading a corresponding data packet from the SRAM module according to a priority queue arbitration strategy; and the signal is transmitted to the output port. The priority queue arbitration strategy is adopted to ensure the priority output of high-priority data packets, the throughput and response time of the system are improved, and the method is particularly suitable for a high-load, multi-port and high-concurrency network environment.

A system and related method, including system memory with a source memory block and a destination memory block each of a memory block size, a first volatile memory and a second volatile memory, each of a volatile memory size. The system includes processing circuitry to receive a garbage collection request associated with the destination memory block. The processing circuitry then determines whether the memory block size is greater than the volatile memory size and pauses data change operations but allows for passive operations to continue. While data change operations are paused the processing circuitry loads a first portion of data of the source memory block to the first volatile memory and a second portion of the data to the second volatile memory. The processing circuitry writes each portion of data from the volatile memory to the destination memory block to complete garbage collection and unpauses the data change operations.

Methods, devices, and systems for managing layouts of semiconductor structures in memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory block, and the second semiconductor structure includes a driver circuit. The first semiconductor structure and the second semiconductor structure are stacked along a first direction. The driver circuit at least partially overlaps with the first memory block in a plan view perpendicular to the first direction.

The application provides a cache manager and a control component. The cache manager comprises an interface, an allocation module and a memory. The interface receives a cache allocation request and sends the cache allocation request to the allocation module. The interface receives first cache index information returned by the allocation module and outputs the first cache index information. In response to the cache allocation request, the allocation module allocates N idle memory blocks and generates the first cache index information. The memory blocks are located in a cache, N is a positive integer, and the first cache index information comprises indexes of the N memory blocks. The memory stores indexes of at least N memory blocks. The cache manager implemented by hardware replaces the software management cache in the prior art, thereby reducing the interaction times between software and hardware when allocating a cache in the control component, improving the information interaction speed inside the control component, and achieving the technical effect of reducing the data transmission time between the host and the flash memory chip.