1609 results about "Memory block" patented technology

The invention relates to the technical field of PC (Personal Computer) terminal AI (Artificial Intelligence) computing, and discloses a method and a system for dynamically scheduling generative AI heterogeneous computing resources of a PC terminal. The system comprises a resource state acquisition module, a scheduling graph generation module, a resource fluctuation entropy analysis module and a scheduling decision engine module. The resource state acquisition module captures running state parameters of a GPU kernel, a CPU thread and a memory block in real time, and generates a resource state feature tensor through normalization processing; the scheduling atlas generation module analyzes and computes the node connection topology, extracts the correlation between the devices, and constructs a multi-dimensional scheduling atlas; the resource fluctuation entropy analysis module separates the load feature vectors, calculates the entropy of each calculation unit and generates a heterogeneous resource entropy matrix; and the scheduling decision engine module jointly analyzes the atlas and the matrix, identifies bottleneck node resource competition characteristics, generates a dynamic scheduling instruction set, adapts to generative AI task requirements, and ensures efficient and stable operation of the task.

A metadata access method, apparatus, and computer-readable storage medium for efficient metadata retrieval through cache management. The method receives metadata query requests including target index information from processes and performs matching operations on a global cache file containing records with index information and slot identifiers. Each cache description array corresponds to memory blocks caching metadata. Upon successful matching, the target cache description array is accessed using the target slot identifier. The data state of target metadata is determined from the cache description array, and target address information indicating the location of the target memory block in shared memory is obtained and returned to the requesting process, enabling efficient shared memory-based metadata access.

Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.

The invention relates to a data processing method and device, computer equipment, a computer readable storage medium and a computer program product. After first matrix data is obtained, tensor data to be processed are obtained, and the tensor data are distributed to a plurality of calculation units; calculating a local feature value corresponding to the target calculation unit according to the local tensor data allocated to the target calculation unit; dividing the target calculation unit into data blocks corresponding to the number of the plurality of calculation units; according to the serial number of the data block, mapping the local feature value recorded in each data block to a target storage block of a target memory until the local feature value in each calculation unit is distributed to the corresponding storage block in the target memory, and obtaining a global feature value table; according to the global feature value table, feature value calculation is carried out to determine the target feature value, conflict-free parallel calculation is achieved, the utilization rate of calculation resources is increased, and the data processing efficiency is improved.

The invention discloses a multi-view collaborative 3D Gaussian splash optimization method and system, and the method comprises the steps: constructing a multi-level heterogeneous video memory pool, and dynamically dividing a video memory in 3D Gaussian reconstruction into a view exclusive memory block and a global shared memory pool; a mixed rendering-gradient pipeline is designed, and hardware-level pipeline parallelism in 3D Gaussian reconstruction is realized through a double-buffer asynchronous switching mechanism based on a CUDA Warp-level parallel primitive fusion forward rendering and back propagation thread group; performing multi-view gradient joint optimization, screening an effective gradient path in 3D Gaussian reconstruction based on the visibility mask matrix, and performing projection error weighted fusion on a multi-view gradient tensor; and implementing a multi-modal densification decision, generating a 3D Gaussian candidate splitting position in 3D Gaussian reconstruction through Monte Carlo sampling, calculating a joint optimization objective function by combining a multi-view projection residual error and a gradient contribution factor, and finally realizing 3D Gaussian reconstruction. According to the invention, high-precision and low-delay large-scale scene real-time rendering and training can be realized.

Methods, devices, and systems for managing layouts of semiconductor structures in memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory block, and the second semiconductor structure includes a driver circuit. The first semiconductor structure and the second semiconductor structure are stacked along a first direction. The driver circuit at least partially overlaps with the first memory block in a plan view perpendicular to the first direction.

The application provides a cache manager and a control component. The cache manager comprises an interface, an allocation module and a memory. The interface receives a cache allocation request and sends the cache allocation request to the allocation module. The interface receives first cache index information returned by the allocation module and outputs the first cache index information. In response to the cache allocation request, the allocation module allocates N idle memory blocks and generates the first cache index information. The memory blocks are located in a cache, N is a positive integer, and the first cache index information comprises indexes of the N memory blocks. The memory stores indexes of at least N memory blocks. The cache manager implemented by hardware replaces the software management cache in the prior art, thereby reducing the interaction times between software and hardware when allocating a cache in the control component, improving the information interaction speed inside the control component, and achieving the technical effect of reducing the data transmission time between the host and the flash memory chip.

The invention discloses a VLA model autonomous generalization method, system and device and a medium, and belongs to the technical field of robot control. The method comprises the steps of obtaining visual observation data and natural language task description of a current environment of a robot, generating an action sequence and controlling the robot to execute tasks; track data in the task execution process are collected, and token-level dense rewards and structured reflection information are output; storing the trajectory data, the token-level dense reward and the structured reflection information into a double-memory block; extracting task priori from the long-term memory by using an experience-driven generator, and generating trajectory data containing a sub-target chain; updating the VLA strategy model by using a reinforcement learning algorithm based on the token-level dense reward; and updating the VLA strategy model by using a supervised fine tuning algorithm based on the high-quality track data set. According to the method, the technical problem of autonomous generalization of the VLA model is solved.

The invention relates to the technical field of embedded systems, in particular to a memory management method for dynamic allocation of an operating system and a storage medium, and dynamic memory management is realized by transforming a memory allocation interface and an operation interface of the operating system. A memory applicant adds a flag bit when initiating a demand application, an operating system executes allocation operation according to the flag bit, when the flag bit indicates that the demand is determined, allocation is performed according to a specified length, and when the flag bit indicates that the demand is not determined, a fixed-length memory block is allocated firstly. And when the memory operation is executed, detecting the idle state of the subsequent memory block according to the memory head flag bit, and expanding the original memory block or redistributing and copying data. According to the method, the memory waste can be remarkably reduced, the memory use efficiency under resource-limited scenes such as an embedded scene and the like is improved, the system flexibility is enhanced through configuration file adjustment and a flag bit strategy while stable operation of a program is guaranteed, and memory management and maintenance are facilitated in combination with detailed memory information records.

The invention provides a memory, an operation method of the memory and a memory system, and relates to the technical field of semiconductor chips. The memory comprises a memory array and a peripheral circuit coupled to the memory array, the memory array comprises memory blocks, and the memory blocks are coupled to the peripheral circuit through word lines. Wherein the storage block comprises a programmed storage unit and an unprogrammed storage unit, and the programmed storage unit comprises a first storage unit and a second storage unit. The peripheral circuit is configured to: perform a program operation on a third memory cell in the memory block, and apply a first voltage to a first word line coupled to the first memory cell at a first stage of a channel preparation stage of the program operation; and applying a second voltage to a second word line coupled to the second memory cell. Wherein the first word line is located between a third word line coupled with the third storage unit and the second word line, and the first voltage is larger than the second voltage.

The embodiment of the invention provides a data processing method and device, equipment, a storage medium and a program product. Comprising the steps of judging whether a transmission mode of an application layer for a to-be-written data write request is a direct read-write mode or not; if the mode is not the direct read-write mode, continuing to judge whether a client cache mechanism is started or not; if the client cache mechanism is started, continuing to judge whether the to-be-written data or metadata of a parent directory of the to-be-written data carry a cache acceleration mark or not; if the to-be-written data or the metadata of the parent directory of the to-be-written data carry a cache acceleration mark, obtaining the size of an idle memory block of a preset cache; when the size of the free memory block is greater than or equal to that of the to-be-written data and the to-be-written data is not overlapped with the data in the preset cache, storing the to-be-written data in a memory block pre-allocated by the preset cache; and traversing the memory block list of the preset cache, and storing the to-be-written data to the target storage. The method is used for achieving the effect of improving the data processing performance.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

The invention provides a memory block management method and a controller. The method comprises the following steps: acquiring a configuration file in a Linux kernel, analyzing the configuration file to obtain a memory size interval, determining a use state of a memory block in the memory size interval, and setting a bit flag of the use state in a flag bit corresponding to each memory block; whether the memory size of a target memory block of the current allocation request is in a memory size interval or not is judged, if yes, whether a first idle linked list in the SLUB allocator is empty or not is judged, and the first idle linked list is used for storing the flag bit of the memory block with the bit marked as idle; and if not, sequentially selecting a flag bit of a target memory block of a linked list from a first idle linked list of the SLUB allocator, and determining the target memory block for the current allocation request according to the flag bit of the target memory block. According to the method and the device, the problems of too high memory block metadata occupation and low allocation efficiency in the SLUB allocator can be solved.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

The invention discloses a branch prediction unit power consumption management method and device, and the method comprises the steps: setting a multi-stage branch predictor and a low-power-consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, and enabling the multi-stage branch predictor to comprise three stages of predictors which are sequentially accessed in an assembly line, the hardware resource consumption and the prediction accuracy of each predictor are gradually increased from front to back; monitoring the prediction condition of each predictor in real time through low-power-consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement within a first preset time according to a front-to-back sequence; branch jump addresses are divided into high-order address fields and low-order address fields by BTBs in the multiple levels of predictors except the first-level predictor to be stored in different storage blocks, and label registers used for taking the high-order addresses as label indexes are arranged. The power consumption unit of each predictor can be finely controlled, the energy consumption is greatly reduced, system-level cooperation is not needed, and the universality is high.

The invention relates to a non-volatile memory erase scheme. Methods, systems, and devices provide techniques for erasing data in a memory device. The memory device includes a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of word line segments. Each of the plurality of word line segments includes one or more word lines forming a subset of word lines in the memory block. The memory device further includes a memory controller configured to perform: receiving an erase command for erasing data in the memory block; and in response to receiving the erase command, causing one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different periods such that when data erase begins at a first word line segment, data erase does not start at another word line segment.

Embodiments of the present disclosure provide a memory management method, a device, a storage medium and a program product. The embodiments of the present disclosure provide a memory management mechanism relatively independent of an operating system, especially applicable to data scenarios where memory swapping is not desirable, or scenarios where independent memory isolation domains are required. Memory pages in a first memory pool are managed by means of a first memory pool management structure, and it is allowed to apply for a memory space from the memory pages in the first memory pool, the applied memory space is segmented into memory blocks of smaller granularity to create a second memory pool, and the memory blocks in the second memory pool are managed by means of a second memory pool management structure, so that the memory space can be allocated at the granularity of the memory blocks. Centralized memory management can be achieved, frequent swap-out of the memory pages in the first memory pool is avoided, system performance fluctuations are reduced, memory fragmentation can be reduced, the memory utilization rate is increased, and the system performance is improved.

Examples disclose a memory system and operating method thereof and computer-readable storage medium. An example memory system includes a memory controller and a memory coupled to the memory controller. The memory includes multiple memory blocks, a memory block includes multiple physical pages. The memory controller is configured to: determine at least one source memory block from the multiple memory blocks; in response to the bitmap type associated with a first source memory block from the at least one source memory block being a first bitmap, write valid data stored in the first source memory block into the first target memory block from the multiple memory blocks; in response to the valid data being written into the first target memory block, erase the source memory block.

The invention relates to the technical field of state recognition, in particular to an Android device remote state monitoring and intelligent operation and maintenance system which comprises an event trigger analysis module, a state feature classification module, a state section plotting module, a state fragment packaging module and a state level response module. In the method, a state path set is constructed through time label alignment of broadcast and thread events, an access source mark and a network return parameter are combined to generate a multi-dimensional state label sequence, a thread scheduling track and a memory block are mapped to form a state section structure, and an active boundary area is positioned in combination with power consumption change. Path numbers and permission information are combined, screened and packaged into a structured state unit, response level zones are divided through the number depth and the repetition rate, and complete restoration of behavior paths and accurate recognition of state nodes under the scenes of concurrent calling, complex event chains and the like are supported. And the granularity of terminal state analysis, the traceability continuity and the hierarchical adaptation capability of operation and maintenance response are remarkably improved.

A transformer acceleration device may include a memory device including first and second memory blocks respectively storing first and second plurality of cache vectors for first and second plurality of tokens, and a memory striding circuit accessing first and second memory blocks. The memory striding circuit may include a memory block address management circuit storing first and second memory block base addresses for the first and second memory blocks, a target address generation circuit calculating a first target address of the first memory block based on the first memory block base address and a first subblock offset and calculating a second target address of the second memory block based on the second memory block base address and the first subblock offset; and a command issue circuit issuing first and second plurality of memory access commands for first and second target subblock of the first and second target address respectively.

The embodiment of the invention discloses a memory device, a programming method and a memory system. The memory device includes: a memory cell array; the memory cell array comprises a memory block; the storage block comprises a plurality of storage units and a plurality of word lines coupled with the plurality of storage units; the peripheral circuit is coupled with the plurality of word lines and is configured to record a first programming total pulse number applied to a first word line in the plurality of word lines in response to incremental step pulse programming on the storage block; when the first programming total pulse number exceeds a first preset threshold value in response, it is judged that programming of a storage unit, coupled to the first word line, in the storage block fails; wherein the first preset threshold value is determined according to the programming speed corresponding to the storage unit coupled with the first word line in the storage block.

The invention relates to the technical field of distributed storage system monitoring, and particularly discloses a metadata real-time monitoring method, device and equipment of a distributed storage system. The method comprises the following steps of: dynamically loading a file system mirror image to construct an initial memory metadata model by deploying an auditing service which is physically isolated from a main node and a standby node; subscribing metadata change event streams published by log nodes in real time, and incrementally updating the model after time sequence sorting and conflict detection; key dimension fields are extracted and converted into a structured format, and after batch compression, the key dimension fields are synchronized to an index engine to construct a dual-path index; and generating cross-level directory topology analysis, a user behavior portrait and storage block distribution early warning in response to query. According to the method, the problems of high time delay, metadata splitting and main node performance interference caused by offline analysis in a traditional scheme are solved, second-level updated full-quantity metadata acquisition and multi-dimensional real-time analysis are realized, and the monitoring efficiency and storage optimization capability of a massive file system are remarkably improved.

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory block including a plurality of memory cells, a voltage generation circuit configured to generate a read voltage and a pass voltage to be applied to word lines of the memory block during a read operation on the memory block, a temperature measurement circuit configured to measure a temperature before or after the read operation is performed, and output a temperature code corresponding to the measured temperature, and a block read counter configured to determine a read count increment of the memory block depending on the read operation based on the temperature code, and to update a read count value for the memory block by adjusting the read count value depending on the read count increment.

A storage device according to the present disclosure includes a non-volatile memory device including a plurality of memory blocks, and a storage controller configured to determine a plurality of error bit counts, each of the plurality of error bit counts indicating a number of error bits of a respective one of the plurality of memory blocks, generate, based on the plurality of error bit counts, reclaim group information indicating respective assigned reclaim groups for each of the plurality of memory blocks, and control the non-volatile memory device to perform a respective read reclaim operation for each of the plurality of reclaim groups based on the reclaim group information, wherein for each of the plurality of reclaim groups, the respective read reclaim operation is performed according to a different reclaim period.

To provide a semiconductor storage device which enables high-speed operation.SOLUTION: A semiconductor storage device includes a substrate, a plurality of memory blocks, and a control circuit. The control circuit is configured to be able to consecutively execute a second program operation, after subsequently executing a first precharge operation and a first program operation in a first-mode write operation. In the first precharge operation, a predetermined voltage is supplied to a first word line. In the first program operation, a first voltage is supplied to a first selection gate line, a first program voltage is supplied to the first word line, and a write path voltage smaller than the first program voltage is supplied to a second word line. In the second program operation, the first voltage is supplied to a second selection gate line, a second program voltage larger than the write path voltage is supplied to the first word line, and the write path voltage is supplied to the second word line.SELECTED DRAWING: Figure 12

A semiconductor package includes first and second semiconductor dies on a buffer die. The first semiconductor die includes first memory blocks on a first semiconductor substrate, a first interlayer dielectric layer, a first through via penetrating the first semiconductor substrate and connected to the buffer die, and first conductive pads on the first interlayer dielectric layer and connected to the first memory blocks. The second semiconductor die includes first calculation blocks on a second semiconductor substrate and configured to calculate data received from the first memory blocks and store results to the first memory blocks, a second interlayer dielectric layer, and second conductive pads below the second interlayer dielectric layer and connected to the first calculation blocks. A top surface of the first interlayer dielectric layer contacts the second interlayer dielectric layer. The first conductive pads contact the second conductive pads.

Examples are disclosed that relate to number-theoretic-transform (NTT) architectures and inverse NTT (INTT) architectures for module lattice-based cryptographic algorithms. One example provides a device for performing an NTT for lattice-based cryptographic algorithms. The device comprises a memory block, a read address permutation generator configured to read input values from the memory block, a commutator stage comprising a first commutator layer of commutators and a second commutator layer, a butterfly stage connected to output of the commutator stage, and a write address permutation generator configured to write output values to the memory block.

The invention relates to an elf file generation method and device based on a virtual machine memory snapshot. Comprising the following steps: respectively partitioning a memory of the virtual machine according to a plurality of set memory block sizes to obtain a plurality of continuous memory blocks corresponding to each memory block size; effective data memory blocks in the memory blocks are marked, and the continuous effective data memory blocks are combined into a memory segment; calculating a loading index corresponding to the size of each memory block according to the total size of the memory segments corresponding to the size of each memory block and the number of the memory segments; determining a target memory block size from the plurality of memory block sizes according to the loading index; and generating a section of each memory segment corresponding to the size of the target memory block, reading the content of each memory segment from the memory of the virtual machine, filling the content into the corresponding section, and writing the section into the elf file. According to the method, the problems that the newly generated elf file is too large and the loading efficiency is low are solved.

Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to a plurality of word lines, respectively, a peripheral circuit configured to perform a test program operation and a pass bit detection operation of measuring a program speed of memory cells connected to a selected word line among the plurality of word lines during a test operation, and control logic configured to control the peripheral circuit to perform the test operation, and set a potential of a pass voltage to be used in a program operation, or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed.

Storage devices, host devices and electronic devices are disclosed. In an embodiment of the disclosed technology, an electronic device providing an improved security function may include a storage device including a replay protected memory block (RPMB), and a host device configured to provide a command protocol information unit (PIU) instructing the storage device to access the RPMB. The command PIU may include a basic header segment including a total extra header segment length field having a value other than 0 and an extra header segment including a host RPMB message.