986 results about "Memory block" patented technology

A metadata access method, apparatus, and computer-readable storage medium for efficient metadata retrieval through cache management. The method receives metadata query requests including target index information from processes and performs matching operations on a global cache file containing records with index information and slot identifiers. Each cache description array corresponds to memory blocks caching metadata. Upon successful matching, the target cache description array is accessed using the target slot identifier. The data state of target metadata is determined from the cache description array, and target address information indicating the location of the target memory block in shared memory is obtained and returned to the requesting process, enabling efficient shared memory-based metadata access.

Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.

The invention relates to a data processing method and device, computer equipment, a computer readable storage medium and a computer program product. After first matrix data is obtained, tensor data to be processed are obtained, and the tensor data are distributed to a plurality of calculation units; calculating a local feature value corresponding to the target calculation unit according to the local tensor data allocated to the target calculation unit; dividing the target calculation unit into data blocks corresponding to the number of the plurality of calculation units; according to the serial number of the data block, mapping the local feature value recorded in each data block to a target storage block of a target memory until the local feature value in each calculation unit is distributed to the corresponding storage block in the target memory, and obtaining a global feature value table; according to the global feature value table, feature value calculation is carried out to determine the target feature value, conflict-free parallel calculation is achieved, the utilization rate of calculation resources is increased, and the data processing efficiency is improved.

The application provides a cache manager and a control component. The cache manager comprises an interface, an allocation module and a memory. The interface receives a cache allocation request and sends the cache allocation request to the allocation module. The interface receives first cache index information returned by the allocation module and outputs the first cache index information. In response to the cache allocation request, the allocation module allocates N idle memory blocks and generates the first cache index information. The memory blocks are located in a cache, N is a positive integer, and the first cache index information comprises indexes of the N memory blocks. The memory stores indexes of at least N memory blocks. The cache manager implemented by hardware replaces the software management cache in the prior art, thereby reducing the interaction times between software and hardware when allocating a cache in the control component, improving the information interaction speed inside the control component, and achieving the technical effect of reducing the data transmission time between the host and the flash memory chip.

The invention discloses a VLA model autonomous generalization method, system and device and a medium, and belongs to the technical field of robot control. The method comprises the steps of obtaining visual observation data and natural language task description of a current environment of a robot, generating an action sequence and controlling the robot to execute tasks; track data in the task execution process are collected, and token-level dense rewards and structured reflection information are output; storing the trajectory data, the token-level dense reward and the structured reflection information into a double-memory block; extracting task priori from the long-term memory by using an experience-driven generator, and generating trajectory data containing a sub-target chain; updating the VLA strategy model by using a reinforcement learning algorithm based on the token-level dense reward; and updating the VLA strategy model by using a supervised fine tuning algorithm based on the high-quality track data set. According to the method, the technical problem of autonomous generalization of the VLA model is solved.

The invention provides a memory block management method and a controller. The method comprises the following steps: acquiring a configuration file in a Linux kernel, analyzing the configuration file to obtain a memory size interval, determining a use state of a memory block in the memory size interval, and setting a bit flag of the use state in a flag bit corresponding to each memory block; whether the memory size of a target memory block of the current allocation request is in a memory size interval or not is judged, if yes, whether a first idle linked list in the SLUB allocator is empty or not is judged, and the first idle linked list is used for storing the flag bit of the memory block with the bit marked as idle; and if not, sequentially selecting a flag bit of a target memory block of a linked list from a first idle linked list of the SLUB allocator, and determining the target memory block for the current allocation request according to the flag bit of the target memory block. According to the method and the device, the problems of too high memory block metadata occupation and low allocation efficiency in the SLUB allocator can be solved.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

The invention discloses a branch prediction unit power consumption management method and device, and the method comprises the steps: setting a multi-stage branch predictor and a low-power-consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, and enabling the multi-stage branch predictor to comprise three stages of predictors which are sequentially accessed in an assembly line, the hardware resource consumption and the prediction accuracy of each predictor are gradually increased from front to back; monitoring the prediction condition of each predictor in real time through low-power-consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement within a first preset time according to a front-to-back sequence; branch jump addresses are divided into high-order address fields and low-order address fields by BTBs in the multiple levels of predictors except the first-level predictor to be stored in different storage blocks, and label registers used for taking the high-order addresses as label indexes are arranged. The power consumption unit of each predictor can be finely controlled, the energy consumption is greatly reduced, system-level cooperation is not needed, and the universality is high.

The invention belongs to the field of Transform model acceleration, and discloses a hybrid bonding 3D stacked accelerator and acceleration method oriented to Transform reasoning, the accelerator adopts a 3D stacked architecture, and comprises a DRAM storage bare chip and a logic bare chip, the DRAM storage bare chip comprises 16 DRAM storage blocks, the logic bare chip comprises 16 processing groups, each processing group corresponds to one DRAM storage block, and the processing groups correspond to the DRAM storage blocks. Each processing group is integrated with two attention processing units, and the DRAM storage blocks are connected with the processing groups through 32 copper-copper hybrid bonding vertical channels. According to the method, the problems of dense calculation and high memory bandwidth requirement in the reasoning process are solved, efficient model reasoning acceleration is realized, and the method is suitable for natural language processing, computer vision, video analysis and other application scenes depending on the Transform model.

Disclosed are storage devices and operation methods thereof. A method includes performing a normal read operation on a memory block of the memory device to read first user data, performing an error correction operation on the first user data, and performing a special read operation on the memory block to read second user data when an error of the first user data fails to be corrected. The memory block includes cell strings, and the cell strings share ground selection lines. In the normal read operation, the memory device applies a first voltage to at least one ground selection line of the ground selection lines and applies a second voltage higher than the first voltage to remaining ground selection lines. In the special read operation, the memory device applies the second voltage or a third voltage higher than the second voltage to the ground selection lines.

The invention relates to the field of automobile electronic control, in particular to a running state monitoring method for a vehicle motor controller, which comprises the following steps: S0, determining a key running signal needing to be continuously monitored; the communication format of the key operation signal on a vehicle-mounted CAN bus is defined; the method comprises the following steps: S1, constructing and deploying an embedded operation event recording system in a motor controller; s2, after the motor controller is powered on and runs, the embedded running event recording system constructed in the S1 is started, and recording of the running event is completed; s3, continuously monitoring and accumulating the power-off dormancy times of the motor controller through the storage aging management module; and executing an erasing operation on the special storage block. According to the method, reliable storage and on-demand return of key event data can be realized on the premise of not depending on an external debugging interface and not increasing significant hardware cost, so that effective monitoring of the working state of the motor controller is realized.

The invention relates to the technical field of wireless communication, and discloses a resource scheduling system and method for multiple services to share multiple links, and the system comprises a user-defined service distribution module, a service state management module, a service data storage management module and a link resource scheduling module. The user-defined service distribution module obtains service data and determines flow identification information of the service data; the service state management module updates a state entry according to the flow identification information; the business data storage management module stores each piece of business data into a storage block; and the link resource scheduling module obtains the link state of the current high and low track link, determines a target descriptor of the to-be-forwarded service from the descriptor buffer area according to the link state and the state entry, and reads the to-be-forwarded data according to the target descriptor for scheduling and forwarding. According to the invention, efficient resource sharing of multiple services on multiple links can be realized, the utilization efficiency of the multiple links is improved, and link resources can be independently planned for different services.

A memory may include a first memory block including a plurality of first memory cells; and a second memory block including a plurality of second memory cells each having a larger size than each of the plurality of first memory cells. Normal data may be stored in the first memory block, and critical data requiring reliability may be stored in the second memory block.

The invention relates to the technical field of network communication integrated circuits, and discloses a method for quickly exchanging Ethernet messages between a chip-level CPU (Central Processing Unit) and a SWITCH, which comprises the following steps of: constructing an Ethernet frame buffer pool in an on-chip memory, dividing the Ethernet frame buffer pool into storage blocks with fixed lengths, and distributing a unique frame index; when the sending process is executed, the central processing unit writes data and submits a frame index to the switch core, and the frame index is read and transmitted by the target port; when a receiving process is executed, a switch port prefetches a frame index and writes data, and the data are processed by a switch core and then notified to be read by a central processing unit; and the central processing unit, the switch core and the port transfer the control right of the storage block through the transfer frame index. Through the shared buffer pool and an index transmission mechanism, copying and carrying of message data between the central processing unit and the switch are avoided, bandwidth occupation and processing delay of a bus in a chip are reduced, and message interaction efficiency is improved.

The invention discloses a data processing method and device, electronic equipment and a nonvolatile storage medium. The method comprises the following steps: dividing a data matrix to be calculated into a plurality of data blocks with target sizes; data corresponding to the data blocks are allocated to a plurality of stream processors for data reading operation, the data reading operation is used for loading the data from a global memory of the edge computing device to a shared memory, and the data reading and writing efficiency of the shared memory is higher than that of the global memory; and loading the data in the memory block with the preset vector length in the shared memory into a register by taking the preset vector length as a unit, and operating the data loaded into the register by adopting a stream processor to obtain an operation result. The technical problem that the computing efficiency is not high due to the fact that the related technology is limited by the particularity of the memory access and computing rule of the correction operator and the hardware performance of the edge computing equipment cannot be fully exerted is solved.

Various aspects of the present disclosure relate to determining data migration priorities in a memory sub-system. A processing device performs a scan operation, such as a read disturb scan, to detect one or more errors in a memory block of the plurality of memory blocks. The processing device determines, based on a result of the scan operation, to perform a data migration operation to move data from one or more memory segments of the memory device to one or more other memory segments of the memory device, wherein the one or more memory segments of the memory device include at least one page of the memory block. The processing logic determines a corresponding priority level of the data migration operation. The processing logic performs the data migration operation based on the corresponding priority level.

Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system can include a memory device and a memory controller configured to, when receiving a flush command indicating data to be cached in a data cache is flushed to the memory device from a host, flush first data to be cached in the data cache to the memory device, a size of the first data being less than a size of a reference write unit, write first parity associated with the first data to a parity storage block, update a value of a parity location pointer indicating a location where the first parity is written, and set a parity write flag indicating whether parity at a location pointed to by the parity location pointer is valid.

The invention discloses a method and system for improving the calculation efficiency of an end-side convolution acceleration engine and a storage medium, and belongs to the technical field of convolution acceleration engines, and the method comprises the steps: determining the weight of the end-side convolution acceleration engine, the size of an input feature map and the size of an output feature map under different conditions; correspondingly dividing an on-chip memory, which is divided into a plurality of memory blocks with preset sizes in advance, of the end-side convolution acceleration engine into three on-chip memory parts according to the sizes of the weight, the input feature graph and the output feature graph and the priorities of the weight, the input feature graph and the output feature graph from high to low, the weights, the input feature maps and the output feature maps are independently stored; and carrying out convolution calculation in a systolic array mode by using the independently stored weights, the input feature map and the output feature map. According to the specification of the current convolution calculation, the features and the weights are dynamically split, and the on-chip memory is dynamically allocated, so that the number of repeated data carrying times is reduced, and the calculation efficiency of the end-side convolution acceleration engine is improved.

The invention discloses a user working environment persistent storage method based on a double-layer container. The method comprises the steps that mirror images of all public containers in mirror image private server are pulled to a shared storage space to form a hot loading area; dividing a corresponding working space from the shared storage space, querying a target storage block corresponding to a target public container mirror image from a hot loading area based on a public container mirror image identifier in a creation request from a client, copying the target storage block to the working space to serve as a system disk, and further establishing a double-layer container and starting the double-layer container; in response to a modification request of a client, performing corresponding modification operation on the initial state inner layer container to obtain a target state inner layer container, so as to run a user working environment based on the target state inner layer container to execute a computing power task; and storing a file corresponding to the modification operation in the remaining space except the system disk in the workspace to form a user mirror image layer. According to the invention, the persistent storage efficiency of the container state and the user working environment can be improved, and the rapid restarting of the container can be realized.

The application discloses a video instance segmentation method and system based on global feature enhancement, and belongs to the technical field of computer vision and deep learning, which comprises the following steps: inputting continuous video frames into a double-channel decoupling feature extraction module to obtain appearance and position features; inputting the two types of features into a tracker and a global feature memory updating module to dynamically update and obtain long-time sequence global context features; completing instance detection matching by the tracker, judging target state to obtain disappeared and newly appeared target queries; combining long-time sequence features to model current frame time sequence to generate enhanced features; finally, the tracker completes segmentation and tracking based on the enhanced features and the target queries, and outputs a segmentation mask sequence, an instance ID, a category ID and a tracking state. Through double-channel decoupling, double-memory block updating, multi-cost matching and multi-weight feature fusion, the application strengthens appearance feature representation and long-time sequence information utilization, and significantly improves segmentation accuracy and tracking robustness in complex scenes.

A memory device including an anti-fuse cell array in a cell array structure is provided. The memory device includes: a core peripheral circuit structure including a first bonding metal pad; and a cell array structure disposed over the core peripheral circuit structure and including a second bonding metal pad in contact with the first bonding metal pad. The cell array structure includes a plurality of memory blocks and a plurality of anti-fuse cells. The core peripheral circuit structure further includes a repair circuit connected to the anti-fuse cells, and the repair circuit is configured to control each anti-fuse cell to be programmed, and to repair the anti-fuse cells based on fuse data of the anti-fuse cells received through first and second bonding metal pads connected to the anti-fuse cells. A repair operation of replacing defective memory cells in the memory cell array region with redundant memory cells is performed.

This invention discloses a high-overload data analysis method and system based on multi-dimensional buffer protection, relating to the field of data acquisition and storage technology. The system consists of several functional modules, including: a transient impedance module, which acquires stress wave propagation parameters and material strain data collected in real time by the recorder node, constructs a dynamic digital twin model of the buffer structure, and outputs impact feature vectors and stress field distribution matrices; a signal reconstruction module, which dynamically configures the sensing signals based on the impact feature vectors, including the gain, bandwidth, and filtering parameters of the analog front end, conditions and performs analog-to-digital conversion on the sensing signals, and uses compressed sensing and dictionary learning algorithms to sparsely reconstruct abnormal data, generating a high-fidelity data stream and storage data integrity identifiers for each storage block; and a federated storage module, which inputs the stress field distribution matrix and storage data integrity identifiers into the edge-side reinforcement learning decision engine to calculate the failure risk probability of each storage block.

The invention discloses an IO merging mechanism based on a block index, relates to the technical field of big data and information retrieval, and optimizes an original multi-file stream output mechanism of open source Lucene into single-file stream output by expanding a Directory interface of the Lucene, so that IO operation merging is realized in an index writing process, and the operation efficiency is improved. The method specifically comprises three parts of a file storage structure, a writing process and a reading process. The file storage structure comprises a single file structure of a file header, a data area and a file tail; during writing, data is cached in the memory block firstly, and after the memory block is full, the data is added to a file by taking a data block as a unit; during reading, quick positioning is realized by analyzing the block index at the end of the file; according to the method, the problems of performance bottleneck, small file flooding, difficulty in atomicity guarantee and the like caused by multi-file IO in the prior art are solved, and the index construction efficiency and the system stability are remarkably improved.

The invention provides a memory management method for an AI accelerator, a medium and a computer program product. The memory management method comprises the following steps: receiving a memory allocation request of a user mode application program to an onboard memory of an AI accelerator; determining whether the request memory size corresponding to the memory allocation request exceeds a preset memory size threshold value or not; when the request memory size exceeds a preset memory size threshold value, calling a kernel mode driving program to allocate a memory space for a user mode application program in an onboard memory; and when the size of the requested memory does not exceed a preset memory size threshold value, allocating a memory space for the user-mode application program based on a pre-allocated memory block in the onboard memory.

The application relates to the technical field of memory detection, in particular to a memory usage tracking method and a storage medium. The method constructs a target memory block containing a header space and a data space through obtaining a memory allocation request, records memory management information in the header space, and hangs the target memory block to a ring-shaped bidirectional linked list; in a memory access process, the validity of the target memory block is checked and access time information is updated, and safe release is performed according to the memory management information when releasing; through periodic traversal of the ring-shaped bidirectional linked list, in combination with the time information and the reference state of the target memory block, a memory usage tracking result is generated, and continuous monitoring and abnormal occupation analysis of the memory life cycle are realized. The application realizes traceability, checkability and analysis of the memory usage state, thereby effectively improving the safety, reliability and problem positioning efficiency of memory management.

The invention discloses an operation method of a memory, the memory and a memory system, and belongs to the technical field of storage. According to the method, in the process of recovering the erasing operation of the storage block, if the erasing operation is in an erasing pulse stage, the voltage of a specific word line connected with the storage block is released in advance in response to the situation that the pause frequency of the erasing operation in the erasing pulse stage is greater than or equal to a threshold value, so that the voltage of the specific word line can enter a floating state in advance; furthermore, the voltage of the specific word line can be increased along with the increase of the ACS (and / or BL) voltage in advance, and the voltage difference between the specific word line and the ACS (and / or BL) in the current recovery erasure operation process is reduced, so that the voltage difference is prevented from exceeding the threshold voltage of the specific unit, the weak erasure of the specific unit in the current recovery erasure operation process can be avoided, and the recovery erasure efficiency of the specific unit is improved. And the frequency of weak erasure of the specific unit in the erasure operation process is reduced, so that the reliability and the performance of the memory can be improved.

The invention relates to the technical field of computers, and provides a short message sending control method, a short message sending control device, a computer readable storage medium and electronic equipment.The short message sending control method comprises the steps that a preset short message sending rate limiting strategy is acquired, the short message sending rate limiting strategy is used for defining the maximum number M of short messages allowed to be sent in a preset time window; initializing an annular storage area based on the maximum short message number M, wherein the annular storage area is composed of M memory blocks; when a short message sending request is received, obtaining a time difference between the current timestamp and the earliest timestamp recorded in the annular storage area; if the time difference is larger than or equal to the preset time window, the current short message is allowed to be sent, and the current timestamp is written into the target memory block occupied by the earliest timestamp. According to the method, the memory overhead and the processing delay can be remarkably reduced while the condition that the sending amount in any continuous time window does not exceed M strictly can be ensured.

A memory device may be provided herein. The memory device may comprise a memory block configured to include a first select line, word lines, a second select line, a channel layer, first select transistors, second select transistors, and memory cells; a voltage generator configured to produce a turn-on voltage and a turn-off voltage applied to the first and second select lines, and to produce a programming voltage and a pass voltage applied to the word lines; a source line driver configured to produce a pre-charge voltage applied to the source line; and a side buffer group configured to apply a programming enable voltage and a programming lock voltage to bit lines.and a control circuit designed to determine a reference position and to control the voltage generator, source line driver, and side buffer group to adjust the time required to preload the channel layer.

The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.