15 results about "Distributed memory" patented technology

The application provides a distributed memory pool memory batch allocation method and system. The method comprises the following steps: receiving a batch allocation request containing a number of slot positions, obtaining a CPU core identifier of a current thread; performing an atomic addition operation on a tail pointer of a corresponding logical shard in a single allocator according to the CPU core identifier, locking a continuous slot position interval, the single allocator being divided into a plurality of logical shards, each logical shard corresponding to a CPU core, each logical shard maintaining an independent tail pointer, the tail pointer being an atomic variable recording the highest bit offset of the allocated logical shard; updating the bit state of the corresponding slot position interval in the bitmap of the single allocator, completing the batch continuous slot position allocation and returning the continuous physical address corresponding to the slot position interval. The method realizes lock-free allocation to reduce the allocation delay under high concurrency, guarantees the global reuse of free slot positions, and maintains a high memory utilization rate.

A computer-implemented system and method for distributed memory-native networking using agents. Each agent comprises a unique identifier, payload, memory field containing lineage and policy references, transport metadata, and a cryptographic signature. A modular protocol stack processes these agents through routing, indexing, and consensus layers, with behavior determined by embedded memory. Routing decisions are trust-scoped based on memory-derived access logs and health feedback. Mutation proposals are validated using dynamic, memory-referenced quorum formation. The system enables stateful, policy-bound propagation, structural reorganization, and adaptive execution without centralized coordination or persistent session state. It operates over conventional transport protocols and supports interoperability with cognition-layer payloads, including semantic execution. The architecture allows dynamic trust modeling, autonomous network adaptation, and memory-driven mutation governance across heterogeneous, decentralized, and highlatency environments.

This utility model belongs to the field of storage, specifically relating to a multi-cavity distributed storage platform, including a storage platform and a storage mechanism including a plurality of distributed storage boxes installed in the inner cavity of the storage platform; the front end of each distributed storage box is used to insert a memory, and the notch at the rear corresponds to the memory interface at the end of the memory; the memory is distributed and installed in each distributed storage cavity of the storage platform, and each memory is relatively independent with its own storage space and data processing capability, forming a distributed system. When writing and retrieving stored content, it is achieved through a first displacement mechanism, a second displacement mechanism, and a disk reading mechanism. After the disk reading structure moves to the corresponding memory position according to the working requirements, the disk reading interface of the disk reading end is connected to the memory interface to perform writing or retrieval of distributed memory. During access and retrieval, each memory is relatively independent, and the content stored in different memories does not interfere with each other.

Several examples of multi-port SRAM systems and related methods for distributed memory pools are disclosed. In one example, a system includes: a memory bus switch coupled to multiple memory buses; a memory pool switch coupled to one or more memory arrays; and one or more SRAM blocks coupled to the memory bus switch and the memory pool switch to convert a first transaction received on one of the multiple memory buses into a second transaction executed on the one or more memory arrays.

This invention relates to a data modeling technology, specifically a multi-module integrated real-time database system. It includes multiple parallel magnetic core memories, each comprising a synchronization host that establishes unidirectional communication with multiple application systems via a filtering channel controller. The magnetic core memories also include a memory database that interacts with the synchronization host. The synchronization host is also connected to multiple data interfaces for real-time data acquisition and supports multiple real-time data acquisition sources. By constructing a distributed memory database using the synchronization host, memory database, and filtering channel controller, a large amount of real-time data is first received and stored in memory. The memory data is then instantiated in a process-by-process manner, forming a system architecture with excellent scalability. The overall system performance can be adjusted by adding a corresponding number of magnetic core memories according to actual application requirements.

This invention discloses a distributed cache coherence system and method based on CXL tunnel transmission coherent bus, belonging to the fields of distributed computing and high-speed interconnect bus technology. Addressing the technical shortcomings of existing distributed architectures based on the CXL protocol, such as high cross-node cache coherence latency, inability to scale without interruption, and low deployment density, this invention encapsulates the coherent bus messages inside the master computing node into the CXL link layer Flit unit for tunnel transmission through a protocol conversion unit. It maps the remote CXL memory pool to the local coherent bus home node, and simultaneously includes a dynamic, uninterrupted topology management mechanism, a high-speed signal and power supply integrated interconnection interface, and an integrated electromagnetic shielding heat dissipation structure. This invention reduces cross-node memory access latency by more than 70% compared to existing solutions, achieves cluster availability of 99.999%, and increases deployment density by more than 40%. It can be widely applied in scenarios such as artificial intelligence computing clusters, heterogeneous computing resource pooling, and distributed memory databases.

The application discloses a distributed memory access device and method suitable for three-dimensional stacked storage, and relates to the technical field of distributed memory scheduling. The distributed memory access device suitable for three-dimensional stacked storage comprises a plurality of master devices integrated on a logic chip, a plurality of memory banks and a memory access scheduling hardware circuit. The plurality of memory banks are organized by low bit interleaving from memory units stacked in three dimensions above the logic chip. The memory access scheduling hardware circuit comprises a plurality of sub-routing networks. The plurality of sub-routing networks are dispersedly arranged on the logic chip, and each sub-routing network connects the plurality of master devices to a memory bank. The plurality of sub-routing networks jointly form a complete, physically distributed memory access path between the plurality of master devices and the plurality of memory banks.

This application discloses a method, apparatus, system, electronic device, and medium for processing API requests. The method includes: loading multiple custom processors pre-built in a database into a distributed memory grid, wherein each custom processor has a first mapping relationship with an API request, and a second mapping relationship between the API request and its corresponding processing method is established in the custom processor based on a reflection mechanism; receiving an API request and routing it to a corresponding target custom processor according to the first mapping relationship, so that the target custom processor determines the target processing method corresponding to the API request according to the second mapping relationship; and invoking the target processing method to process the API request. This application improves the API registration method, and the distributed service cluster is simple to deploy, easy to expand, and avoids the problem of distributed consistency from the root.

A host-originated memory read request is received by a non-host device from a host device to retrieve data stored at a device memory attached to the non-host device, the memory host-originated read request from the host device including a specific host-assigned memory read request type attribute. Responsive to receiving the host-originated memory read request, the non-host device generates a device-memory-bound memory read request corresponding to the host-originated memory read request, a priority mapping being applied to map the specific host-assigned memory read request type attribute to a specific device-memory priority selected from among a plurality of device-memory priorities. The device-memory-bound memory read request is sent along with the specific device-memory priority to a memory controller of the device memory to access the data stored at the device memory.

The application discloses a kind of multistage memory adaptive management system and method for emotional companion robot, belong to the technical field of robot intelligent interaction and artificial intelligence memory management;Around the concept repeatedly proposed by user in long-term interaction, preference, relationship fact, behavior habit and rule constraint establish memory entry, through effective mechanism filter short time repeat brush score behavior, through three kinds of running state of increase, buffer, reduce score realizes the adaptive migration of memory weight, and adopts eighteen points system score to distribute memory entry to four-level library, three-level library, two-level library and first-level library.According to memory level, execute ladder type attenuation, backflow, delete and protection strategy, so that temporary memory can be naturally eliminated, and stable preference and core rules can be retained for a long time.This scheme does not need to rely on vector database or high-power model, and can be deployed in emotional companion robot, intelligent doll, mobile application, intelligent assistant, social software and cloud service.

The application discloses a distributed memory pooling method and device for a real-time stream computing scene. Three API of Put, Get and Delete are provided for an upper application, and four primitive API of Malloc, Free, Write and Read are used in lower layer implementation. A cache layer is constructed through specified protocol operation in the lower layer, and a FIFO and LRU mixed strategy is used for corresponding cache eviction. A master node is maintained by a cluster node for global memory allocation, and the Malloc operation of each stream computing task is forwarded to the master node for load balancing of memory allocation. The application can effectively reduce network overhead caused by traditional TCP / IP, and can reduce overhead caused by remote node memory access in distributed memory computing by constructing a cache layer thereon, so that the response speed of the system is significantly improved.

A memory device may include various circuitry including multiple memory banks and a circuit under array. The circuit under array may include a number of control blocks each coupling to a respective memory bank. The control blocks may route data and commands to the memory cells of the memory arrays of the respective memory banks. In particular, the control blocks may include routing circuitry including column routing circuits, row routing circuits, and coupling routing circuits to route data between external devices and the memory banks. For example, the coupling routing circuits may couple the column routing circuits and the row routing circuits. Implementing the coupling routing circuits with the control blocks may reduce a footprint of the circuit under array.

Techniques relating to computing systems that utilize silicon photonics are disclosed. In some embodiments, a computing system includes a plurality of computing die packages containing processors configured to execute program instructions operating on data stored in distributed memory accessible via a unified memory architecture. The computing system further includes a plurality of memory die packages configured to implement the unified memory architecture, such that a given memory die package includes one or more optical interfaces configured to receive memory requests from the processors and one or more memory controllers configured to access a portion of the distributed memory in response to the received memory requests.

This invention relates to the field of financial technology and discloses a continuous service trading device, method, and equipment based on distributed memory. The device includes: an account operation system, a trading system and a clearing system built based on distributed memory technology. The account operation system, trading system, and clearing system are physically independently deployed and their business functions are decoupled. The device also includes a main center, a backup center, a disaster recovery center, and an intelligent traffic scheduler. Nodes of the account operation system, trading system, and clearing system are deployed in the main center, backup center, and disaster recovery center. The intelligent traffic scheduler is configured among the main center, backup center, and disaster recovery center, and dynamically schedules business traffic between the main center and the backup center or disaster recovery center when the system performs maintenance, upgrades, testing, or failover. Through the above methods, the system of this invention has strong scalability and achieves continuous service of the trading system while ensuring high-performance processing capabilities.