267 results about "Clock control" patented technology

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

The invention relates to the technical field of earthquake and acoustic exploration, and discloses a signal acquisition and transmission method, device, equipment and medium based on a main control unit, and the method comprises the steps: generating a sampling clock signal and a time counting signal, driving an analog-to-digital conversion unit to obtain a digital acquisition signal, and reading equipment state parameters; after the timestamp is added, the digital signal is stored in the first cache unit, the state data after the timestamp is added is stored in the second cache unit, the data signal cache unit is written into a first FLASH partition after being full, and the state data cache unit is written into a second FLASH partition after being full. And after data is read from the FLASH, differential signals are output through the multi-wire parallel interface, the logic processing unit and the serialization unit. According to the invention, power consumption is reduced through unified power management and optimization of clock control and a dormancy mechanism, and transmission bandwidth is improved in combination with high-speed differential output, so that both low power consumption and high efficiency are realized.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

A method may include generating a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate. The method may include disconnecting the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate, and generating a second clock path, wherein the mesh is connected to a second CCL. The method may include generating a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree. Finally, the method may include generating a second clock tree in the second clock path between the second CCL and a second sequential gate.

A control system includes: a time master configured to periodically transmit synchronization signals for time synchronization via a network; and circuitry connected to the time master via the network, wherein the circuitry includes a local clock and is configured to: periodically determine, for every two or more receptions of the synchronization signal via the network, a communication timing so that a frequency of the communication timing is reduced from a transmission frequency of the synchronization signal; periodically perform, in accordance with the communication timing periodically determined with the reduced frequency, data exchange with the time master including transmission of a response signal to the synchronization signal; acquire an offset of the local clock with respect to the time master based on a result of the data exchange; correct the local clock in accordance with the offset; and control a machine based on the corrected local clock.

The invention discloses an acoustic signal partial discharge detection system of a distribution network transformer, which is characterized by comprising a multi-sensor acquisition unit, a synchronous clock control unit, a signal preprocessing unit, an edge calculation processing unit and a communication and storage unit, the edge calculation processing unit integrates a cross-band denoising module, a multi-scale feature extraction module, a lightweight neural network diagnosis module and a diagnosis result fusion module, wherein the cross-band denoising module is used for performing joint denoising on audible sound and ultrasonic frequency band signals. According to the invention, a set of partial discharge detection scheme for a distribution network transformer scene is established, and the scheme flow comprises denoising, feature extraction, neural network training and diagnosis. According to the scheme, audible audio frequency band and ultrasonic frequency band data are covered, and interference generated by mechanical vibration of the transformer in the ultrasonic frequency band is removed through a soft threshold value of wavelet transformation and a pulse detection denoising algorithm.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

The invention relates to the technical field of testability design, and discloses an on-chip clock controller and test equipment, the on-chip clock controller comprises a main clock control circuit, the functional clock input end of the main clock control circuit is connected with a phase-locked loop output clock, and the clock output end of the main clock control circuit is connected to a main frequency domain receiving node so as to output a main frequency clock signal to the main frequency domain receiving node; the functional clock input end of the slave clock control circuit is connected with the clock output end of the master clock control circuit, and the clock output end of the slave clock control circuit is connected to a frequency division domain receiving node so as to output a frequency division clock signal to the frequency division domain receiving node; wherein the master clock control circuit and the slave clock control circuit are controlled by external slave enable signals, and a data interaction channel is arranged between the master frequency domain receiving node and the frequency division domain receiving node. By cascading the master clock control circuit and the slave clock control circuit and constructing the data interaction channel, dynamic collaborative testing of the master frequency domain and the frequency division domain is realized, and the problem of delay fault detection of the multi-frequency-domain integrated circuit is solved.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

A control circuit includes: an input sampling circuit, configured to perform sampling processing on an initial command address signal based on a first clock signal to generate an intermediate command address signal; a gating generation circuit, configured to generate a first gating enable signal based on the intermediate command address signal and perform pulse width adjustment on the first gating enable signal based on a reset signal to generate a first gating signal; and a clock control circuit, configured to perform control processing on a second clock signal based on the first gating signal to generate a command clock signal. There is an association relationship between the level state of the first gating enable signal and the intermediate command address signal.

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

A digital phase-locked loop (PLL) circuit is provided, comprising: a synchronization control module configured to generate an input characterization signal representing the periodic change of the input periodic signal relative to the base clock signal based on a base clock signal and an input periodic signal; a counting control module configured to generate a clock counting result representing the multiple relationship between the period of the input characterization signal and the period of the base clock signal based on the base clock signal and the input characterization signal; an arithmetic control module configured to generate a base clock control variable based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and to generate an output clock control variable based on the clock counting result; and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate an output clock signal based on the output control signal and the base clock signal.

The invention relates to the technical field of sequential control, and discloses a sequential logic control circuit for a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter), which comprises an analog signal acquisition circuit for receiving and preprocessing an initial input signal; the noise shaping circuit is used for performing frequency spectrum shaping on quantization noise in the analog signal and generating the analog signal subjected to noise shaping; the successive approximation type analog-to-digital converter is used for performing bit-by-bit comparison with the analog signal subjected to noise shaping and gradually completing conversion from the analog signal to the digital signal from the highest bit to the lowest bit; and the clock control circuit is used for coordinating sequential logic among the analog signal acquisition circuit, the noise shaping circuit and the successive approximation type analog-to-digital converter. According to the method, frequency spectrum remodeling is carried out on the quantization noise in the signal, the signal-to-noise ratio of the signal is remarkably improved on the premise that the hardware complexity is not additionally increased, and then interference of the noise on follow-up analog-to-digital conversion is reduced.

The application discloses a signal receiving device of an electric wave clock and relates to the technical field of electric wave clocks.The electric wave clock comprises an electric wave clock body, a clock control module arranged on the back of the electric wave clock body and a signal receiving module arranged on the outer side of the clock control module; the clock control module and the signal receiving module are connected through wires; the back of the electric wave clock body is provided with a winding mechanism; and the winding mechanism is arranged on the circumferential side of the clock control module.The signal receiving module is separated from the electric wave clock body, the clock control module and the signal receiving module are connected through wires, the signal receiving module is installed outdoors, the winding mechanism is used to wind or release the wires, the signal receiving strength of the signal receiving module is effectively improved, the data transmission stability between the clock control module and the signal receiving module is improved, and the time accuracy of the electric wave clock body is ensured.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The invention discloses a programmable logic chip supporting single-ended clock input and electronic equipment. The chip comprises a function module and a clock module, and the clock module comprises a first clock source used for generating a first single-ended clock signal; the clock selection unit is used for selecting the first single-ended clock signal or the second single-ended clock signal to be output according to a set selection signal; the clock generation unit is used for performing frequency conversion and phase adjustment on the clock signal output by the clock selection unit according to a set configuration signal to generate one or more single-ended output clocks; the clock distribution unit is used for outputting one or more single-ended output clocks generated by the clock generation unit to corresponding functional modules according to a set control signal; and the clock control unit is used for generating a selection signal, a configuration signal and a control signal according to preset configuration information or externally input configuration information. According to the integrated clock module, the problem that an existing programmable logic chip depends on an external clock chip is solved.

This invention discloses an optimized method for TCMS and ATC time synchronization control. When ATC communication is normal, the time parameter information sent by ATC is valid, the ATP bypass switch is not in the bypass position, the time difference between the TCMS internal clock and the standard time sent by the ATC during normal communication exceeds 2 seconds, and the ATC heartbeat read in the current cycle differs from the called ATC heartbeat cache variable, and the ATC heartbeat read in the previous cycle also differs from the called ATC heartbeat cache variable, the TCMS internal clock is synchronized with the ATC time when all the above conditions are met. This method solves the problem of TCMS misinterpreting a change in ATC heartbeat when the gateway device is powered on again while the ATC heartbeat is stopped, causing the TCMS time to synchronize with the ATC time at the moment before the gateway power failure. This method has strong versatility and improves the reliability and stability of TCMS system clock control.

The embodiment of the invention provides a power consumption control circuit, a chip and electronic equipment, the circuit comprises a first storage circuit, a state identification circuit and a clock control circuit, the state identification circuit is connected to a transmission channel, and the first storage circuit is connected to the state identification circuit and the clock control circuit; the state identification circuit is used for identifying the state of the transmission channel in each clock cycle and storing the state in the first storage circuit, and the first storage circuit is used for storing the states of multiple clock cycles; the clock control circuit is used for controlling the clock frequency of the transmission channel according to the states in the first storage circuit. The power consumption control circuit is arranged for different transmission channels, and the clock frequency of each transmission channel is adjusted in a self-adaptive mode according to the states of the transmission channels in multiple time periods. Therefore, the power consumption generated by the clock of each transmission channel can be reduced as much as possible, and the power consumption of the whole semiconductor chip can be effectively reduced.

A fractional-N phase-locked loop (PLL) and its charge pump control method are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a frequency divider clock controller. The first current source provides a first current. The first PFD generates a first detection signal based on a first frequency divider clock to control the first current source, wherein the first frequency divider clock is generated based on an oscillation clock with an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal based on a second frequency divider clock to control the second current source. The frequency divider controller controls the second frequency divider clock based on a variable delay relative to the first frequency divider clock, wherein the variable delay is an integer multiple of the oscillation period. Using this method, phase noise can be reduced.

Provided is a clock generating apparatus including a voltage control oscillator that outputs a clock corresponding to a control voltage which is input, a control voltage generator that generates the control voltage corresponding to a difference between a frequency of the clock and a target frequency, a starting voltage generator that generates a starting voltage which is supplied to the voltage control oscillator during a start period of the voltage control oscillator, and a starting circuit that sets the control voltage to the starting voltage during the start period after a start-up of the voltage control oscillator.

The application discloses an operational amplifier circuit, an analog-to-digital converter and an Internet of Things chip, wherein the operational amplifier circuit comprises an amplifier module and a level shift module; the level shift module comprises a level shift capacitor and a clock controller; the level shift capacitor is connected in series between the differential output end of the amplifier module in the first amplification time of the first amplification of the amplifier module to sample the output voltage of the amplifier module, and is connected in series between the output end of the amplifier module and a load capacitor in the second amplification time of the second amplification to perform secondary amplification after level shifting; and the first amplification of the amplifier module is disconnected before the amplifier module is completely amplified and established, so that the first amplification time is less than the time required for the amplifier module to be completely amplified and established. The circuit of the application can ensure high gain, improve speed and reduce power consumption.

A method and system for deterministic communications between a plurality of interconnected semiconductor chips. The system includes a plurality of semiconductor chips, and a controller coupled to each of the plurality of semiconductor chips, respectively. The controller is configured to transfer data from one semiconductor chip to another. Each of the semiconductor chips and the controller include a respective clock, and the controller is configured to synchronize the clocks of the plurality of semiconductor chips. The controller schedules and manages data flows from and to the plurality of semiconductor chips for deterministic communications between the plurality of semiconductor chips. The controller may implement IEEE Time Sensitive Networking (TSN) protocol for scheduling and managing the data flows between the plurality of semiconductor chips.

The application provides a phase-locked loop chip and a phase-locked loop system, and relates to the technical field of integrated circuits.The gain automatic switching reference sampling phase detector for a phase-locked loop proposed in the application can effectively improve the phase detection gain in the locked state while keeping the wide capture range [‑π / 2, π / 2] characteristic of the traditional reference sampling phase detector; the gain automatic switching reference sampling phase detector proposed in the application uses a gain controller to compare the branch voltages output by the first branch unit and the second branch unit with the relationship of the preset threshold voltage to determine whether it works in the normal mode or the gain multiplication mode; if both branch voltages are less than the preset threshold voltage, an enable signal of the gain multiplication mode is generated, the clock generator generates the corresponding clock control signal, and the clock control signal acts on the first branch unit and the second branch unit, so that the effect of M times gain increase is achieved, and the compromise relationship between the phase detection gain and the capture range of the existing phase detector is broken.

The invention discloses a hybrid power system continuous dynamic-discrete strategy double-layer parallel simulation architecture which comprises a plurality of modules distributed in a master process and a slave process, the master process is used for simulating and solving a continuous subsystem model and controlling an overall simulation time sequence, and the slave process is used for simulating and solving a discrete subsystem model. The master process comprises a clock control module, a discrete event processing module, a continuous model grouping parallel module and a continuous state sending module, the slave process comprises a continuous state receiving module, a discrete model grouping parallel module and a discrete event sending module, and a shared memory module is set as an interaction channel of the master process and the slave process. According to the method, the simulation efficiency of the hybrid power system is effectively improved on the premise of ensuring the accuracy of a simulation time sequence through consecutive discrete subsystem parallelism and model grouping parallelism in the subsystems. The framework can be applied to hybrid power system simulation fields such as cascading failure analysis, power system stability control system checking and the like.

A circuit (100) for a phase-locked loop is described herein. The circuit (100) includes a phase frequency detector (102) configured to determine a phase error; a loop filter (106) coupled to the phase frequency detector (102) and configured to provide a clocked signal based on the phase error; and a controller (116) coupled to the phase frequency detector (102) and the loop filter (106). The controller (116) is configured to receive the phase error, detect a behavior of the phase error, and in response to the behavior of the phase error, perform a response including causing the phase frequency detector (102) to adjust the phase error and causing the loop filter (106) to adjust the clocked signal. Thus, the circuit (100) may reduce setup time, overshoot, and / or undershoot in an output clock generated based on the clock control signal.

The application provides a source driver, a display device and a flexible circuit board, relates to the technical field of display, and aims to enhance the electrostatic protection capability and prevent problems such as electrostatic discharge flash screen. The source driver comprises a digital circuit, an analog circuit and a protection circuit. The digital circuit is configured to receive a first voltage signal and output an enable control signal. The analog circuit is electrically connected with the digital circuit, and the analog circuit is configured to receive the enable control signal and a second voltage signal and output a clock control signal. The protection circuit is electrically connected with the digital circuit and the analog circuit, and the protection circuit is configured to control the voltage difference to be less than a threshold voltage when a voltage difference between the first voltage signal and the second voltage signal is generated. Based on this, when an electrostatic attack signal occurs, the voltage difference between the digital ground signal and the analog ground signal does not affect the digital logic operation, the accuracy of the source driver signal logic is ensured, and the anti-static ability of the source driver is improved.

The application relates to a dual-mode FLASH-SAR ADC conversion circuit and method, the circuit comprising a FLASH ADC module, a SAR ADC module, a clock control module and an encoding module. In reference mode one, the FLASH ADC module is a single-end structure, the FLASH ADC module samples the voltage division of a first reference voltage in a conversion stage, the positive and negative ends of the FLASH ADC module are connected with the voltage division of the first reference voltage and an input signal respectively in a sampling stage, and all the sampling capacitors in the SAR ADC module sample the input signal. In reference mode two, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of a second reference voltage in a conversion stage, the positive and negative ends of the FLASH ADC module are connected with the second reference voltage and the input signal respectively in a sampling stage, and half of the sampling capacitors in the SAR ADC module sample the input signal. The ADC circuit resources are greatly saved, and the application cost is saved.

This application discloses an LVDS adaptive frame synchronization system, comprising: a transmitting end: a clock generation module providing multi-rate clocks; a data parallel-to-serial conversion module converting parallel data into a high-speed serial bit stream under clock control; a multi-functional auxiliary channel parallel-to-serial conversion module interleaving and encoding auxiliary control information and synchronization information into a composite bit stream; and an LVDS driver group converting signals into differential signals for transmission. The receiving end: an LVDS receiver group converts differential signals into single-ended signals, including multiple data signals, one auxiliary channel signal, and one half-rate clock signal. A serial-to-parallel conversion and synchronization control module uses a half-rate clock to perform DDR sampling of the data and auxiliary channel signals. Synchronization information is extracted by sampling on the falling edge of the auxiliary channel signal, and auxiliary control information is extracted by sampling on the rising edge. A synchronization detection unit obtains the capture sequence from the synchronization information, and a numerically controlled delay unit calculates the delay correction amount based on the mapping relationship between the capture sequence and the correction signal to delay the data, thereby achieving adaptive frame synchronization.

An apparatus includes a logic circuit having a clock input, a first logic circuit control output, and a second logic circuit control output. A clock generation circuit has a first clock control input, a second clock control input, and a clock output. The clock output is coupled to the clock input. An off-timer circuit has an off-timer output. A comparator has a comparator output. An out-of-audio (OOA) circuit has a first OOA input, a second OOA input, a third OOA input, a first OOA output, and a second OOA output. The first OOA input is coupled to the comparator output. The second OOA input is coupled to the clock output. The third OOA input is coupled to the off-timer output. The first OOA output is coupled to the first clock control input. The second OOA output is coupled to the second clock control input.