612 results about "Clock control" patented technology

The invention provides a PCIe clock gating circuit and a PCIe clock control method. The PCIe clock gating circuit comprises a link width control circuit, a link rate control circuit and a link state control circuit, the link width control circuit is used for outputting a control signal for closing a clock of a module not related to the current width when the current link width is smaller than the maximum width; the link rate control circuit is used for outputting a control signal for closing a clock of a non-current rate related module, and the link state control circuit is used for outputting a control signal for closing a clock of an abnormal working state related module when the current link state is an abnormal working state. The abnormal working state related modules comprise related modules corresponding to other link states except the current link state; and the link state control circuit is also used for outputting a control signal for closing clocks of the training code stream sending module, the training code stream receiving module and the link training related module in a normal working state.

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

The invention discloses a current and voltage signal synchronous correction and output method and system, and relates to the technical field of power system analysis and control. Compared with a previous current and voltage signal correction method, the method solves the problems that traditional multi-channel signal acquisition depends on conventional clock control, and synchronization precision is insufficient; a conventional sampling circuit is weak in anti-interference capability. The problem that an existing scheme lacks efficient error prediction and dynamic optimization capability is solved. Through a multi-channel FPGA clock synchronization and double-differential sampling technology, complete acquisition of high-frequency transient characteristics of voltage and current signals is ensured; a dynamic calibration algorithm and multi-stage composite filtering are combined, so that common-mode interference and non-linear errors are effectively suppressed; and finally, through optical fiber isolation output and intelligent feedback control, signal full-link synchronous correction is realized, the electric energy metering error can be reduced, the fault positioning precision is improved, the characteristics of high precision, strong anti-interference and low energy consumption are realized, and a reliable data reference is provided for intelligent power grid and new energy grid connection.

The invention provides a novel clock control method and system based on FPGA, and relates to the technical field of signal processing. The system provided by the invention comprises: a VCXO voltage-controlled crystal oscillator, a digital-to-analog converter, a PLL phase-locked loop module, a DDMTD measurement module and an adaptive clock control module. The phase-locked loop is implemented, a phase detection algorithm and a clock control algorithm are executed based on a single FPGA chip, and the hardware design complexity is low. The invention uses a digital dual-mixing time difference method (DDMTD) to measure and obtain a clock phase detection result, and cooperates with a dynamic PID clock control algorithm to quickly adjust the local clock frequency, so as to realize the fast tracking and locking of the frequency and phase between the local clock and the clock source. The dynamic PID clock control algorithm of the invention dynamically adjusts the parameter P of the PID algorithm in real time according to the state, the clock frequency deviation and the clock phase difference, so that the algorithm has the advantages of stronger locking ability, shorter convergence time and faster response.

The invention discloses a multi-channel parallel sampling high-dynamic response analog-to-digital conversion method, system and equipment and a storage medium, and belongs to the technical field of power electronics and signal processing, and the method comprises the steps: configuring a high-speed analog-to-digital converter channel to form a parallel sampling module, carrying out the alternate sampling of an input power grid analog signal, and generating a discrete sampling sequence group; inputting to a control unit to extract feature data, and calculating to obtain a fluctuation feature value; constructing a channel clock control vector, sending the channel clock control vector to each high-speed analog-to-digital converter channel, adjusting a sampling trigger moment, and re-executing analog signal sampling to obtain a sampling sequence after phase compensation processing; performing waveform reconstruction processing to obtain continuous reconstruction waveform data; and performing electric energy integral operation, and outputting a dynamic metering result. According to the invention, the problems of slow response, sampling distortion and large metering error of the analog-to-digital conversion system under the conditions of frequency fluctuation, unsteady disturbance and bidirectional power in the prior art are solved.

Embodiments relate to a level shifter including a first circuit unit configured to output a start signal, a reset signal, and a node charge signal to a gate driver in response to a start control signal and a node charge control signal that are input from a timing controller, a second circuit unit configured to output an output erase signal and a clock shift stop signal in response to the start signal and the reset signal, and a third circuit unit configured to generate a clock signal based on a clock control signal input from the timing controller and output the generated clock signal to the gate driver in response to the output erase signal and the clock shift stop signal that are output from the second circuit unit, a display device including the same, and a method of driving the display device.

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

The embodiment of the invention discloses a clock equipment failure early warning method and device based on clock control quantity. The method comprises the following steps: acquiring the frequency control quantity of each synchronous clock device in the frequency synchronization network, and calculating the frequency control accumulation quantity based on each frequency control quantity; calculating a frequency drift amount corresponding to the frequency control accumulation amount based on a Kalman filtering algorithm, and calculating a frequency sky drift amount and a frequency cycle drift amount based on the frequency drift amount; inputting the frequency control accumulation amount, the frequency sky drift amount and the frequency cycle drift amount into the trained support vector machine model as input quantities to obtain an alarm output result; and carrying out clock equipment failure early warning on a preset management terminal based on the alarm output result. According to the embodiment of the invention, a manager can clearly and intuitively know the potential failure risk condition of the system at the moment, the condition is processed in time, and the actual occurrence of the risk is avoided.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

Hub node of a passive optical network, wherein the hub node includes a DSP (Digital Signal Processing) chain configured to: Receiving a signal burst from a leaf node in the passive optical network, wherein the signal burst comprises a frame including a payload and a frame header, the frame header comprising a clock and gain control section, a frame detection section and an equalizer section; Retrieving a clock phase of the leaf node from the clock-and-gain control section of the frame header; Estimation of the signal strength of a signal burst from the leaf node in the passive optical network; Compensation for differences in the signal power of the signal burst from the leaf node; Detecting a frame alignment sequence that indicates the arrival of the signal burst; Determination of MIMO (Multiple Input, Multiple Output) polarization filter coefficients from the frame alignment sequence; Aligning the phase between the X-polarization and Y-polarization of the signal burst using the MIMO polarization filter coefficients; and Determine the frequency offset estimate (FOE) of a local oscillator signal.

The invention discloses a clock control method for an intelligent adjusting unit, and the method achieves the excellent clock stability through the comprehensive application of a high-precision constant-temperature crystal oscillator and a dynamic temperature compensation technology. An integrated intelligent power management and electric quantity monitoring mechanism ensures seamless clock operation and system time continuity during power failure; gPS / Beidou and encryption communication technologies are integrated, so that the accuracy of clock synchronization is enhanced, and the security of data transmission is enhanced; machine learning is adopted to predict clock drift, so that a calibration strategy is intelligent, and the maintenance burden is reduced; strict authority management and multi-level security protection are implemented, and unauthorized access is effectively prevented; the combination of the power-off self-starting timing and the health monitoring system further ensures the long-term accurate operation of the clock and the high reliability of the system. A series of innovative measures jointly construct a clock control solution which is high in accuracy, safe and high in adaptability, and the strict requirement of a modern intelligent system for time synchronization is met.

The invention relates to the technical field of earthquake and acoustic exploration, and discloses a signal acquisition and transmission method, device, equipment and medium based on a main control unit, and the method comprises the steps: generating a sampling clock signal and a time counting signal, driving an analog-to-digital conversion unit to obtain a digital acquisition signal, and reading equipment state parameters; after the timestamp is added, the digital signal is stored in the first cache unit, the state data after the timestamp is added is stored in the second cache unit, the data signal cache unit is written into a first FLASH partition after being full, and the state data cache unit is written into a second FLASH partition after being full. And after data is read from the FLASH, differential signals are output through the multi-wire parallel interface, the logic processing unit and the serialization unit. According to the invention, power consumption is reduced through unified power management and optimization of clock control and a dormancy mechanism, and transmission bandwidth is improved in combination with high-speed differential output, so that both low power consumption and high efficiency are realized.

A robot system including a robot, an image capturing device, and a controller. The controller and the image capturing device have clocks, the controller conducts transmission of, to the image capturing device, an image-capturing instruction including a predetermined waiting time, the predetermined waiting time being a time between a time of the transmission and an image capturing time, or a required time obtained by subtracting, from the waiting time, a difference time between the time of the transmission and receiving time of the image-capturing instruction, the image capturing device conducts image capturing of an image of the workpiece at time when the required time elapses from the receiving time and transmits image data, and the controller controls the robot based on position information of the robot at time when the waiting time elapses from the time of the transmission and the image data.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

The invention relates to a redundant feedback latch multilevel anti-single-particle reinforced trigger of a FinFET (FinFET) process, which comprises a data input structure, a clock input structure, four clock control structures, a delay structure, a data master latch structure, a data slave latch structure and a data output structure, the trigger latches data for both the data master latch structure and the data slave latch structure by using a redundancy feedback circuit, and delays one path of data by using a delay structure to filter external single-particle transient pulses at a data end; through a redundancy feedback latch structure and a delay unit, the circuit realizes multi-dimensional reinforcement of single-particle unit / multi-bit upset and single-particle transient, and the single-particle radiation reinforcement resistance of the trigger is significantly improved. In addition, a design reinforcing method combining a circuit and a layout is preferably adopted, the number of Fins in unit grid spacing is designed to be the maximum, an interdigital structure is used for devices at sensitive nodes, meanwhile, the sensitive nodes are arranged in an isolated mode, and the single-particle multi-bit upset resisting capacity is further enhanced.

The circuits and methods described herein provide a technical solution for technical issues for USB links. To reduce or eliminate the effects associated with the entry of a USB link into a low power mode, an initial link acquisition may be performed while disabling spread spectrum clock (SSC) modulation. After initial link acquisition, SSC modulation may be dynamically enabled at a later stage. This delayed activation of the retimer provides improved performance compared to a solution in which SSC modulation is continually activated, including reducing the complexity of the timing training process and enabling faster USB link re-establishment. This reduced link acquisition period may enable the system to enter the power saving mode more frequently and may reduce the latency involved in exiting the power saving mode. This may maintain or improve the overall USB transmission speed, and may reduce USB-related power consumption for USB-connected devices.

A circuit for a phase-locked loop is described herein. The circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. The controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. Thus, the circuit may reduce settling time, overshoot, and / or undershoot in an output clock generated based on the clock control signal.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

The embodiment of the invention provides a digital driving waveform generation device and method of a galvanometer and projection equipment, and relates to the technical field of laser projection. The device comprises a subframe delay module, a clock control module, an address control module and an amplitude storage module, the sub-frame delay module is used for delaying the sub-frame signal and transmitting the delayed sub-frame signal to the address control module; the clock control module is used for providing a control clock for generating a digital driving waveform for the address control module; the amplitude storage module is used for storing a plurality of amplitudes of the digital driving waveform according to a preset storage sequence; and the address control module is used for reading the amplitudes of a preset segment number from the amplitude storage module according to a preset galvanometer type when the rising edge or the falling edge of the delay subframe signal arrives, and outputting the amplitudes in sequence according to a reading sequence to generate a digital driving waveform. The embodiment of the invention is used for generating the digital driving waveform, so that the galvanometer moves to an accurate position required by image display.

A method may include generating a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate. The method may include disconnecting the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate, and generating a second clock path, wherein the mesh is connected to a second CCL. The method may include generating a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree. Finally, the method may include generating a second clock tree in the second clock path between the second CCL and a second sequential gate.

The invention discloses a clock control device and method, a controller and a system-on-chip, and the device comprises the steps: delaying a first preset clock to stop inputting a digital clock signal to a digital logic device based on an analog clock signal inputted by an analog clock generation device when a low-power-consumption request signal issued by the digital logic device is received; delaying the second preset clock to close the analog clock signal output by the analog clock generation device; when a wake-up input signal input by an external wake-up source is received, after a first preset clock is delayed to input a high-level digital clock gating signal to a digital clock gating unit in the clock control device, a third preset clock is delayed to control the analog clock generation device to output an analog clock signal; the digital clock gating unit inputs a digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal. The device can completely avoid burrs generated when clock signals are turned on and turned off.

A control system includes: a time master configured to periodically transmit synchronization signals for time synchronization via a network; and circuitry connected to the time master via the network, wherein the circuitry includes a local clock and is configured to: periodically determine, for every two or more receptions of the synchronization signal via the network, a communication timing so that a frequency of the communication timing is reduced from a transmission frequency of the synchronization signal; periodically perform, in accordance with the communication timing periodically determined with the reduced frequency, data exchange with the time master including transmission of a response signal to the synchronization signal; acquire an offset of the local clock with respect to the time master based on a result of the data exchange; correct the local clock in accordance with the offset; and control a machine based on the corrected local clock.

The invention relates to the technical field of communication, and discloses an on-chip clock controller and a power consumption control method thereof, and a computer readable storage medium, and the method comprises the steps: generating a differential delay control signal according to a scanning enable signal and a configuration signal of a test data register; generating a clock enable signal and a clock selection signal according to the scanning enable signal; determining a target clock from the clock sources through the clock selection signal; and determining an output sequence of the target clocks through the differential delay control signal, and controlling the target clocks to be sequentially output according to the output sequence through the clock enable signal. Through the mode, clock source switching and output are accurately controlled through the clock enable signal and the clock selection signal, the target clock is controlled to be output in sequence through the differential delay control signal, the register is prevented from capturing data at the same time, the instantaneous power consumption peak value is effectively reduced, and the power consumption is reduced. Therefore, the instantaneous power consumption of the chips of the plurality of clock sources during the scanning test is reduced.

A processor comprises an execution unit and a performance switching module coupled to the execution unit. The performance switching module includes a control unit, a clock control unit, a voltage control unit and a multi-cycle path control unit. The control unit is configured to output at least one control instruction according to a performance requirement of the processor. The clock control unit is configured to receive a clock adjustment instruction on the at least one control instruction to adjust a clock rate provided to the execution unit. The voltage control unit is configured to receive a voltage adjustment instruction of the at least one control instruction to adjust a supplied voltage provided to the execution unit. The multi-cycle path control unit is configured to receive a path adjustment instruction of the at least one control instruction to adjust a cycle number of the instruction execution cycle of the execution unit.

The invention discloses a latch, relates to the field of integrated circuit design, and aims to solve the problem that the error rate of circuit output level is relatively high after a plurality of storage nodes of a latch circuit are impacted by particles in the prior art. The latch at least comprises an input module, a clock control module, a storage module and an output module, the first end of an input module is connected with the input end of the latch, and the second end of the input module is connected with the input end of the storage module; the output end of the storage module is connected with the first end of an output module; the second end of the output module is connected with the output end of the latch, and the input end of the clock control module is connected with the clock signal input end; the output end of the clock control module is respectively connected with the input module and the output module; the latch is used for generating an inverse signal of a corresponding level of the target node by using the storage module when particle collision occurs to the target node; therefore, the accuracy of circuit output level after a plurality of storage nodes are impacted by particles at the same time is improved.

A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engines is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address, The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

The invention provides a low-power-consumption SOC optimization method and system. The method comprises the following steps: periodically sampling interface states of a plurality of interfaces; periodically determining a joint weight, wherein the joint weight is used for indicating the relevance among the interfaces; determining the relevance between the interfaces and the behaviors based on the corresponding relation between the interface states of the plurality of historical interfaces and the actual behaviors; determining a prediction behavior of the current period based on the relevance between the interface and the behavior, the interface state of the current period and the joint weight of the current period; and determining a target clock domain and a target power supply domain based on the prediction behavior of the current period, the first corresponding relation and the second corresponding relation, and triggering a control strategy of a power supply and a clock based on the target clock domain and the target power supply domain. Under different working modes, power supply, clock and data storage strategies of multiple modules are dynamically coordinated, system-level power consumption optimization is achieved, and meanwhile rapid wakeup and data integrity are ensured.

The embodiment of the invention discloses an integrated circuit device and an internal data transmission control method of the integrated circuit device, which are invented for reducing the power consumption of the integrated circuit device. The integrated circuit device includes: a data forwarding unit connected to an upstream unit that transmits or forwards data and to a downstream unit that receives or forwards data; the first input end of the clock gating unit is connected with the normally open clock, and the second input end of the clock gating unit is used for inputting a clock control signal; and the output end of the clock gating unit is connected with the clock input end of the data forwarding unit, so that the clock input end of the data forwarding unit is controlled to have or have no normally open clock signal input according to a clock control signal input by the second input end of the clock gating unit. The method is suitable for data transmission in the chip.

The invention discloses an acoustic signal partial discharge detection system of a distribution network transformer, which is characterized by comprising a multi-sensor acquisition unit, a synchronous clock control unit, a signal preprocessing unit, an edge calculation processing unit and a communication and storage unit, the edge calculation processing unit integrates a cross-band denoising module, a multi-scale feature extraction module, a lightweight neural network diagnosis module and a diagnosis result fusion module, wherein the cross-band denoising module is used for performing joint denoising on audible sound and ultrasonic frequency band signals. According to the invention, a set of partial discharge detection scheme for a distribution network transformer scene is established, and the scheme flow comprises denoising, feature extraction, neural network training and diagnosis. According to the scheme, audible audio frequency band and ultrasonic frequency band data are covered, and interference generated by mechanical vibration of the transformer in the ultrasonic frequency band is removed through a soft threshold value of wavelet transformation and a pulse detection denoising algorithm.