485 results about "Clock control" patented technology

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

The invention discloses a current and voltage signal synchronous correction and output method and system, and relates to the technical field of power system analysis and control. Compared with a previous current and voltage signal correction method, the method solves the problems that traditional multi-channel signal acquisition depends on conventional clock control, and synchronization precision is insufficient; a conventional sampling circuit is weak in anti-interference capability. The problem that an existing scheme lacks efficient error prediction and dynamic optimization capability is solved. Through a multi-channel FPGA clock synchronization and double-differential sampling technology, complete acquisition of high-frequency transient characteristics of voltage and current signals is ensured; a dynamic calibration algorithm and multi-stage composite filtering are combined, so that common-mode interference and non-linear errors are effectively suppressed; and finally, through optical fiber isolation output and intelligent feedback control, signal full-link synchronous correction is realized, the electric energy metering error can be reduced, the fault positioning precision is improved, the characteristics of high precision, strong anti-interference and low energy consumption are realized, and a reliable data reference is provided for intelligent power grid and new energy grid connection.

The invention discloses a multi-channel parallel sampling high-dynamic response analog-to-digital conversion method, system and equipment and a storage medium, and belongs to the technical field of power electronics and signal processing, and the method comprises the steps: configuring a high-speed analog-to-digital converter channel to form a parallel sampling module, carrying out the alternate sampling of an input power grid analog signal, and generating a discrete sampling sequence group; inputting to a control unit to extract feature data, and calculating to obtain a fluctuation feature value; constructing a channel clock control vector, sending the channel clock control vector to each high-speed analog-to-digital converter channel, adjusting a sampling trigger moment, and re-executing analog signal sampling to obtain a sampling sequence after phase compensation processing; performing waveform reconstruction processing to obtain continuous reconstruction waveform data; and performing electric energy integral operation, and outputting a dynamic metering result. According to the invention, the problems of slow response, sampling distortion and large metering error of the analog-to-digital conversion system under the conditions of frequency fluctuation, unsteady disturbance and bidirectional power in the prior art are solved.

Embodiments relate to a level shifter including a first circuit unit configured to output a start signal, a reset signal, and a node charge signal to a gate driver in response to a start control signal and a node charge control signal that are input from a timing controller, a second circuit unit configured to output an output erase signal and a clock shift stop signal in response to the start signal and the reset signal, and a third circuit unit configured to generate a clock signal based on a clock control signal input from the timing controller and output the generated clock signal to the gate driver in response to the output erase signal and the clock shift stop signal that are output from the second circuit unit, a display device including the same, and a method of driving the display device.

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

The invention relates to the technical field of earthquake and acoustic exploration, and discloses a signal acquisition and transmission method, device, equipment and medium based on a main control unit, and the method comprises the steps: generating a sampling clock signal and a time counting signal, driving an analog-to-digital conversion unit to obtain a digital acquisition signal, and reading equipment state parameters; after the timestamp is added, the digital signal is stored in the first cache unit, the state data after the timestamp is added is stored in the second cache unit, the data signal cache unit is written into a first FLASH partition after being full, and the state data cache unit is written into a second FLASH partition after being full. And after data is read from the FLASH, differential signals are output through the multi-wire parallel interface, the logic processing unit and the serialization unit. According to the invention, power consumption is reduced through unified power management and optimization of clock control and a dormancy mechanism, and transmission bandwidth is improved in combination with high-speed differential output, so that both low power consumption and high efficiency are realized.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

A method may include generating a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate. The method may include disconnecting the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate, and generating a second clock path, wherein the mesh is connected to a second CCL. The method may include generating a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree. Finally, the method may include generating a second clock tree in the second clock path between the second CCL and a second sequential gate.

A control system includes: a time master configured to periodically transmit synchronization signals for time synchronization via a network; and circuitry connected to the time master via the network, wherein the circuitry includes a local clock and is configured to: periodically determine, for every two or more receptions of the synchronization signal via the network, a communication timing so that a frequency of the communication timing is reduced from a transmission frequency of the synchronization signal; periodically perform, in accordance with the communication timing periodically determined with the reduced frequency, data exchange with the time master including transmission of a response signal to the synchronization signal; acquire an offset of the local clock with respect to the time master based on a result of the data exchange; correct the local clock in accordance with the offset; and control a machine based on the corrected local clock.

The invention relates to the technical field of communication, and discloses an on-chip clock controller and a power consumption control method thereof, and a computer readable storage medium, and the method comprises the steps: generating a differential delay control signal according to a scanning enable signal and a configuration signal of a test data register; generating a clock enable signal and a clock selection signal according to the scanning enable signal; determining a target clock from the clock sources through the clock selection signal; and determining an output sequence of the target clocks through the differential delay control signal, and controlling the target clocks to be sequentially output according to the output sequence through the clock enable signal. Through the mode, clock source switching and output are accurately controlled through the clock enable signal and the clock selection signal, the target clock is controlled to be output in sequence through the differential delay control signal, the register is prevented from capturing data at the same time, the instantaneous power consumption peak value is effectively reduced, and the power consumption is reduced. Therefore, the instantaneous power consumption of the chips of the plurality of clock sources during the scanning test is reduced.

A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engines is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address, The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

The invention provides a low-power-consumption SOC optimization method and system. The method comprises the following steps: periodically sampling interface states of a plurality of interfaces; periodically determining a joint weight, wherein the joint weight is used for indicating the relevance among the interfaces; determining the relevance between the interfaces and the behaviors based on the corresponding relation between the interface states of the plurality of historical interfaces and the actual behaviors; determining a prediction behavior of the current period based on the relevance between the interface and the behavior, the interface state of the current period and the joint weight of the current period; and determining a target clock domain and a target power supply domain based on the prediction behavior of the current period, the first corresponding relation and the second corresponding relation, and triggering a control strategy of a power supply and a clock based on the target clock domain and the target power supply domain. Under different working modes, power supply, clock and data storage strategies of multiple modules are dynamically coordinated, system-level power consumption optimization is achieved, and meanwhile rapid wakeup and data integrity are ensured.

The invention discloses an acoustic signal partial discharge detection system of a distribution network transformer, which is characterized by comprising a multi-sensor acquisition unit, a synchronous clock control unit, a signal preprocessing unit, an edge calculation processing unit and a communication and storage unit, the edge calculation processing unit integrates a cross-band denoising module, a multi-scale feature extraction module, a lightweight neural network diagnosis module and a diagnosis result fusion module, wherein the cross-band denoising module is used for performing joint denoising on audible sound and ultrasonic frequency band signals. According to the invention, a set of partial discharge detection scheme for a distribution network transformer scene is established, and the scheme flow comprises denoising, feature extraction, neural network training and diagnosis. According to the scheme, audible audio frequency band and ultrasonic frequency band data are covered, and interference generated by mechanical vibration of the transformer in the ultrasonic frequency band is removed through a soft threshold value of wavelet transformation and a pulse detection denoising algorithm.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

The invention relates to the technical field of testability design, and discloses an on-chip clock controller and test equipment, the on-chip clock controller comprises a main clock control circuit, the functional clock input end of the main clock control circuit is connected with a phase-locked loop output clock, and the clock output end of the main clock control circuit is connected to a main frequency domain receiving node so as to output a main frequency clock signal to the main frequency domain receiving node; the functional clock input end of the slave clock control circuit is connected with the clock output end of the master clock control circuit, and the clock output end of the slave clock control circuit is connected to a frequency division domain receiving node so as to output a frequency division clock signal to the frequency division domain receiving node; wherein the master clock control circuit and the slave clock control circuit are controlled by external slave enable signals, and a data interaction channel is arranged between the master frequency domain receiving node and the frequency division domain receiving node. By cascading the master clock control circuit and the slave clock control circuit and constructing the data interaction channel, dynamic collaborative testing of the master frequency domain and the frequency division domain is realized, and the problem of delay fault detection of the multi-frequency-domain integrated circuit is solved.

The embodiment of the invention provides a clock control circuit, a memory and a clock control method, and the clock control circuit comprises a delay adjustment circuit which is configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a judgment result signal, and when the memory is in a duty ratio adjustment training mode, adjusting the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal according to the judgment result signal, or adjusting the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal, outputting a first target clock signal, and outputting a second target clock signal. A second target clock signal, a third target clock signal and a fourth target clock signal; the judgment circuit is electrically connected with the delay adjustment circuit, and is configured to record the self-refreshing mode exit moment of the memory and the phase sequence of the first phase clock signal and the third phase clock signal, and compare the phase sequence with the last self-refreshing mode exit moment and the phase sequence of the first phase clock signal and the third phase clock signal; and outputting a judgment result signal according to whether the two phase sequences are consistent or not. The embodiment of the invention is at least beneficial to improving the phase difference among the four-phase clock signals.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

The invention discloses a clock control method of a multi-channel driving system for DAC time division multiplexing in an optical computing system, which comprises the following steps: S101, acquiring a time interval from an edge moment when a control signal of a sampling control circuit jumps from an effective state to an invalid state to a stable holding state at an initial temperature; s102, acquiring the time interval of the DAC from the updating of the input data to the stabilization of the analog output voltage of the DAC; s103, target compensation delay needed by DAC input data is obtained, and the target compensation delay meets the requirement that after the control signal enters the invalid state, analog output of the DAC is kept stable and unchanged within the establishment keeping time; and S104, performing delay processing of target compensation delay on the input data of the DAC by using a delay circuit arranged at the input end of the DAC, and inputting the data into the DAC. According to the invention, DAC data updating and the working time sequence of the sampling hold circuit can be coordinated, and sampling errors caused by time sequence conflicts are avoided.

A control circuit includes: an input sampling circuit, configured to perform sampling processing on an initial command address signal based on a first clock signal to generate an intermediate command address signal; a gating generation circuit, configured to generate a first gating enable signal based on the intermediate command address signal and perform pulse width adjustment on the first gating enable signal based on a reset signal to generate a first gating signal; and a clock control circuit, configured to perform control processing on a second clock signal based on the first gating signal to generate a command clock signal. There is an association relationship between the level state of the first gating enable signal and the intermediate command address signal.

The invention relates to a LINK-JOINT asymmetric large delay matching unit based on a Schmitt trigger and application of the LINK-JOINT asymmetric large delay matching unit. The large delay matching unit comprises an input stage circuit used for realizing inversion and preliminary transmission of signals; an intermediate stage circuit for amplifying the signal and introducing a delay; the inverted proportional tube circuit is used for further increasing the delay time of the signal and realizing voltage following and amplification; the output stage circuit is used for outputting the processed signal; the auxiliary circuit provides a feedback mechanism, the input stage circuit, the intermediate stage circuit, the inverted proportional tube circuit and the output stage circuit are respectively provided with a pair of complementary PMOS (P-channel Metal Oxide Semiconductor) tubes and NMOS (N-channel Metal Oxide Semiconductor) tubes, the auxiliary circuit is provided with two NMOS tubes of which the sources are connected to the same line, an input signal I is connected with the input stage circuit, and an output signal O is connected with the output stage circuit. The large delay matching unit can be applied to an asynchronous self-clock control system of a Bluetooth chip, and the large delay matching unit can be used between nodes of a data path in a delay matching circuit module.

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

A digital phase-locked loop (PLL) circuit is provided, comprising: a synchronization control module configured to generate an input characterization signal representing the periodic change of the input periodic signal relative to the base clock signal based on a base clock signal and an input periodic signal; a counting control module configured to generate a clock counting result representing the multiple relationship between the period of the input characterization signal and the period of the base clock signal based on the base clock signal and the input characterization signal; an arithmetic control module configured to generate a base clock control variable based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and to generate an output clock control variable based on the clock counting result; and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate an output clock signal based on the output control signal and the base clock signal.

The invention relates to the technical field of sequential control, and discloses a sequential logic control circuit for a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter), which comprises an analog signal acquisition circuit for receiving and preprocessing an initial input signal; the noise shaping circuit is used for performing frequency spectrum shaping on quantization noise in the analog signal and generating the analog signal subjected to noise shaping; the successive approximation type analog-to-digital converter is used for performing bit-by-bit comparison with the analog signal subjected to noise shaping and gradually completing conversion from the analog signal to the digital signal from the highest bit to the lowest bit; and the clock control circuit is used for coordinating sequential logic among the analog signal acquisition circuit, the noise shaping circuit and the successive approximation type analog-to-digital converter. According to the method, frequency spectrum remodeling is carried out on the quantization noise in the signal, the signal-to-noise ratio of the signal is remarkably improved on the premise that the hardware complexity is not additionally increased, and then interference of the noise on follow-up analog-to-digital conversion is reduced.

The present invention discloses a high-end power control circuit based on digital logic and an anti-interference method. The high-end power control circuit includes a digital trigger module, the output end of the digital trigger module is simultaneously connected to the gates of a first PMOS transistor and a second PMOS transistor, and the control end is connected to the output end of the output driving circuit. At this time, the digital trigger module will use the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered during the rising edge period of the output signal, and thus the output end of the digital trigger module is always in a low level state. The anti-interference method is based on the high-end power control circuit to raise the drain potential of the first LDMOS transistor when the output signal is in the rising edge stage, reducing the noise pulse width. The high-end power control circuit has the advantages of simple structure and small chip volume, and the high-end power control circuit and the anti-interference method more effectively eliminate noise interference.

The application discloses a signal receiving device of an electric wave clock and relates to the technical field of electric wave clocks.The electric wave clock comprises an electric wave clock body, a clock control module arranged on the back of the electric wave clock body and a signal receiving module arranged on the outer side of the clock control module; the clock control module and the signal receiving module are connected through wires; the back of the electric wave clock body is provided with a winding mechanism; and the winding mechanism is arranged on the circumferential side of the clock control module.The signal receiving module is separated from the electric wave clock body, the clock control module and the signal receiving module are connected through wires, the signal receiving module is installed outdoors, the winding mechanism is used to wind or release the wires, the signal receiving strength of the signal receiving module is effectively improved, the data transmission stability between the clock control module and the signal receiving module is improved, and the time accuracy of the electric wave clock body is ensured.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The present invention discloses a clock signal selection circuit, which includes a delay chain circuit and a delay locked loop for the clock selection signal. The above clock signal selection circuit includes a negative edge D flip-flop, a first low-level latch, and a selection unit. The selection unit is used to receive a first clock signal and a second clock signal, and the second clock signal is a delayed signal of the first clock signal. The negative edge D flip-flop has its signal input terminal connected to an external control circuit, its clock control terminal is used to receive an externally input trigger signal, and its signal output terminal is connected to the signal input terminal of the first low-level latch. The clock control terminal of the first low-level latch is used to receive the second clock signal, and its signal output terminal is connected to the selection unit to control the selection unit to output the first clock signal or the second clock signal. The control signal is processed by the negative edge D flip-flop and the first low-level latch to control the operation of the selection unit, avoiding the selection unit from outputting the second clock signal when the second clock signal is at a high level, so as to avoid the generation of glitches.