Clock control circuit and clock control method

Abstract

A clock control circuit which includes a frequency multiplying interpolator for generating and outputting multiphase clocks by frequency multiplying an input clock; a switch for outputting two of the multiphase clocks input thereto from the frequency multiplying interpolator; a fine adjusting interpolator, to which the two outputs from the switch are applied, for outputting a signal obtained by internally dividing the phase difference between the two outputs; and a control circuit for controlling the switching of the switch and varying the internal-division ratio of the fine adjusting interpolator.

Description

[0001] This invention relates to clock control technology and, more particularly, to a clock control circuit and method using an interpolator for frequency multiplication.[0002] In order to deal with an increase in the scale of circuitry that can be integrated on a single chip and in order to handle higher operating frequencies, semiconductor integrated circuits which include a synchronizing circuit that operates upon being supplied with a clock are provided with a clock control circuit for controlling phase and frequency of clocks externally and internally of the chip.[0003] A PLL (Phase-Locked Loop) or a DLL (Delay-Locked Loop) is used conventionally as such a clock control circuit. In semiconductor circuits having system-scale circuitry on a single chip such as an LSI chip (referred to also as a "system on silicon"), it is now necessary to provide a clock control circuit for phase and frequency control for each macroblock within the chip, by way of example.[0004] In addition to u...

AI Technical Summary

Benefits of technology

[0013] Accordingly, an object of the present invention, in one aspect, is to provide a clock control circuit and method as well as a semiconductor integrated circuit device in which center-frequency fluctuation caused when a PLL is used and jitter due to a feedback loop are eliminated to thereby reduce phase error to a major degree.

[0038] reducing jitter of a frequency-multiplied clock by generating multiphase clocks, which are obtained by frequency multiplying an input clock, using a frequency multiplying interpolator which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals;

Problems solved by technology

The clock control circuits according to the prior art described above have a number of problems described below.

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