390results about "Continuous to patterned pulse manipulation" patented technology

A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.

A duty cycle detector includes a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state; a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharging network configured to discharge the first capacitor when the clock is in a first state; and a second discharging network configured to discharge the second capacitor when the clock is in a second state.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

A clock doubler includes a first differential gate and a second differential gate. The first differential gate generates an output clock signal from a first clock signal, a first complementary clock signal, a second clock signal, and a second complementary clock signal and adjusts a duty cycle of the output clock signal based on a first bias control signal. The second differential gate generates a complementary output clock signal from the first clock signal, the first complementary clock signal, the second clock signal, and the second complementary clock signal and adjusts a duty cycle of the complementary output clock signal based on a second bias control signal.

Provided are a duty cycle calibration circuit and method, a chip, and an electronic device. In the duty cycle calibration circuit, through a counting clock signal having a higher clock signal frequency than a calibration clock signal, a counting unit is configured to acquire a number of counting pulses generated in a high-level state and a low-level state of the calibration clock signal within a preset counting period, so as to obtain an actual duty cycle of the calibration clock signal. Compared with a method of acquiring a duty cycle of a calibration clock signal by comparing the calibration clock signal with a reference clock signal, inaccurate measurement of the duty cycle of the calibration clock signal after the reference clock signal is affected can be overcome. Therefore, accuracy of measurement of the duty cycle can be improved, and precision of calibration of the duty cycle can be improved accordingly.

The invention relates to a clock duty ratio adjusting method and system in the technical field of clock adjustment. The clock duty ratio adjusting method comprises the following steps of configuring numerical values of a first current source, a first capacitor, a second current source and a second capacitor based on a target clock duty ratio; performing two-phase non-overlapping processing on the original input clock signal to obtain a first phase clock signal and a second phase clock signal, and performing phase inversion processing on the original input clock signal to obtain an inverted input clock signal; enabling the first current source to charge the first capacitor, and enabling the second current source to charge the second capacitor; acquiring a first voltage and a second voltage, and performing stability detection based on the first voltage and the second voltage; if a stable state is reached, directly outputting an original input clock signal; and if the stable state is not reached, channel impedance adjustment is performed according to the detection result until the stable state is reached, so that the problems that the existing fixed clock duty ratio setting flexibility is relatively low and the application scene compatibility is relatively low are solved.

The invention relates to the technical field of chips, and provides a clock duty ratio calibration method and device, a medium and a program product, and the method comprises the steps: obtaining a plurality of intermediate control values used for representing a duty ratio state through executing a scanning process for multiple times; the at least one intermediate control value is a control value recorded when the duty ratio detection signal is subjected to final state transition in one scanning process; performing statistical processing on the plurality of intermediate control values to generate a final duty ratio control signal; the clock duty cycle is calibrated based on the final duty cycle control signal. According to the invention, the problems of poor anti-interference capability, misjudgment caused by the influence of a circuit environment and low single comparison precision in the prior art are solved, the clock duty ratio distortion caused by the mismatch of a duty ratio detection circuit and environmental noise is avoided, and the bit error rate is effectively reduced.

The present disclosure discloses a duty cycle signal processing circuit and method, and an audio signal processing device. The duty cycle signal processing circuit includes an amplitude detector and an operation unit, where the amplitude detector is configured to detect a first amplitude of an audio signal, generate a second amplitude, and send the second amplitude to the operation unit; and the operation unit is configured to obtain a power supply voltage, and perform operation processing on the second amplitude and the power supply voltage, to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage. In the present disclosure, conversion efficiency of a corresponding power amplifier unit can be improved.

The present application relates to the technical field of radio frequency. Provided are an operating frequency adjustment method for a radio-frequency circuit, and an operating frequency control circuit and a radio-frequency power supply device. The operating frequency adjustment method for a radio-frequency circuit comprises: controlling a radio-frequency circuit to provide output at different operating frequencies to a load; measuring circuit parameters of the radio-frequency circuit during output at each operating frequency; on the basis of the circuit parameters of the radio-frequency circuit during output at each operating frequency, performing calculation to obtain a resonant frequency of the radio-frequency circuit; and adjusting an operating frequency of the radio-frequency circuit to the resonant frequency. The present application can quickly determine a resonant frequency of a radio-frequency circuit, and adjust an operating frequency of the radio-frequency circuit to the resonant frequency.

A clock conditioning circuit includes a duty cycle correction circuit. The duty cycle correction circuit has a first input capacitor, a first self-biasing inverter and a variable capacitor. The first self-biasing inverter has an input coupled to the first input capacitor. The variable capacitor may be coupled to the first input capacitor. The variable capacitor may be configured to receive a first clock signal. A capacitance of the variable capacitor may be programmable by a capacitance control signal.

The invention discloses a clock duty ratio adjusting circuit. The clock duty ratio adjusting circuit comprises an integrator, an adjusting control unit, a charging and discharging unit, a first shaping unit and a phase detection unit. The integrator is used for generating a control signal based on a clock output signal and a reference signal; the adjusting control unit is used for generating an adjusting signal based on power supply voltage and a control signal; the charging and discharging unit is used for generating a charging and discharging signal based on the clock input signal and adjusting the charging and discharging signal based on the adjusting signal; the first shaping unit is used for shaping the charging and discharging signal to generate a shaped signal; the phase detection unit is used for performing phase detection on the clock input signal and the shaping signal to generate a clock output signal. According to the clock duty ratio adjusting circuit, clock signals which are stable in duty ratio and can be well subjected to self-adaptive adjustment can be obtained.

The invention provides a constant-power PWM signal control method, a medium and equipment, and the method comprises the steps: obtaining an initial digital quantity of a resistive load and an initial clock frequency of a PWM signal, and representing the initial digital quantity as a power value of the resistive load at an initial moment; obtaining a first digital quantity of a real-time power value of the resistive load; adjusting the clock frequency of the PWM signal based on the initial digital quantity, the first digital quantity and the initial clock frequency; a second digital quantity is obtained, and the second digital quantity is a fixed value and is used for setting the reference duty ratio of the PWM signal; based on the first digital quantity, the second digital quantity and the adjusted clock frequency, the duty ratio of the PWM signal is adjusted, so that the total period duration of the PWM signal is not changed, and the output power of the power circuit is constant. Furthermore, according to the invention, the stability of the PWM signal frequency and period can be maintained, the accurate control of the output power can be realized, the power MOS tube is ensured to work in a proper switching range, and the reliability and efficiency of the system are improved.

A circuit detects zero crosses in an input-signal and includes a low-pass-filter (LPF) receiving the input-signal and introducing a phase-shift dependent on the frequency thereof. Filter circuitry receives the output of the LPF, applies a fixed phase-shift thereto, and adjusts phase and DC-offset thereof based on control signals to produce a filtered output-signal. Control circuitry has a zero-crossing detector receiving the input-signal and the filtered output-signal, detecting zero-crossings of the input-signal and the filtered output-signal, asserting a digital zero cross signal at each zero crossing, and determining a phase-shift and DC-offset between the input-signal and filtered output-signal. The control circuitry has a controller generating the control signals, based upon the phase-shift and DC-offset, so a total phase-shift between the input-signal and the filtered output-signal is constant and there is a same duty-cycle between the input-signal and the filtered output-signal, providing for accurate zero-crossing detection.

The present invention relates to the technical field of chips, and provides a frequency calibration method, an electronic device, a storage medium and a computer program product, the method comprising: determining a current frequency deviation direction of a tested clock, the current frequency deviation direction being a deviation direction of a current frequency of the tested clock relative to a target frequency; adjusting the calibration step length and the calibration code according to the difference between the current frequency deviation direction and the previous frequency deviation direction; and if the adjusted calibration step length reaches the preset step length, calibrating the output signal frequency of the tested clock according to the adjusted calibration code. According to the method, the overall calibration time is effectively shortened, the defects that the calibration speed is low, the number of iterations is large, and the calibration precision is fixed in a traditional dichotomy method are overcome, and the calibration efficiency and flexibility are remarkably improved.

This disclosure provides methods, devices, and systems for wireless communications. The present implementations more specifically relate to reducing the power consumption of radio frequency (RF) power amplifiers without sacrificing power efficiency. In some aspects, an RF transmitter may include a signal generator, a power amplifier, and a duty cycle controller. The signal generator is configured to produce one or more RF signals based on a modulation scheme, and the power amplifier is configured to amplify the one or more RF signals for transmission over a wireless communication channel. In some implementations, the duty cycle controller may adjust a duty cycle of each RF signal based on data to be transmitted according to the modulation scheme. By changing the duty cycle of the RF signal, the duty cycle controller may toggle the output power of the power amplifier and thus modulate the amplitude of the output waveform to carry the data.

A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.

The invention provides a pulse-triggered sampling channel absolute time delay calibration method, which comprises the following steps of: generating a sine wave signal and a square wave signal through a high-precision dual-channel signal source, triggering a sampling board card by the square wave signal to synchronously sample the sine wave signal, and calculating the initial phase of the sine wave and the corresponding time. Furthermore, square wave signals output by the signal source are converted into sine waves, through dual-channel synchronous sampling, dual-channel initial phases and corresponding time are calculated, and the total time difference of the dual-channel output time difference of the signal source and the dual-channel synchronous sampling time difference of the sampling board card is obtained. Then, the sampling board card synchronously samples the same high-frequency sine wave signal through double channels, and the double-channel synchronous sampling time difference is obtained; and finally, changing the frequency of the signal source, analyzing the relationship between the time sequence of the square wave triggering sampling sine wave signal and the signal source dual-channel output time difference sequence, and performing inverse proportion fitting by taking the signal frequency as an independent variable, thereby finally obtaining the triggering delay of the sampling board card.

The present disclosure provides an integrated circuit, which includes a divider stage, a frequency trimming stage, a voltage control stage, and a logic stage. The divider stage is configured to generate a first clock signal by dividing a frequency of an input clock signal. The frequency trimming stage is configured to add a first delay to the first clock signal to generate a second clock signal. The voltage control stage is configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal. The logic stage is configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal.

According to the clock signal detection circuit disclosed by the invention, the functions of level shifting and voltage extraction of clock differential signals are integrated into the same level of circuit, so that compared with a two-level scheme that the clock differential signals are shifted first and then the peak values of the clock differential signals are sampled in an existing structure, the transmission delay of the signals is reduced; and false triggering caused by noise is avoided by adopting the hysteresis comparison circuit, so that the signal detection circuit provided by the embodiment of the invention improves the detection speed while ensuring the detection precision. In addition, the logic circuit adopts an RS trigger, so that the stability of a hysteresis interval is improved, and the transmission delay of the signal is further reduced.

The invention discloses a duty ratio adjusting circuit and a memory. The duty ratio adjusting circuit comprises a duty ratio adjusting link, a duty ratio detector and a state machine, and the duty ratio adjusting link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; the duty ratio detector is coupled with the duty ratio adjusting link so as to generate a corresponding detection signal based on the detected duty ratio of the output clock signal; the state machine is coupled with the duty ratio detector so as to generate a corresponding control code based on the detection signal; the duty ratio adjusting link comprises a plurality of inverter units connected in series, a first adjusting link and a second adjusting link. The first adjusting link and the second adjusting link are both coupled to the same intermediate node of the duty ratio adjusting link. Through the above mode, the first adjusting link and the second adjusting link are coupled to the same intermediate node of the duty ratio adjusting link, so that the time delay of the duty ratio adjusting circuit can be reduced.

A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.

The signal generator includes the following: an oscillation generation circuit, configured to generate an initial oscillation signal based on an oscillation control signal; a duty cycle correction circuit, connected to an output end of the oscillation generation circuit and configured to adjust a duty cycle of the initial oscillation signal based on a duty cycle control signal, to generate an adjusted oscillation signal; an output interface, connected to an output end of the duty cycle correction circuit and configured to output the adjusted oscillation signal to an external test system; and an amplitude adjustment circuit, connected to the output end of the duty cycle correction circuit and configured to adjust an amplitude of the adjusted oscillation signal based on an amplitude control signal, to generate a test signal.

A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.

Reduce radiated noise through frequency spreading of clock signals. [Solution] The clock signal generation circuit (10) includes a first modulation signal generation circuit (11) that generates a first modulation signal (Sm1) having a first frequency (f1), a second modulation signal generation circuit (12) that generates a second modulation signal (Sm2) having a second frequency (f2) lower than the first frequency, a signal synthesis circuit (13) that generates a synthetic modulation signal (Smc) by synthesizing the first modulation signal and the second modulation signal, and an oscillator (14) that generates a clock signal (CLK) having a frequency corresponding to the synthetic modulation signal.

A method is provided for reducing common mode voltages in a system that includes an inverter connected to a motor by a long cable by controlling switches of the inverter to generate voltage vectors that emulate a three-phase sinusoidal waveform by switching between adjacent active vectors and active vectors that are separated by 180 degrees, determining whether a phase angle of the vectors is increasing or decreasing, determining a decision angle within the sector which is a function of a duty cycle offset and a modulation index; and applying duty cycle manipulation rules, including: responding to an increasing phase angle that is less than the decision angle by setting a duty cycle of the adjacent active vectors to a duty cycle high value; and responding to an increasing phase angle that is greater than 60 degrees minus the decision angle by setting the duty cycle to a low value.

An all-digital duty cycle corrector and a method for correcting a duty cycle of an output clock are provided. The all-digital duty cycle corrector includes a duty cycle adjustment circuit, an asynchronous sampler, a counter and a correction control circuit. The duty cycle adjustment circuit performs duty cycle adjustment on an input clock to generate the output clock according to a digital control code. The asynchronous sampler performs asynchronous sampling on the output clock to generate N sampling results at N time points, respectively. The counter counts a number of first logic values among the N sampling results to generate a counting result. The correction control circuit compares the counting result with a reference value to generate a comparison result, and selectively adjusts the digital control code according to the comparison result, in order to correct the duty cycle of the output clock.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

The invention discloses a phase coding optoelectronic oscillator with an adjustable duty ratio and an implementation method thereof, and relates to the technical field of photoelectricity. The optoelectronic oscillator comprises a laser, a Mach-Zehnder modulator, a single-mode fiber, a photoelectric detector, an electric amplifier, an electric band-pass filter and an electric power divider which are connected in sequence; a direct current port of the intensity modulator is connected with the function generator, one path of the electric power divider serves as output, and the other path is connected with a radio frequency port of the intensity modulator; the output voltage of the preset function generator jumps between the two linear bias points and the minimum bias point of the Mach-Zehnder modulator, so that the direct output of the phase-coded microwave signal with the adjustable duty ratio is realized. According to the invention, the coherence of the phase coding microwave signal is good, the phase noise is low, the duty ratio is adjustable, the coding flexibility is high, the structure is simple, and the equipment cost is low.

The invention provides a duty ratio correction circuit, a control chip and electronic equipment, and belongs to the technical field of artificial intelligence chips, and the duty ratio correction circuit comprises a first cross coupling pair transistor which comprises a first output end and a second output end; the first input circuit comprises a first connecting end, a first grounding end and M first branches connected between the first connecting end and the first grounding end, each first branch comprises a first switch and a first switching tube which are connected in series, and the first connecting end is connected with the first output end; the second input circuit comprises a second connecting end and a second grounding end, and the second connecting end is connected with the second output end; one of the positive phase input end and the negative phase input end of the comparator is connected with the first connecting end, and the other one is connected with the second connecting end; the control device is used for adjusting the closing number of the first switches according to level signals output by the output end of the comparator. In the process, the two input circuits do not need to be corrected one by one, and the time spent on correcting the duty ratio is shortened.

The application discloses an RC oscillator circuit, relates to the technical field of integrated circuits, and aims at the problem that current RC oscillators cannot flexibly adjust the duty cycle of output square wave signals, and provides an RC oscillator circuit, which is characterized in that a first switch is connected with an adjustable capacitor at the output end of a square wave signal generating module; when the square wave signal output by the square wave signal generating module is at a certain level stage, the first switch is closed to connect the adjustable capacitor to the output end of the square wave signal generating module, and the connected adjustable capacitor can cause a delay when the square wave signal is flipped from the current level to another level; since the capacitance value of the adjustable capacitor is adjustable, the delay caused by the square wave signal when the square wave signal is flipped is adjustable, so that the effect that the duty cycle of the square wave signal can be freely adjusted is achieved.