233results about "Continuous to patterned pulse manipulation" patented technology

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

The invention relates to the technical field of chips, and provides a clock duty ratio calibration method and device, a medium and a program product, and the method comprises the steps: obtaining a plurality of intermediate control values used for representing a duty ratio state through executing a scanning process for multiple times; the at least one intermediate control value is a control value recorded when the duty ratio detection signal is subjected to final state transition in one scanning process; performing statistical processing on the plurality of intermediate control values to generate a final duty ratio control signal; the clock duty cycle is calibrated based on the final duty cycle control signal. According to the invention, the problems of poor anti-interference capability, misjudgment caused by the influence of a circuit environment and low single comparison precision in the prior art are solved, the clock duty ratio distortion caused by the mismatch of a duty ratio detection circuit and environmental noise is avoided, and the bit error rate is effectively reduced.

The present invention relates to the technical field of chips, and provides a frequency calibration method, an electronic device, a storage medium and a computer program product, the method comprising: determining a current frequency deviation direction of a tested clock, the current frequency deviation direction being a deviation direction of a current frequency of the tested clock relative to a target frequency; adjusting the calibration step length and the calibration code according to the difference between the current frequency deviation direction and the previous frequency deviation direction; and if the adjusted calibration step length reaches the preset step length, calibrating the output signal frequency of the tested clock according to the adjusted calibration code. According to the method, the overall calibration time is effectively shortened, the defects that the calibration speed is low, the number of iterations is large, and the calibration precision is fixed in a traditional dichotomy method are overcome, and the calibration efficiency and flexibility are remarkably improved.

A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.

The present disclosure provides an integrated circuit, which includes a divider stage, a frequency trimming stage, a voltage control stage, and a logic stage. The divider stage is configured to generate a first clock signal by dividing a frequency of an input clock signal. The frequency trimming stage is configured to add a first delay to the first clock signal to generate a second clock signal. The voltage control stage is configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal. The logic stage is configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal.

According to the clock signal detection circuit disclosed by the invention, the functions of level shifting and voltage extraction of clock differential signals are integrated into the same level of circuit, so that compared with a two-level scheme that the clock differential signals are shifted first and then the peak values of the clock differential signals are sampled in an existing structure, the transmission delay of the signals is reduced; and false triggering caused by noise is avoided by adopting the hysteresis comparison circuit, so that the signal detection circuit provided by the embodiment of the invention improves the detection speed while ensuring the detection precision. In addition, the logic circuit adopts an RS trigger, so that the stability of a hysteresis interval is improved, and the transmission delay of the signal is further reduced.

A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.

Reduce radiated noise through frequency spreading of clock signals. [Solution] The clock signal generation circuit (10) includes a first modulation signal generation circuit (11) that generates a first modulation signal (Sm1) having a first frequency (f1), a second modulation signal generation circuit (12) that generates a second modulation signal (Sm2) having a second frequency (f2) lower than the first frequency, a signal synthesis circuit (13) that generates a synthetic modulation signal (Smc) by synthesizing the first modulation signal and the second modulation signal, and an oscillator (14) that generates a clock signal (CLK) having a frequency corresponding to the synthetic modulation signal.

A method is provided for reducing common mode voltages in a system that includes an inverter connected to a motor by a long cable by controlling switches of the inverter to generate voltage vectors that emulate a three-phase sinusoidal waveform by switching between adjacent active vectors and active vectors that are separated by 180 degrees, determining whether a phase angle of the vectors is increasing or decreasing, determining a decision angle within the sector which is a function of a duty cycle offset and a modulation index; and applying duty cycle manipulation rules, including: responding to an increasing phase angle that is less than the decision angle by setting a duty cycle of the adjacent active vectors to a duty cycle high value; and responding to an increasing phase angle that is greater than 60 degrees minus the decision angle by setting the duty cycle to a low value.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

The invention discloses a phase coding optoelectronic oscillator with an adjustable duty ratio and an implementation method thereof, and relates to the technical field of photoelectricity. The optoelectronic oscillator comprises a laser, a Mach-Zehnder modulator, a single-mode fiber, a photoelectric detector, an electric amplifier, an electric band-pass filter and an electric power divider which are connected in sequence; a direct current port of the intensity modulator is connected with the function generator, one path of the electric power divider serves as output, and the other path is connected with a radio frequency port of the intensity modulator; the output voltage of the preset function generator jumps between the two linear bias points and the minimum bias point of the Mach-Zehnder modulator, so that the direct output of the phase-coded microwave signal with the adjustable duty ratio is realized. According to the invention, the coherence of the phase coding microwave signal is good, the phase noise is low, the duty ratio is adjustable, the coding flexibility is high, the structure is simple, and the equipment cost is low.

The invention provides a duty ratio correction circuit, a control chip and electronic equipment, and belongs to the technical field of artificial intelligence chips, and the duty ratio correction circuit comprises a first cross coupling pair transistor which comprises a first output end and a second output end; the first input circuit comprises a first connecting end, a first grounding end and M first branches connected between the first connecting end and the first grounding end, each first branch comprises a first switch and a first switching tube which are connected in series, and the first connecting end is connected with the first output end; the second input circuit comprises a second connecting end and a second grounding end, and the second connecting end is connected with the second output end; one of the positive phase input end and the negative phase input end of the comparator is connected with the first connecting end, and the other one is connected with the second connecting end; the control device is used for adjusting the closing number of the first switches according to level signals output by the output end of the comparator. In the process, the two input circuits do not need to be corrected one by one, and the time spent on correcting the duty ratio is shortened.

The application discloses an RC oscillator circuit, relates to the technical field of integrated circuits, and aims at the problem that current RC oscillators cannot flexibly adjust the duty cycle of output square wave signals, and provides an RC oscillator circuit, which is characterized in that a first switch is connected with an adjustable capacitor at the output end of a square wave signal generating module; when the square wave signal output by the square wave signal generating module is at a certain level stage, the first switch is closed to connect the adjustable capacitor to the output end of the square wave signal generating module, and the connected adjustable capacitor can cause a delay when the square wave signal is flipped from the current level to another level; since the capacitance value of the adjustable capacitor is adjustable, the delay caused by the square wave signal when the square wave signal is flipped is adjustable, so that the effect that the duty cycle of the square wave signal can be freely adjusted is achieved.

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

The present invention provides a signal synchronization device and a digital signal output device. A digital circuit counts a first frequency signal to generate a count value, generates an output voltage according to the count value, and an analog circuit generates a feedback signal according to the output voltage. A synchronization circuit samples the feedback signal according to a second frequency signal to generate a synchronization signal. A control circuit generates a voltage control signal according to the second frequency signal and the synchronization signal to control the digital circuit to stop counting the first frequency signal, wherein the frequency of the first frequency signal is lower than the frequency of the second frequency signal.

A duty cycle correction (DCC) circuit (100) for use in relation to differential signal communications, a method of providing duty cycle correction, and communications systems and methods employing same, are disclosed herein. In one example embodiment, the circuit (100) includes a differential signal inverter circuit (110, 112) including first and second inverter circuits (132, 134), each of which has a respective inverter and respective first and second transistor devices (134, 136) respectively coupled between the respective inverter and first and second voltages (138, 140), respectively. The circuit also includes a feedback circuit (111) coupled to respective output ports (106, 108) of the respective first and second inverter circuits and also to respective feedback input ports (A, B, C, D) of the respective transistor devices (134, 136). The feedback circuit operates to provide one or more feedback signals (A, B, C, D) causing one or more of the transistor devices to perform current limiting. Respective duty cycles of output signals respectively are equal or substantially equal based on the current limiting.

A duty cycle correction circuit includes a phase adjustment circuit, a divider circuit, a phase difference detection circuit, and a duty control circuit. The phase adjustment circuit adjusts a duty cycle of a first input clock signal according to a plurality of control codes to generate a duty corrected clock signal. The divider circuit divides the duty corrected clock signal to generate a plurality of multi-phase clock signals. The phase difference detection circuit detects phase differences between the plurality of multi-phase clock signals to generate detection signals. The duty control circuit detects a bang-bang state of the duty corrected clock signal in accordance with the detection signals, changes values of the plurality of control codes by a first unit in accordance with the detection signals until the bang-bang state is detected, and adjusts the value of the plurality of control codes by a second unit smaller than the first unit when the bang-bang state is detected.

A duty cycle correction device and a duty cycle correction method thereof are disclosed. A duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal according to the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal.

A system includes an inverter configured to convert DC power from a battery to AC power, wherein the inverter includes: a pulse demodulator including: an analog timer including: a first stage pulse generator, a second stage pulse generator connected to the first stage pulse generator, and a third stage pulse generator connected to the second stage pulse generator; and a voltage translator including: a voltage divider connected to the first stage pulse generator, the second stage pulse generator, and the third stage pulse generator, and a comparator connected to the voltage divider.

An example apparatus includes; first current source circuitry (270) having a terminal; a first transistor (275) having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry (200); second current source circuitry (250) having a terminal; a second transistor (260) having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor (296) having a first terminal and a second terminal; a capacitor (292) having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier (265) having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

A clock signal duty ratio correction circuit includes: a period indication signal generation circuit configured to operably generate a period indication signal according to a clock signal, wherein a period indication level of the period indication signal is correlated with a period time of the clock signal; a first ramp signal generation circuit configured to operably generate a first ramp signal according to the clock signal; and a clock signal regeneration circuit configured to operably generate a clock regeneration signal according to a triggering of the clock signal and according to a comparison between the first ramp signal and the period indication level, such that the clock regeneration signal has a target duty ratio; wherein a slope of the first ramp signal is correlated with the target duty ratio.

The application provides a duty cycle correction circuit, a method, a control chip and electronic equipment, and belongs to the technical field of artificial intelligence chips.The duty cycle correction circuit comprises a cross-coupled pair of transistors, a first load circuit, a second load circuit and a comparator.The cross-coupled pair of transistors comprises a first switch tube, a second switch tube, a first output end and a second output end.The first load circuit comprises a first connection end and a second connection end, M first branches and a first device.The second load circuit is symmetrically distributed with the first load circuit with respect to the cross-coupled pair of transistors.The duty cycle correction circuit provided by the application does not need to correct two links of CLKP and CLKN separately, significantly shortens the correction period and improves the boot speed.

The invention relates to a DAC clock duty ratio and quadrature phase calibration circuit and a digital regulation and control method. The digital regulation and control method comprises the steps that a four-phase clock generation circuit (1) generates four paths of fixed phase offset clocks based on differential signals; the DCC duty ratio adjusting circuit (2) responds to the duty ratio adjusting signal to adjust the duty ratio of the four paths of fixed phase offset clocks; the QEC phase adjusting circuit (3) responds to the phase adjusting signals to correct the quadrature phases of the four duty ratio adjusting signals; the one-to-three inverter link (4) shapes the four orthogonal clock signals, performs signal shaping processing and outputs a calibration clock; the detection circuit (5) analyzes the calibration clock to generate a detection result; and the digital regulation and control circuit (6) dynamically generates a duty ratio adjustment signal and a phase adjustment signal according to a detection result, so that closed-loop control is formed, and synchronous optimization of the duty ratio and the quadrature phase is realized. The circuit can solve the problems of duty ratio distortion and phase deviation between two groups of I / Q signals existing in the generated four-path fixed phase offset clock.

A control device (1) for controlling an RMS value of an electrical load current (5) at a time-varying load (2), characterized in that the control device (1) is configured to provide a voltage pulse train (4) having a predetermined duty cycle (10) at the time-varying load (2) and in at least one pulse phase (8) of the voltage pulse train (4): - to detect a respective sample value (16) of the electrical load current at the time-varying load (2), wherein the control device (1) is configured to detect the sample value (16) of the electrical load current in a last tenth of the pulse phase (8) and / or during a falling signal edge of a pulse of the voltage pulse train (4), - to determine an actual RMS value (11) of the electrical load current assigned for the sample value (16) of the electrical load current by means of a dependency (17) stored in the control device (1).- to determine a difference value (25) between the actual RMS value (11) of the electrical load current and a target RMS value (6) of the electrical load current, - to determine an adapted duty cycle (26) of the voltage pulse train from the difference value (25) of the electrical load current according to a predetermined procedure, and - to provide an adapted voltage pulse train (27), having the adapted duty cycle (26), to the time-varying load (2).

Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.

The application provides a duty cycle correction circuit and a chip, a pre-charging module is added, and a capacitor can be pre-charged to a predetermined voltage after each comparison of a comparator ends, so that the charging time of a charge pump module on two charging and discharging nodes can be shortened, the analog voltage output by the two charging and discharging nodes can quickly reach the input voltage value at which the comparator can compare in the next comparison, the starting time required by the comparator for each comparison is shortened, the response time and the stabilization time of the loop of the duty cycle correction circuit itself are shortened, the clock duty cycle calibration efficiency is finally improved, and the transmission rate of a signal is improved.

Injection-Locked Digital Oscillator This description relates to an injection-locked digital oscillator (2). An adder (100) adds the first and second digital words (OP2, OP1) and provides a third digital word (RES) as a result, the words being N bits long, with N an integer strictly greater than 1. A register (102) updates the second word from the third word (RES) at each period of a clock signal (clk). A first circuit (200) receives a reference signal (REF) at a natural frequency of one output bit (OUT), and a reference increment, inc_ref. The first circuit calculates a first value (valref) that is selectively equal to and less than the reference increment inc_ref, depending on at least one state of the reference signal.The first circuit provides the first word at least in part by summing the first value and a positive control number, P, the output bit being a bit from the second word. Figure for the abbreviation: Fig. 2.

This application provides a pulse generation method, apparatus, electronic device, and storage medium. The method includes: acquiring an attribute value corresponding to a target pulse signal, the attribute value corresponding to a preset attribute; and generating a pulse corresponding to the target pulse signal based on the attribute value corresponding to the preset attribute. It is understood that a universal pulse generation integrated circuit can be designed and manufactured to generate a pulse corresponding to the target pulse signal based on its attribute value. When it is necessary to generate pulses corresponding to other target pulse signals, only the attribute values ​​of the other target pulse signals need to be input into the pulse generation integrated circuit to generate the corresponding pulses, thereby greatly simplifying the design and application complexity of the pulse generation integrated circuit and improving its versatility to a certain extent.

The invention discloses a radiation hardening foreground calibration circuit and equipment, the foreground calibration circuit comprises a comparator, a first trigger, a counter, an accumulator, a digital-to-analog converter and a radiation hardening unit, the radiation hardening unit comprises a delay module, a second trigger, an XNOR gate and an AND gate, and the delay module and the second trigger delay and synchronize the result signal output by the comparator to obtain a second path of result signal, perform XNOR operation with the original result signal obtained by the first trigger, and then perform AND operation with the clock signal to serve as a response signal of the counter and the accumulator. The invention aims to solve the problem that a space task fails due to the fact that a traditional foreground calibration circuit is easily influenced by a single particle when running in a radiation environment and a single particle function is interrupted, improve the radiation hardening capability of the foreground calibration circuit running in the radiation environment, and realize the radiation hardening optimization design of the foreground calibration circuit.

A broadband impulse generator includes a first delay line and a second delay line that receive an input signal and include a plurality of delay elements connected in series with each other, an oscillation signal generator that generates an oscillation signal having a certain number of pulses during a target impulse duration based on the input signal and an output signal of the first delay line, an envelope signal generator that generates a plurality of envelope signals having a delay duration with each other and having a certain voltage level during the target impulse duration, based on the input signal and an output signal of the second delay line, and an impulse signal generator that generates an impulse signal having the certain number of pulses during the target impulse duration based on the plurality of impulse signals and the oscillation signal.