163results about "Pulse manipulation delay" patented technology

Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.

A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.

A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

In a semiconductor integrated circuit, respective semiconductor circuits are disposed in different regions partitioned in accordance with their operation probabilities per unit time, and a supply voltage and a threshold voltage are correlatively controlled in each region. A target value for controlling the threshold voltage is determined in accordance with the operation probability of the semiconductor circuit. A threshold voltage control circuit controls substrate voltages of p-type and n-type MOS transistors included in the semiconductor circuit so that the threshold voltage can be constant at the target value regardless of the temperature change occurring in use. Simultaneously, a supply voltage control circuit controls the supply voltage for the semiconductor circuit so that an objective operating frequency can be attained. As a result, a semiconductor integrated circuit with low power consumption can be obtained.

A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.

A delay circuit in a semiconductor memory device generates a sense amplifier enable signal having a delay time with respect to the timing of selection of one of memory cells. The delay time corresponds to the largest read time for the memory cell located at the most distant position and has an irregularity reflecting an irregularity in threshold voltage of nMOSFET transfer gates in each memory cell, which affects the read time. An optimum timing for the sense amplifier enable signal can be obtained by the delay circuit irrespective of the irregularity in the threshold voltage of the nMOSFET transfer gates.

A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

A jitter generator produces a jittery test signal for use in performing a jitter test on an integrated circuit (IC) device under test (DUT). The jitter generator includes a programmable delay circuit for delaying a non-jittery input signal with a varying delay controlled by input digital delay control data to produce the test signal. A pattern generator supplies a sequence of delay control data to the programmable delay circuit causing it to produce a desired jitter pattern in the test signal. During a calibration process, a measurement unit feeds the test signal back to the input of the programmable delay circuit, causing the test signal to oscillate with a period proportional to the delay through the delay circuit. The measurement unit then measures the period of the test signal for various values of delay control data and reports measurement results. Based on the measurement results, host equipment then determines an appropriate sequence of delay control data for producing a desired jitter pattern in the test signal and programs the pattern generator to produce that sequence of delay control data during a jitter test. The jitter generator can form a part of a built-in, self-test (BIST) circuit implemented within the DUT itself.

A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.

A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

An inverter type delay circuit, voltage-controlled oscillation circuit, and voltage-controlled delay circuit capable of realizing simplification of circuit configuration, reduction of an effect of power source noise, and reduction of jitter, wherein a delay circuit, voltage-controlled oscillation circuit, and voltage-controlled delay circuit comprised of a plurality of delay stages controlled in drive current in accordance with a bias voltage or a control voltage and determined in delay time by the drive current, adding a change of a power source voltage to the above bias voltage or control voltage by a predetermined ratio and supplying a result of the addition to the above delay stages to suppress the power source voltage dependencies of the delay times of the delay stages, or connecting by a predetermined ratio a plurality of delay stages having different power source voltage dependencies, for example, power source voltage dependencies of opposite delay times, to suppress the power source voltage dependencies of delay times of the delay stages are realized.

A bandpass filter circuit 10 of the present invention includes: transconductance amplifier circuits 1 to 3; a common-mode feedback circuit 4 which outputs a first control signal to the transconductance amplifier circuit 1 so that a D.C. voltage level of a differential output of the transconductance amplifier circuit 1 is at a predetermined level; a common-mode feedback circuit 5 which outputs a second control signal to the transconductance amplifier circuit 2 so that a D.C. voltage level of a differential output of the transconductance amplifier circuit 2 is at a predetermined level; and capacitors C1 to C3. Each of the members are connected as shown in FIG. 1. With the configuration, a bandpass filter circuit capable of adjusting constants such as a Q-value is realized.

A duty cycle correction circuit (10) for receiving an input clock signal (11) and generating an output clock signal (13) having a predetermined duty cycle includes a clock trigger circuit (12) generating the output clock signal (13) having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (22); a charge pump circuit (14) receiving the output clock signal and generating charging and discharging currents for a capacitor (C1) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit (18) receiving the control voltage and generating first and second bias voltages (23, 24) in response to the control voltage; and a delay-locked loop circuit (20) receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.

A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a, 40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a, 40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2). In another embodiment, more than two adder and register units (55) control corresponding multiplexers (56) for selecting clock phases from the voltage-controlled oscillator (30) for application to an output multiplexer (58), which is controlled by a clock control circuit (60) to apply the selected clock phases to the T flip-flop (62). In another embodiment, primary and phase-shifted frequency synthesis circuits (227, 327) receive initialization values (INIT1, INIT2) that establish the phase differential and ensure proper initialization.

A system and method for bitwise deskew. A DQS timing is used as reference, the delays of a plurality of transmission wires are calibrated with reference to a DQS line timing. Other embodiments are described and claimed.