20 results about "Dead time control" patented technology

The application discloses a dead time control circuit and electronic equipment, and belongs to the technical field of electronics. The dead time control circuit comprises an inductive element, a first field effect tube connected with the inductive element, a second field effect tube connected with the inductive element and the first field effect tube, a detection circuit for detecting a first switching state of the first field effect tube, a second switching state of the second field effect tube and a current flow direction of the inductive element, a logic judgment circuit for outputting an adjustment mode signal of a dead time, a first off time and a second off time according to the first switching state, the second switching state and the current flow direction, an operation circuit for outputting a dead time control signal according to the first off time and the second off time in an adjustment direction indicated by the adjustment mode signal, and a time delay circuit, wherein the dead time control signal is used for adjusting a time delay value of the time delay circuit to adjust the dead time of the first field effect tube and the second field effect tube.

The control of the switches S21 to S28 of the DC / DC converter 120 includes a first mode in which all of the switches S21 to S28 of the DC / DC converter 120 are OFF and a plurality of second modes in which at least one of the switches S21 to S28 of the DC / DC converter 120 is ON, and when switching from the first mode to one of the plurality of second modes, a dead time Td is not provided between the first mode and the one of the plurality of second modes.

The utility model discloses a single-phase brushless motor time-delay starting operation module, which mainly comprises a brushless motor main body and a matched control assembly, and comprises two 41F type Hall sensors which are connected in parallel, a common pull-up resistor and the like. The two Hall sensors are symmetrically installed on the two sides of the geometric center line of a stator magnetic pole, the detection faces face a rotor permanent magnet, high and low levels are output through induction of rotor magnetic pole changes, the H-bridge power tube is controlled, and stator coil power supply state switching is achieved. During working, according to the characteristics of the Hall sensor, the motor is controlled to be started and run according to the principle that the motor is firstly turned off and then turned on, and the dead time control unit generates 0.5-2 ms power tube switching delay. According to the module, the starting success rate of the motor is greatly improved, the starting failure risk is effectively reduced, and the vibration amplitude in the starting process is obviously reduced. In the operation stage, the motor efficiency is remarkably improved, and the rotating speed fluctuation is extremely small when the load changes. Moreover, the circuit design of the module is simplified, so that the hardware cost is greatly reduced.

This invention discloses a gate drive monitoring circuit and device, solving the problems of low adjustment flexibility and duty cycle accuracy in existing technologies, and the inability to achieve only a single function. It includes a gate drive feedback module and a gate drive monitoring module connected to a gate drive module. The gate drive feedback module is connected to the gate drive monitoring module. The gate drive monitoring module includes a dead time control unit and a duty cycle compensation unit. The dead time control unit is connected between the gate drive module and the gate drive feedback module, and the duty cycle compensation unit is connected to the gate drive module. This invention can independently achieve automatic adjustment of the dead time of the high-side MOSFET and the low-side MOSFET, improving adjustment flexibility, increasing duty cycle accuracy, and enabling complex and diverse functions.

The invention relates to an active clamping flyback converter and a control method thereof, and belongs to the field of flyback converters. According to the active clamping flyback converter, voltage stabilization of output voltage is achieved through a double-closed-loop control structure composed of a peak current mode loop and a dead time control loop, and the peak current mode loop is used for controlling the conduction time of a main switching tube. And the dead time control loop is used for detecting whether the active clamping flyback converter realizes a soft switching function or not. A double-loop control loop of a peak current mode and a dead time control mode is adopted, the problem that when the active clamping flyback converter is in light load, zero voltage switching is difficult to achieve in the first switching period, and additional loss is caused is solved, the cost of circuit design is effectively reduced, the occupied size is reduced, and the integration level is improved.

The embodiment of the present application discloses a dead time control circuit and method. In a specific embodiment, the circuit comprises a feedback circuit for generating a first enable signal and a second enable signal when a modulation signal is high; wherein the first enable signal is low for controlling the lower tube to be closed; a floating ground circuit for outputting an upper tube gate control signal when the second enable signal is high; and an upper tube gate potential detection circuit for opening the upper tube when the upper tube gate control signal is low. The embodiment automatically adjusts the discharge delay time without any manual setting intervention, ensures that the upper and lower tubes are not connected, and the discharge delay is as small as possible, thereby preventing large peak current from burning the power tube and chip, ensuring the performance of the chip while improving the reliability of the chip.

The invention relates to the technical field of circuits, in particular to a driving circuit, a chip and electronic equipment. According to the driving circuit, a grid voltage detection circuit generates a first detection signal and a second detection signal according to the grid voltage of an upper switching tube and the grid voltage of a lower switching tube; the dead time control circuit determines a first duration and a second duration according to the first detection signal and the second detection signal, and outputs a second signal and a fourth signal; the edge detection circuit outputs a fifth signal and a sixth signal according to the input signal, the second signal and the fourth signal; the control circuit outputs a first control signal according to the third signal and the fifth signal, and outputs a second control signal according to the third signal and the sixth signal. According to the method, the flexibility and the accuracy of adjustment of the dead time are improved.

The utility model provides a dead time adjusting circuit and an active clamping forward power supply chip, which belong to the technical field of switching power supply control, and comprise a current detection module used for detecting the current flowing through a pin OVLP through the resistance of the pin OVLP to the ground and outputting a digital control logic signal and a mirror current source; the digital control output module is connected with the current detection module and is used for receiving the digital control logic signal and converting the digital control logic signal into a control selection signal so as to determine the selected dead time; the variable current output module is connected with the current detection module and is used for outputting variable current according to the mirror current source so as to provide current required by time delay for the dead zone time selection module; and the dead zone time selection module is connected with the digital control output module and is used for selecting a dead zone time path according to the control selection signal, realizing a time delay function by using the current of the variable current output module, outputting a dead zone time control signal and realizing adjustability of dead zone time.

The invention provides a closed-loop dead time control system and method suitable for an inverter, and the method comprises the steps: detecting the power supply voltage of the inverter, and converting the power supply voltage into a first digital signal; detecting the peak value of the alternating current output by the inverter, and converting the peak value of the alternating current into a second digital signal; inputting the first digital signal and the second digital signal into a preset artificial intelligence model, and calculating to obtain the optimal dead time in the current working state; adjusting the resistance value of a digital resistor according to the optimal dead time so as to change the node voltage in the driving signal generation path; and generating two paths of complementary driving signals based on the adjusted node voltage, and outputting the driving signals to a power tube of an inverter through a driver so as to solve the problem of inaccurate dead time control.

The utility model provides a dead time control circuit and a drive circuit. Wherein the dead time control circuit is provided with a dead time pin. The dead time control circuit comprises a first current source, a first power tube, a voltage balance circuit and a dead time generation circuit. The first current source is coupled to the power supply voltage. The first power tube is coupled in series with the first current source. The input end of the voltage balancing circuit is coupled with the first end of the first power tube, and the output end of the voltage balancing circuit is coupled with the dead time pin. The dead time generation circuit comprises a second power tube and a charging and discharging circuit. The first end of the second power tube is coupled to the power supply voltage, and the second end of the second power tube is coupled to the ground. The first end of the charging and discharging circuit is coupled with the dead time pin, and the second end of the charging and discharging circuit is coupled with the control end of the second power tube. According to the dead time control circuit and the dead time drive circuit provided by the utility model, accurate control of dead time can be realized by accessing corresponding external resistors.

This invention discloses a dead-time control circuit, PCB board, and controller, including a low-side dead-time setting unit, a high-side dead-time setting unit, a valley detection unit, and a trigger switch. The output terminals of the low-side and high-side dead-time setting units are respectively connected to the input terminal of the valley detection unit, and the output terminal of the valley detection unit is connected to the input terminal of the trigger switch. The low-side dead-time setting unit is used to delay the external low-side input signal; the high-side dead-time setting unit is used to delay the external high-side input signal; the valley detection unit is used to determine the lowest voltage moment of the switching node based on the output signals of the low-side and high-side dead-time setting units, and sends a control signal to the trigger switch based on the lowest voltage moment. By introducing the valley detection mechanism, the dead-time control is transformed from static preset to dynamic sensing and response, which is beneficial for optimizing switching losses.

Embodiments described herein provide a wireless power transmitter that dynamically adjusts dead time to reduce power loss. Specifically, a wireless power transmitter includes a transistor circuit for switching a first voltage at a first node and a second voltage at a second node, and an LC circuit coupled between the first node and the second node. The wireless power transmitter also includes a controller coupled to the transistor circuit. The controller is configured to determine whether any one of the first voltage and the second voltage is negative during a dead time of the switching. The controller is configured to increment or decrement the dead time by an adjustment amount depending on whether the negative voltage is detected.

A system comprises one or more sensors for determining sensor data, the sensor data including ambient parameters internal to the enclosure; a controller comprising one or more sensor interfaces configured to communicate with one or more sensors to receive the sensor data; one or more processors; and memory storing computer instructions configured to perform: determining, based on the sensor data, an existence or probability of condensation within the enclosure; and decreasing a dead time of the one or more soft switching mechanisms based on the existence or probability of condensation within the enclosure, the decreasing the dead time increasing heat in the converter circuitry to assist in addressing the existence or probability of condensation.

The application discloses a kind of single-photon detector dead time dynamic control device and method, in the device, drive circuit, for after input signal amplification is loaded to avalanche photodiode cathode;Avalanche extraction amplification circuit is used to filter and amplify first avalanche analog signal, and output second avalanche analog signal;Multi-amplitude discrimination circuit is used to discriminate the amplitude of second avalanche analog signal, and respectively output first avalanche digital signal to dead time processing module, amplitude data to dead time control module;Dead time control module sets signal to dead time processing module to output dead time;Dead time processing module processes first avalanche digital signal according to dead time setting signal and then outputs second avalanche digital signal.The application can dynamically adjust the setting of dead time according to the size of avalanche current amplitude in the detection process, and can improve the maximum count rate under the condition of low post-pulse probability.

The present disclosure provides a driving circuit and a driving chip. The driving circuit comprises a dead time control circuit, a conversion circuit, a bridge circuit and a pull-up circuit; the bridge circuit comprises a first switch tube located at an upper bridge arm and a second switch tube located at a lower bridge arm; the dead time control circuit is used for performing dead time control processing on a low-voltage driving control signal to obtain a first low-voltage logic signal and a second low-voltage logic signal used for driving the second switch tube; the conversion circuit is used for converting the first low-voltage logic signal into a high-voltage logic signal used for driving the first switch tube; and the pull-up circuit is used for accelerating the pull-up speed of the high-voltage logic signal under the control of the first low-voltage logic signal.

The application relates to a GaN HEMT power half-bridge circuit system, which comprises a dead time control circuit (1), a level shift circuit and an upper side logic circuit (2), a logic and control circuit (3), a high side drive (4), a low side drive (5), a current detection circuit (6), a high side device (7), a low side device (8), a diode (D), a first capacitor (C101), an inductor (L), a second capacitor (C102) and a first resistor (R101). The GaN HEMT half-bridge circuit system of the embodiment of the application can reduce the static power consumption of the circuit, improve the performance of the circuit, and has the function of the protection circuit system for preventing the high side and low side devices from being in series; the performance of the half-bridge circuit is improved, the reliability of the circuit is improved, and the risk of equipment damage is reduced.

The application discloses a push-pull converter and a driving method thereof. The push-pull converter comprises a transformer, a first switch tube and a second switch tube connected to a primary side of the transformer, and further comprises a driving circuit, a detection circuit, a dead time control circuit and a logic control circuit. The push-pull converter and the driving method thereof optimize and improve the efficiency by configuring the turn-on and turn-off of the first switch tube and the second switch tube on the primary side according to the characteristics of the push-pull converter. The turn-on speed of the first switch tube and the second switch tube is fast, and the driving in the turn-off stage is controlled in multiple sections. The driving rate in each section can be adjusted to reduce the voltage stress of the first switch tube and the second switch tube. The part of the turn-off stage that does not affect the spike is accelerated, so that the spike is generated only by the magnetizing current. ZVS (zero voltage turn-on) can be realized by setting a large dead time, and the system's ability to correct the magnetic bias is improved.

The invention provides a totem-pole bridgeless PFC current zero-crossing peak suppression method and system, and the method comprises the steps: monitoring an operation signal of a totem-pole bridgeless PFC circuit in real time, judging whether the circuit is in a zero-crossing state or not according to a preset threshold value, and determining a zero-crossing type at the same time; when it is determined that the circuit is in a zero-crossing state, dead time control is started immediately, and all switching tubes are turned off; after dead zone time control is finished, soft start control is carried out on a target switching tube of the high-frequency bridge arm according to the zero-crossing type, and the duty ratio is gradually increased to a target value from an initial value from the first switching period to the Nth switching period; after soft start control is completed, bipolar control is executed, the totem-pole bridgeless PFC circuit is regarded as a full-bridge rectification structure, and the midpoint voltage of a bridge arm is controlled to adjust the inductive current; and after the bipolar control lasts for M second switching periods, quitting the zero-crossing control mode, and executing conventional double-closed-loop control. According to the invention, the current zero-crossing peak problem of the totem-pole bridgeless PFC can be effectively suppressed.

The invention discloses a quick response dynamic dead time control circuit for a gallium nitride half-bridge driving chip. The circuit comprises an input-stage logic circuit, a step-down level shift circuit, a delay matching circuit, a high-side output-stage driving circuit, a low-side output-stage driving circuit, a step-up level shift circuit, a zero-current detection circuit, a slope detection circuit, a dual-threshold voltage detection circuit and a switch node rising edge side dead time error sampling circuit. A switch node falling edge side dead time error sampling circuit, a dead time control signal generating circuit and a dead time adjusting circuit. According to the invention, power tube loss can be effectively reduced while control precision and response speed are considered.

This invention discloses a synchronous discrimination and dynamic dead-time control system for single-photon detectors, comprising a trigger discrimination module, a fan-out and delay module, a gate signal processing module, a single-photon avalanche diode (SPAD), an avalanche signal extraction module, an avalanche synchronous discrimination module, and a dynamic dead-time processing module connected in sequence. The fan-out and delay module is also connected to the avalanche synchronous discrimination module. This invention solves the problems of large time jitter in existing gated single-photon detectors, the inability of the avalanche signal extraction scheme to distinguish between two distorted avalanche signals, and the inability of the dead-time control scheme to distinguish between the correct avalanche signal and the afterpulse signal.