114 results about "Dead time control" patented technology

A resonant switching power converter having adaptive dead time control provides improved efficiency along with reduced EMI/audible noise and component stresses. A dead time between pulses generated by a switching circuit is adaptively set in conformity with a value of the input voltage to the resonant switching power converter and an indication of a magnitude of the current passing through inductive element of the resonant tank of the converter. The indication of the current magnitude may be the switching frequency of the converter, or a measure of line or load current levels. The dead time can be obtained from a look-up table or computed from the current magnitude and input voltage values.

An embodiment apparatus comprises a secondary synchronous rectifier and a secondary gate drive controller coupled to a transformer winding. The secondary gate drive controller is configured to generate a forward gate drive signal for the forward switch and generate a freewheeling gate drive signal for the freewheeling switch, wherein the secondary gate drive controller generates a dead time between the forward gate drive signal and the freewheeling gate drive signal.

A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

A flyback converter includes a primary-side switch that controls conduction of current on a primary side of a transformer and a synchronous rectifier on a secondary side of the transformer. A synchronous rectifier driver controls the conduction of the synchronous rectifier by adaptively adjusting a turn-off threshold of the synchronous rectifier.

The invention relates to a digital self-adaptive dead-time control circuit, belonging to the electronic technical field and relating to an integrated circuit technology and power conversion and motor-driving circuits which adopt a synchronous rectification technology. The digital self-adaptive dead-time control circuit comprises a phase discriminator, a D-trigger, a reversible counter, an n-to-1 multiple selector, (n+1) delay units, two low-flip level inverters, two common inverters and an NOR gate. The phase demodulation comparison of starting signals of an NMOS transistor SR is continued to control the reversible counter to carry out add-subtract count, so as to adjust a delay time unit and control the multiple selector to start the NMOS transistor SR in a suitable clock to further realize the self-adaptive adjustment of dead time. The invention not only avoids the simultaneous conduction of two power tubes caused by overshot dead time, but also avoids the conduction of a body diode caused by overlong dead time, thereby decreasing additional loss caused by the unsuitably set dead time and improving the whole efficiency of the power converter.

There is provided a dead time control method capable of recognizing a critical situation in which a commutating transistor cannot be turned on because of a temporary variation in an output voltage of a synchronous rectifying DC-DC converter and adaptively preventing the commutating transistor from being turned on. The synchronous rectifying DC-DC converter compares an output Voff of an error amplifier with a voltage Vt obtained by multiplying the peak voltage of a ramp by G2. When Voff becomes greater than or equal to Vt, the converter determines that dead time is insufficient to control the switching of the commutating transistor and prevents the commutating transistor from being turned on.

The invention provides a dual-mode synchronous rectification control circuit for a DCM and a CCM, belonging to the technical field of power management. The structure of the circuit is simple, the rectification conduction loss can be effectively reduced, and high efficiency of synchronous rectification is realized. Minimum dead time control is realized by a second negative level detector. A turn-off time shielding module prevents the wrong turn-on of a synchronous rectifier tube M2, and a turn-on time shielding module prevents the wrong turn-off of the synchronous rectifier tube M2. Drain electrodes of LDMOS and DEMOS high voltage devices are used by a first sampling end to bear high voltage, the clamping of a drain end VD of the synchronous rectifier tube M2 by a Zener is avoided, and the current leakage to the ground by the drain end VD of the synchronous rectifier tube M2 is prevented. The high efficiency of synchronous rectification is realized by the above measures together. In addition, a synchronous control module is introduced, and the synchronous rectification in a current continuous mode CCM is realized.

A gate drive circuit including dead time control circuits delaying on periods of switching elements S1, S2 based on a control signal; driving circuits; and monitor circuits. Each of the monitor circuits includes a current source and an N-type FET in which the source is connected to the gate of one of the switching elements; the drain is connected to the current source; and a predetermined voltage is applied to the gate. When an off state of one of the switching elements is detected, the N-type FET Qn outputs an off signal to the dead time control circuit on the other switching element side. Based on the off signal, the dead time control circuit on the other switching element side terminates an operation of delaying the on period of the other switching element.

In a power supply device including a PWM-controlled DC/DC converter which changes an output voltage on the basis of a setting signal, and a control unit, the DC/DC converter includes a circuit for changing a dead-time control voltage in accordance with a control signal. A dead-time control circuit is arranged, which sets the ON duty of a PWM main switching element at a predetermined time constant in accordance with the dead-time control voltage. The control unit outputs the setting signal and control signal. In this arrangement, an input rush current generated in changing the output voltage during operation can be reduced, and the time required for causing the output voltage to reach the setting value can also be shortened.

A half-bridge-type control signal generating circuit outputs two control signals to control directly and drive switching actions of two electronic switches of a half-bridge-type circuit architecture. The half-bridge-type control signal generating circuit comprises an AND-gate logic unit, a NAND-gate logic unit, a circuit protection unit, a function generator, a clock generator, a soft boot unit connected to the clock generator, a sample and hold unit, a first comparator connected to the soft boot unit and the function generator, an OR-gate logic unit connected to the soft boot unit, the first comparator, the AND-gate logic unit and the NAND-gate logic unit, a second comparator connected to the sample and hold unit, the function generator, the AND-gate logic unit and the NAND-gate logic unit, and a dead time control unit connected to the function generator, the AND-gate logic unit and the NAND-gate logic unit.

The invention relates to self-adaptive dead time control. A DC-DC converter comprises a first transistor and a second transistor which are in series connection between a power voltage and the ground and are driven by PWM pulses. A connecting point between the two transistors is connected to an inductor that is in series connection with a load. A first timing module is used for determining a first time difference between a first edge of a first signal at the connecting point and a first edge of a second signal at a control terminal of the first transistor. A second timing module is used for determining a second time difference between a second edge of the first signal and a second edge of the second signal. The first edge and the second edge of the second signal respectively corresponds to a first edge and a second edge of one pulse among the PWM pulses. A delay module is used for delaying the first edge and the second edge of the second signal respectively based on the first time difference and the second time difference.

A signal source for use as a frequency source or time keeping signal source includes a radioactive emission source generating a substantially periodic signal corresponding to a radioactive material's disintegration rate. A radioactive emission detector generates a radioactive emission detection signal and, to stabilize the detected periodic signal, a dead time controlling attenuator blanks or shuts off the radioactive emission detection signal for a selected dead time interval in response to each detected radioactive emission (i.e., a detected signal pulse or signal component) generated by the source. The dead time controlling attenuator output provides a long-term and short-term a stable periodic signal.

The invention discloses a current control method for an active power filter. The current control method comprises the following steps of: comparing a compensating current command signal ic* with a practical compensating current signal ic; generating a PWM (Pulse Width Modulation) signal for controlling the switch-on/off of a main circuit by the hysteresis comparator by taking a difference delta ic of the two signals as an input of a hysteresis comparator; and controlling the switch-on/off of a switch by the PWM signal through a driving circuit, thereby controlling the change in the compensating current ic, wherein the width H of the hysteresis comparator is designed to be capable of automatically adjusting following the magnitude of ic; the hysteresis comparator is replaced by a comparator under timing control of a clock; the delta ic is judged for one time within each clock period; and the PWM signal changes for one time within at least one clock period. The hysteresis current control is the control based on the transient state of current and has the advantages of high dynamic response speed and excellent robustness; the hysteresis current control essentially is a frequency conversion SPWM (Sinusoidal Pulse Width Modulation) modulation mode for implied carrier wave; in a three-phase high-power factor rectifier, the wave frequency of the implied carrier wave under hysteresis control periodically changes following the voltage of a power grid; the change frequency is two times of the power frequency; the hysteresis current control is wide in output spectral range and is better in filtering property; and harmonic energy is uniformly distributed in a wider frequency band scope.

The invention relates to a bidirectional current alternate control circuit for an AC rectification power source. The circuit comprises a PFC (Power Factor Correction) control circuit unit, a split-phase and dead time control circuit, an AC bidirectional current detection and control circuit and the like, wherein the AC bidirectional current detection and control circuit is connected with an AC power source and controls and drives two low-frequency switches, two high-frequency PWM (Pulse Width Modulation) switches and two synchronous rectifier tubes to work according to detected forward and reserve current signals of the AC power source, alternately output working frequency signals and high-frequency PWM signals as well as synchronous rectification signals; the split-phase and dead time control circuit receives and processes signals from the PFC control circuit unit and outputs the signals to a high-frequency PWM driving control circuit unit and a synchronous rectification driving control circuit unit to realize power factor correction; and the high-frequency PWM driving control circuit unit and the synchronous rectification driving control circuit unit ensure that the AC rectification power source has the highest efficiency while having the characteristic of high power factor. The AC bidirectional current detection and control circuit in the invention is simple and reliable and has low cost.

The invention relates to the technical field of step-down DC-DC converters and particularly relates to a step-down DC-DC converter system, which comprises an upper MOS transistor, an upper MOS transistor driving circuit, a lower MOS transistor, a lower MOS transistor driving circuit, a first capacitor, an inductor, a switch, a power supply, a dead time control circuit, a feedback control circuit, a second capacitor, a first capacitor charging control circuit and a pulse integrating circuit, wherein the feedback control circuit is used for generating PWM control signals; when the duty cycle of the PWM control signals is close to or equal to 100%, the first capacitor charging control circuit is used for generating a switching signal to control the conduction time and the conduction frequency of the lower MOS transistor, and thus, the first capacitor is charged and enough voltage is acquired to ensure normal switching control on the upper MOS transistor by the upper MOS transistor driving circuit. The first capacitor charging control circuit is used to enable the first capacitor to have enough charging time when the duty cycle is large or equal to 100%, and control on the upper MOS transistor by the system is thus ensured.

The invention provides a PWM phase-shifting control device for a bi-directional DC-DC converter. The control device comprises a dead time control unit, a PWM phase-shifting control circuit and a bi-directional DC-DC converter which are sequentially connected. According to the PWM phase-shifting control device for the bi-directional DC-DC converter, the PWM phase-shifting control technology is adopted to enable a control strategy to be simple and easy to achieve. For multi-PWM control technology, drive signals of each unit circuit need to be staggered with each other to guarantee smooth conversion between Insulated Gate Bipolar Translators (IGBT), therefore switching frequency can be decreased, and switching loss can be reduced.