46 results about "Dead time control" patented technology

The invention belongs to the field of analog integrated circuit design and integrated systems, and particularly relates to a programmable dead time control circuit for a high-voltage half-bridge driver. Comprising a dead zone time selection circuit (100), a multi-selection mode circuit module and a dead zone logic control circuit (105) which are connected in sequence, and the multi-selection mode circuit module comprises an overlapped input mode circuit (101), an equal ratio input mode circuit (102), a fixed mode input circuit (103) and a dead zone forbidden mode circuit (104) which are connected in parallel. According to the invention, the control of four kinds of dead time can be completed on one driving circuit, so that the circuit can freely control the magnitude of the output dead time without other external structures.

The invention provides a control method for dead time of a power unit. The power unit comprises a power semiconductor device module and a driving module. The control method comprises the steps of obtaining a current value of the power unit; determining the turn-off time of the power semiconductor device module according to the current value and a preset relation table, wherein the preset relation table comprises a corresponding relation between the determined current value and the turn-off time based on the type of the power semiconductor device module; determining the dead time of the power semiconductor device module according to the turn-off time; and determining a driving pulse of the driving module according to the dead time, so that the driving pulse controls the power semiconductor device module to realize the dead time. According to the technical scheme of the invention, the dead time of the power semiconductor device module is automatically updated according to the current value of the power unit, and the probability of current short circuit caused by simultaneous conduction of two power switches in a bridge arm in the power semiconductor device module is reduced. And thus, the stability of equipment or a system comprising the power unit is improved.

The application discloses a dead time control circuit and electronic equipment, and belongs to the technical field of electronics. The dead time control circuit comprises an inductive element, a first field effect tube connected with the inductive element, a second field effect tube connected with the inductive element and the first field effect tube, a detection circuit for detecting a first switching state of the first field effect tube, a second switching state of the second field effect tube and a current flow direction of the inductive element, a logic judgment circuit for outputting an adjustment mode signal of a dead time, a first off time and a second off time according to the first switching state, the second switching state and the current flow direction, an operation circuit for outputting a dead time control signal according to the first off time and the second off time in an adjustment direction indicated by the adjustment mode signal, and a time delay circuit, wherein the dead time control signal is used for adjusting a time delay value of the time delay circuit to adjust the dead time of the first field effect tube and the second field effect tube.

The control of the switches S21 to S28 of the DC / DC converter 120 includes a first mode in which all of the switches S21 to S28 of the DC / DC converter 120 are OFF and a plurality of second modes in which at least one of the switches S21 to S28 of the DC / DC converter 120 is ON, and when switching from the first mode to one of the plurality of second modes, a dead time Td is not provided between the first mode and the one of the plurality of second modes.

The utility model discloses a single-phase brushless motor time-delay starting operation module, which mainly comprises a brushless motor main body and a matched control assembly, and comprises two 41F type Hall sensors which are connected in parallel, a common pull-up resistor and the like. The two Hall sensors are symmetrically installed on the two sides of the geometric center line of a stator magnetic pole, the detection faces face a rotor permanent magnet, high and low levels are output through induction of rotor magnetic pole changes, the H-bridge power tube is controlled, and stator coil power supply state switching is achieved. During working, according to the characteristics of the Hall sensor, the motor is controlled to be started and run according to the principle that the motor is firstly turned off and then turned on, and the dead time control unit generates 0.5-2 ms power tube switching delay. According to the module, the starting success rate of the motor is greatly improved, the starting failure risk is effectively reduced, and the vibration amplitude in the starting process is obviously reduced. In the operation stage, the motor efficiency is remarkably improved, and the rotating speed fluctuation is extremely small when the load changes. Moreover, the circuit design of the module is simplified, so that the hardware cost is greatly reduced.

This invention discloses a gate drive monitoring circuit and device, solving the problems of low adjustment flexibility and duty cycle accuracy in existing technologies, and the inability to achieve only a single function. It includes a gate drive feedback module and a gate drive monitoring module connected to a gate drive module. The gate drive feedback module is connected to the gate drive monitoring module. The gate drive monitoring module includes a dead time control unit and a duty cycle compensation unit. The dead time control unit is connected between the gate drive module and the gate drive feedback module, and the duty cycle compensation unit is connected to the gate drive module. This invention can independently achieve automatic adjustment of the dead time of the high-side MOSFET and the low-side MOSFET, improving adjustment flexibility, increasing duty cycle accuracy, and enabling complex and diverse functions.

The invention relates to an active clamping flyback converter and a control method thereof, and belongs to the field of flyback converters. According to the active clamping flyback converter, voltage stabilization of output voltage is achieved through a double-closed-loop control structure composed of a peak current mode loop and a dead time control loop, and the peak current mode loop is used for controlling the conduction time of a main switching tube. And the dead time control loop is used for detecting whether the active clamping flyback converter realizes a soft switching function or not. A double-loop control loop of a peak current mode and a dead time control mode is adopted, the problem that when the active clamping flyback converter is in light load, zero voltage switching is difficult to achieve in the first switching period, and additional loss is caused is solved, the cost of circuit design is effectively reduced, the occupied size is reduced, and the integration level is improved.

The invention discloses a full gallium nitride integrated driving circuit with dead time control, a chip and equipment, the circuit comprises a power supply management module, a driving module and an output voltage clamping module, the input end of the power supply management module is connected to an external power supply end, and the output end of the driving module is connected to an external power supply end; the output end of the power management module is connected with the first input end of the driving module; the first input end of the driving module is connected to the input end of the output voltage clamping module, the second input end of the driving module is connected to an external control signal end, and the output end of the driving module is connected to the input end of the output voltage clamping module and the output end of the all-gallium nitride integrated driving circuit. The dead zone time is controlled through the driving module, so that the problem that the last driving stage is communicated up and down due to the fact that the dead zone time is too short can be avoided, and the problem that the time delay of the driving circuit is large due to the fact that the dead zone time is too long can also be avoided.

The utility model discloses a gate control detector dead time defense circuit and a QKD system. The circuit comprises a clock signal generation module, an FPGA unit and a multi-channel gating detector, the clock signal generation module provides homologous clock signals for the FPGA unit and the multi-channel gating detector, the FPGA unit provides dead time control signals for the multi-channel gating detector when monitoring detection pulse signals output by the multi-channel gating detector, and the detection pulse signals output by the multi-channel gating detector are output by the FPGA unit. And the multi-channel gating detector enters a dead time state when receiving the dead time control signal. By means of the circuit, all detection channels in the multichannel gating detector can enter / exit the dead time state at the same time by means of response of hardware and input optical signals, and defense against dead time attack behaviors is achieved.

The embodiment of the present application discloses a dead time control circuit and method. In a specific embodiment, the circuit comprises a feedback circuit for generating a first enable signal and a second enable signal when a modulation signal is high; wherein the first enable signal is low for controlling the lower tube to be closed; a floating ground circuit for outputting an upper tube gate control signal when the second enable signal is high; and an upper tube gate potential detection circuit for opening the upper tube when the upper tube gate control signal is low. The embodiment automatically adjusts the discharge delay time without any manual setting intervention, ensures that the upper and lower tubes are not connected, and the discharge delay is as small as possible, thereby preventing large peak current from burning the power tube and chip, ensuring the performance of the chip while improving the reliability of the chip.

A switching converter circuit and a driving circuit with adaptive dead time therein. The switching converter circuit switches the voltage at one end of an inductor therein according to a pulse width modulation signal to convert an input power supply into an output power supply. The switching converter circuit includes an upper bridge MOSFET, a lower bridge MOSFET, and a driving circuit. The driving circuit includes an upper bridge driver, a lower bridge driver, and a dead time control circuit. The dead time control circuit adaptively delays a lower bridge driving signal according to an output current to generate an upper bridge enabling signal, enabling the upper bridge driver to generate an upper bridge driving signal according to the pulse width modulation signal; and / or adaptively delays the upper bridge driving signal to generate a lower bridge enabling signal, enabling the lower bridge driver to generate a lower bridge driving signal according to the pulse width modulation signal; so as to adaptively control a dead time period during which neither the upper bridge MOSFET nor the lower bridge MOSFET conducts.

The invention relates to the technical field of circuits, in particular to a driving circuit, a chip and electronic equipment. According to the driving circuit, a grid voltage detection circuit generates a first detection signal and a second detection signal according to the grid voltage of an upper switching tube and the grid voltage of a lower switching tube; the dead time control circuit determines a first duration and a second duration according to the first detection signal and the second detection signal, and outputs a second signal and a fourth signal; the edge detection circuit outputs a fifth signal and a sixth signal according to the input signal, the second signal and the fourth signal; the control circuit outputs a first control signal according to the third signal and the fifth signal, and outputs a second control signal according to the third signal and the sixth signal. According to the method, the flexibility and the accuracy of adjustment of the dead time are improved.

The invention relates to the technical field of integrated circuits. According to the technical scheme, the programmable dead time control circuit comprises an input module and a dead time module, the dead time module comprises a first module and a second module, and the first module and the second module generate a first output signal and a second output signal respectively and are used for outputting dead time. If the signal input by the first input end and the signal input by the second input end have no time difference, the dead time is the time set by the programmable dead time control circuit; or, the time difference tau exists between the input signals input by the first input end and the input signals input by the second input end, the dead time is set to be delta, and if tau is larger than delta, the dead time is set to be tau; if tau is smaller than delta, the dead time is delta. According to the technical scheme, it can be guaranteed that the dead zone time meets the requirement, and additional loss can be avoided. The method has a wide application range, and the dead time can be programmably adjusted according to the actual use condition.

The utility model provides a dead time adjusting circuit and an active clamping forward power supply chip, which belong to the technical field of switching power supply control, and comprise a current detection module used for detecting the current flowing through a pin OVLP through the resistance of the pin OVLP to the ground and outputting a digital control logic signal and a mirror current source; the digital control output module is connected with the current detection module and is used for receiving the digital control logic signal and converting the digital control logic signal into a control selection signal so as to determine the selected dead time; the variable current output module is connected with the current detection module and is used for outputting variable current according to the mirror current source so as to provide current required by time delay for the dead zone time selection module; and the dead zone time selection module is connected with the digital control output module and is used for selecting a dead zone time path according to the control selection signal, realizing a time delay function by using the current of the variable current output module, outputting a dead zone time control signal and realizing adjustability of dead zone time.

The utility model relates to a dead time control circuit for an inverter and an inverter driving device comprising the same. The circuit includes: an input pin connected to a controller; the first output pin is connected to a lower bridge arm of the inverter, and the second output pin is connected to an upper bridge arm of the inverter; each trigger comprises a data input end, a clock input end and an output end, the output end of the first trigger is connected to the first output pin, the output end of the second trigger is connected to the second output pin, and the data input end of the second trigger is connected to the input pin; a first inverter; and the first time delay circuit and the second time delay circuit are used for controlling the dead time of a high-side driving signal and a low-side driving signal of the inverter. According to the control circuit provided by the utility model, the dead time can be flexibly adjusted according to different application requirements, and meanwhile, the reliability of the circuit is improved in a low-cost manner.

The invention discloses a dead time control circuit for a buck converter and the buck converter, the buck converter comprises a main switch tube and a synchronous switch tube which are connected in series between a power supply voltage and a grounding end, and a common node of the main switch tube and the synchronous switch tube is a switch node. The dead time control circuit is used for controlling the dead time between turn-off of the synchronous switch tube and turn-on of the main switch tube, and comprises a switch node detection circuit used for detecting the voltage of a switch node and generating an effective first detection signal when the voltage of the switch node drops to a first threshold voltage; and the dead time adjusting circuit is used for generating an effective edge of the clock pulse signal at an effective edge of the first detection signal, counting the number of the effective edges of the clock pulse signal in a plurality of continuous switching periods to obtain a count value, and adaptively adjusting the size of the dead time according to the count value, therefore, ideal dead time can be obtained in a steady state.

The invention belongs to the technical field of step-down circuits, and discloses a step-down converter based on turn-on time control, which comprises a logic control module used for generating a first driving signal and a second driving signal based on a received turn-off signal, a start signal and a bias comparison signal, and sending the first driving signal and the second driving signal to a dead time control module and a sleep time detection module; the sleep time detection module is used for generating a mode control signal based on the first driving signal and the second driving signal; the mode control signal is respectively sent to a bias loop comparison module and an error amplification module; the bias loop comparison module is used for generating a bias comparison signal based on a first bias current and sending the bias comparison signal to the logic control module when the mode control signal is at a high level, and generating a bias comparison signal based on a second bias current and sending the bias comparison signal to the logic control module when the mode control signal is at a low level; the second bias current is less than the first bias current. According to the invention, the quiescent current consumption under the ultra-light load can be reduced and the efficiency of the ultra-light load can be improved on the basis of keeping the high response speed under the conventional load.

The invention provides a closed-loop dead time control system and method suitable for an inverter, and the method comprises the steps: detecting the power supply voltage of the inverter, and converting the power supply voltage into a first digital signal; detecting the peak value of the alternating current output by the inverter, and converting the peak value of the alternating current into a second digital signal; inputting the first digital signal and the second digital signal into a preset artificial intelligence model, and calculating to obtain the optimal dead time in the current working state; adjusting the resistance value of a digital resistor according to the optimal dead time so as to change the node voltage in the driving signal generation path; and generating two paths of complementary driving signals based on the adjusted node voltage, and outputting the driving signals to a power tube of an inverter through a driver so as to solve the problem of inaccurate dead time control.

The invention discloses a device and method for dynamically controlling the dead time of a single-photon detector, and the device comprises a drive circuit which is used for amplifying an input signal and then loading the amplified input signal to a cathode of an avalanche photodiode; the avalanche extraction and amplification circuit is used for filtering and amplifying the first avalanche analog signal and outputting a second avalanche analog signal; the multi-amplitude discriminating circuit is used for discriminating the amplitude of the second avalanche analog signal and respectively outputting a first avalanche digital signal to the dead time processing module and amplitude data to the dead time control module; the dead time control module outputs a dead time setting signal to the dead time processing module; the dead time processing module processes the first avalanche digital signal according to the dead time setting signal and then outputs a second avalanche digital signal. According to the amplitude of the avalanche current in the detection process, the setting of the dead time is dynamically adjusted, and the effect of improving the maximum counting rate can be achieved under the condition that the post-pulse probability is low.

The utility model provides a time delay circuit and a rectification circuit and a rectification chip thereof. The time delay circuit comprises a first time delay unit and a second time delay unit, the first time delay unit is used for discharging according to the target control signal, and outputting a first control signal to the second time delay unit after the voltage after discharging reaches the first threshold voltage of the first inverting module; the second time delay unit is used for charging according to the first control signal, and outputting a second control signal after the voltage after charging reaches a second threshold voltage of the second anti-phase module; wherein the sum of the first time when the first time delay unit discharges to reach the first threshold voltage and the second time when the second time delay unit charges to reach the second threshold voltage is a target fixed value, the target fixed value is determined according to the electrical parameters of the device, and then the first time and the second time are subjected to temperature influence variable quantity complementation. Therefore, the time delay duration of the time delay circuit is not affected by the temperature, and the accuracy of dead time control is improved.

The invention discloses a driving circuit with an automatic dead-zone switching function based on a double-N power tube DCDC architecture, which comprises a driving circuit, a delay chain circuit, an SW failure prevention circuit and a sampling logic circuit, and is characterized in that the driving circuit is responsible for transmitting an input signal HSON to a signal HSG for output; the delay chain circuit is responsible for outputting a signal HSDEADB consistent with the signal HSG in delay through delay control to the sampling logic circuit for dead time control, the sampling logic circuit is responsible for judging which one of the signal SW and the signal HSDEADB delays for a longer time, and the SW failure prevention circuit part is responsible for generating a signal SWPRE of which the delay is not limited by a signal VH. According to the invention, the delay chain and the sampling SW are combined, the delay chain or the sampling SW signal is automatically selected at different SW overturning speeds to control the dead time, the dead time is reduced in a full-load range, and no series connection is ensured.

The utility model provides a dead time control circuit and a drive circuit. Wherein the dead time control circuit is provided with a dead time pin. The dead time control circuit comprises a first current source, a first power tube, a voltage balance circuit and a dead time generation circuit. The first current source is coupled to the power supply voltage. The first power tube is coupled in series with the first current source. The input end of the voltage balancing circuit is coupled with the first end of the first power tube, and the output end of the voltage balancing circuit is coupled with the dead time pin. The dead time generation circuit comprises a second power tube and a charging and discharging circuit. The first end of the second power tube is coupled to the power supply voltage, and the second end of the second power tube is coupled to the ground. The first end of the charging and discharging circuit is coupled with the dead time pin, and the second end of the charging and discharging circuit is coupled with the control end of the second power tube. According to the dead time control circuit and the dead time drive circuit provided by the utility model, accurate control of dead time can be realized by accessing corresponding external resistors.

The present invention provides a negative voltage detection circuit and an adaptive dead time control system. Among them, the negative voltage detection circuit includes: a first-side negative voltage detection module, which obtains a first-side sampling voltage based on the gate voltage of the low-side switching transistor in the half-bridge circuit, and generates a first-side negative voltage signal when the first-side sampling voltage is less than the reference voltage; a second-side negative voltage detection module, which obtains a second-side sampling voltage based on the node voltage of the high-side switching transistor and the low-side switching transistor in the half-bridge circuit, and generates a second-side negative voltage signal when the second-side sampling voltage is less than the reference voltage. Through the negative voltage detection circuit and the adaptive dead time control system provided by the present invention, the problems of low accuracy and the like existing in the traditional negative voltage detection circuit are solved.

This invention discloses a dead-time control circuit, PCB board, and controller, including a low-side dead-time setting unit, a high-side dead-time setting unit, a valley detection unit, and a trigger switch. The output terminals of the low-side and high-side dead-time setting units are respectively connected to the input terminal of the valley detection unit, and the output terminal of the valley detection unit is connected to the input terminal of the trigger switch. The low-side dead-time setting unit is used to delay the external low-side input signal; the high-side dead-time setting unit is used to delay the external high-side input signal; the valley detection unit is used to determine the lowest voltage moment of the switching node based on the output signals of the low-side and high-side dead-time setting units, and sends a control signal to the trigger switch based on the lowest voltage moment. By introducing the valley detection mechanism, the dead-time control is transformed from static preset to dynamic sensing and response, which is beneficial for optimizing switching losses.

The circuit comprises a low-side circuit and a high-side circuit. The low-side circuit comprises an input interface part, a low-side circuit monitoring and protecting part and an output interface part II; the low-side circuit monitoring and protecting part is formed by sequentially connecting a temperature sensing circuit with a port multiplexing circuit and a dead time control trimming circuit and then respectively connecting the temperature sensing circuit with a pulse generating circuit and a low-voltage locking and delay circuit; the port multiplexing circuit comprises a dead time control circuit, a latch module, a trimming array module, a trimming addressing module, a burnout control module and a multiplexing port protection circuit. Under the condition that chip ports are not increased, the output end is multiplexed as the programmable trimming port, the packaging cost is saved, and the precision of performance parameters and the product yield of the gate drive chip are improved.

Embodiments described herein provide a wireless power transmitter that dynamically adjusts dead time to reduce power loss. Specifically, a wireless power transmitter includes a transistor circuit for switching a first voltage at a first node and a second voltage at a second node, and an LC circuit coupled between the first node and the second node. The wireless power transmitter also includes a controller coupled to the transistor circuit. The controller is configured to determine whether any one of the first voltage and the second voltage is negative during a dead time of the switching. The controller is configured to increment or decrement the dead time by an adjustment amount depending on whether the negative voltage is detected.

The invention relates to a dead zone circuit capable of adjusting dead zone time. The circuit is formed by connecting an enable signal end EN, a power end VDD, a dead time control port DTC, an external resistor RD, a resistor R3, a resistor R4, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, a capacitor C1, a capacitor C2, a current mirror assembly, an IN signal end, an IN-signal end, a PMOS tube MP1, a PMOS tube MP2, a first phase inverter INV1, a second phase inverter INV2, a third phase inverter INV3, an adjustable dead time output signal end OUT1 and an adjustable dead time output signal end OUT2. According to the dead zone circuit capable of adjusting the dead zone time, the current value of the current mirror assembly can be changed by changing the resistance value of the external resistor RD, then the delay time of the circuit is changed, and the purpose of adjusting the dead zone time is achieved.

The invention discloses a resonant gate drive circuit with reconfigurable dead time control, which belongs to the field of integrated circuits and comprises a reconfigurable dead time control circuit and a resonant drive circuit. The reconfigurable dead time control circuit is formed by cascading a pulse wave generation circuit, a shift register circuit and a logic operation circuit in three stages, and the input end of the reconfigurable dead time control circuit is connected with an external control signal; the resonant driving circuit is composed of six transistors, two inductors and a capacitor, and the output end of the resonant driving circuit is connected with a driven circuit. The pulse wave generating circuit comprises six sets of D triggers, output signals form six independent control signals through the shift register circuit and the logic operation circuit, six transistors of the resonance driving circuit are directly driven to be in the on-off state, resonance is generated through an inductor and a driven circuit load capacitor, and driving energy recovery is achieved. And variable-frequency and variable-duty-ratio output is realized by changing partial pulse duration of the input signal. The circuit provided by the invention can flexibly regulate and control key parameters by only depending on an external control signal.

The application discloses a resonant gate drive circuit with reconfigurable dead-time control, and belongs to the field of integrated circuits, comprising a reconfigurable dead-time control circuit and a resonant drive circuit. The reconfigurable dead-time control circuit is composed of three cascaded stages of a pulse wave generation circuit, a shift register circuit and a logic operation circuit, and an input end is connected with an external control signal; the resonant drive circuit is composed of six transistors, two inductors and one capacitor, and an output end is connected with a driven circuit; the pulse wave generation circuit comprises six groups of D flip-flops, output signals pass through the shift register circuit and reach the logic operation circuit to form six independent control signals, directly drive the switching states of the six transistors of the resonant drive circuit, generate resonance through the inductors and the load capacitor of the driven circuit, realize drive energy recovery, and realize frequency conversion and duty cycle conversion output by changing the pulse length of part of the input signals. The circuit only relies on one external control signal, and can flexibly control key parameters.

The present application is applicable to the technical field of switching power supply, and provides a dead time control circuit, a voltage converter and a switching power supply. The dead time control circuit includes a sampling module, a comparison module, a counting module and a first delay module. The comparison module is electrically connected to the sampling module and the counting module respectively, the counting module is electrically connected to the first delay module, the sampling module is used to be electrically connected to the gate of the lower switch tube, the drain of the lower switch tube and the source of the upper switch tube respectively, and the first delay module is used to be electrically connected to the driving module. The dead time control circuit provided in the embodiment of the present application delays the input signal through the synergistic effect of the sampling module, the comparison module, the counting module and the first delay module, thereby adjusting the first driving signal and realizing the control of the dead time. After multiple cycles of adjustment and control, the dead time is gradually stabilized within a preset range, thereby improving the conversion efficiency of the voltage converter.