254 results about "Circuit architecture" patented technology

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

The invention provides a solid-state transformer. The solid-state transformer comprises a first-stage circuit, a first direct-current bus and a second-stage circuit, the first-stage circuit structure is used for receiving alternating-current electric energy and converting the alternating-current electric energy into first direct-current electric energy. The first DC bus is electrically connected to first DC electric energy. The second-stage circuit is electrically connected to the first-stage circuit through a first DC bus, and is configured to perform isolated step-down DC / DC conversion on the first DC electric energy to generate second DC electric energy. The first stage circuit is configured to operate with a modulation index greater than 1, and the modulation index is defined as a ratio of twice an AC voltage provided by the AC power to a voltage on the first DC bus.

The invention discloses an energy storage system parallel operation circuit and a control method thereof. The energy storage system parallel operation circuit comprises a master battery cluster loop, a slave battery cluster loop and a battery cluster pre-charging equalization loop. And the pre-charging equalization loop is provided with a controllable resistor bypass which is connected in parallel with the contactor and is controlled by the battery management system. A charging and discharging parallel operation strategy is divided, the voltage of a battery cluster is collected, a pre-charging equalization loop is connected, and primary and secondary closing operations are carried out based on the voltage state. The problem of circuit and device damage caused by impact current due to large inter-cluster voltage difference is solved through the master-slave configuration pre-charge equalization loop; meanwhile, the problem of long parallel operation time caused by separation of a pre-charging time sequence and an equalization time sequence is solved by combining a control method; through the dynamic secondary closing operation, the problem that balance is easily damaged by voltage fluctuation in the parallel operation process, and parallel operation fails is solved, parallel operation can be achieved without system restart in a loop under a complex scene in cooperation with a circuit architecture, and the parallel operation reliability, the operation stability and the charging efficiency of the energy storage system are effectively improved.

Filter devices and fabrication methods are disclosed. A filter device includes a piezoelectric plate and a conductor pattern on a front surface of the piezoelectric plate. The conductor pattern includes interdigital transducers (IDTs) of a plurality of transversely-excited film bulk acoustic resonators (XBARs) and a plurality of conductors connecting the plurality of XBARs in a ladder filter circuit architecture. The plurality of conductors includes a first conductor adjacent to a second conductor. An opening is provided through the piezoelectric plate between the first conductor and the second conductor.

The invention discloses a broadband digital phase shifter based on an inductor sharing topology and an equivalent band-pass network, relates to the technical field of microwave integrated circuits, and is suitable for being applied to a Sub-GHz frequency band. The phase shifter comprises a phase shift circuit module and a driving circuit module, and the phase shift circuit module comprises six basic phase shift units including a fine phase shift unit and a coarse phase shift unit which cooperatively realize full-range multi-state phase shift. The fine phase shift unit adopts an inductor sharing topology, so that a phase shift path and a reference path share a circuit architecture, the design is simplified, and the chip layout is optimized; the coarse tuning phase shifting unit adopts an all-pass network as a reference path, a phase shifting path is an equivalent band-pass network formed by cascading a high-pass network and a low-pass network, and the 180-degree phase shifter adopts a double-inductor all-pass network to optimize amplitude-frequency response. And the driving circuit module outputs complementary voltage pairs through the level conversion circuit to drive the switching transistor to realize path switching. The antenna has the advantages of being compact in structure, stable in amplitude, excellent in radio frequency performance and high in adaptability.

The invention relates to the technical field of electric car braking, and discloses an electric car braking system based on multi-redundancy guarantee and self-adaptive control and a control method, and the electric car braking system comprises a redundant circuit module, a distributed driving module, an efficient transmission module and a self-adaptive control center. The reliability is remarkably improved, seamless switching of a main circuit and a standby circuit within 50 ms is achieved through a circuit dual-redundancy architecture, the distributed multi-motor driven torque reconstruction algorithm is matched, the braking efficiency retention rate under a single fault is improved, the circuit fault survival rate reaches 100%, the braking efficiency and safety are optimized, the mechanical loss is reduced to 8% or below through an efficient transmission module, and the reliability is improved. The braking distance of 100 km / h is shortened to 29 m, the energy utilization efficiency is improved, the energy consumption is further reduced through the low-friction transmission design, the dynamic adaptability and the collaboration are enhanced, a self-adaptive control center solves the multi-system instruction conflict through multi-sensor fusion and fuzzy PID adjustment with the sampling frequency of 1 kHz, the braking stability is improved by 40% or above, and the braking stability is improved by 20% or above. And the response time of the key control instruction under the emergency working condition is shortened to 75mS.

A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a dynamic delay adaptive asynchronous time sequence control circuit for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). According to the circuit disclosed by the invention, through an innovative circuit architecture and a control method, remarkable breakthrough is realized in the aspects of conversion precision and speed. According to the circuit, a unique two-stage dynamic delay adjustment mechanism is adopted, intelligent optimization of delay time is achieved based on real-time comparison frequency monitoring, the effective conversion rate under 16-bit precision is improved by 25% or above, and meanwhile it is kept that ENOB is not lower than 15 bits. The innovative current charging capacitance type delay unit is combined with the PVT compensation technology, and the delay time stability is superior to + / -3% within the working temperature range of-40 DEG C to 125 DEG C. Through a dynamic adjustment algorithm of cooperative work of a shift register and a lookup table, the system can automatically adapt to establishment time change of 10 ns to 50 ns, and compared with a fixed delay scheme, invalid waiting time is saved by more than 30%.

Systems and methods are presented herein that include utilizing a specialized circuit architecture for the purpose of locating lost items through voice command recognition. The system can be customized with minimal, low power components to continuously monitor for a locating phrase and produce an audible alert when the locating phrase is detected. The system can be included in a stand-alone portable device that can be attached to electronic and non-electronic portable objects, or the system can be embedded with other circuitry into a portable electronic device. The system can be powered by battery such that it is practical for the device to function as a locating device, continuously monitoring for the locating phrase. Voice recognition can be performed completely within the system, providing the benefit of privacy.

The application provides a pulse density modulation interface implementation method and device of an analog-to-digital converter, electronic equipment and a storage medium. The method comprises the following steps: designing a circuit architecture of an analog-to-digital converter, and setting working variable parameters for components in the circuit architecture; determining a transfer function of an output signal and a transfer function of noise based on the working variable parameters; in the case that an oversampling rate (OSR) is a first set value, a filter order is a second set value, and a quantization bit number is a third set value, calculating an optimal solution of the transfer function of the noise; determining a value corresponding to the working variable parameters of the components according to the optimal solution; and selecting corresponding components for the circuit architecture based on the value, and generating a pulse density modulation interface of an analog-to-digital converter. The application can accurately design a PDM interface, and improves the signal processing performance of the interface.

The invention discloses a small-sized wide instantaneous bandwidth radio frequency receiving front-end SiP module based on an HTCC, and belongs to the technical field of microwaves and radio frequency. The radio frequency receiving front end is realized on the basis of an SiP module of the HTCC, the mirror image frequency is far away from the radio frequency signal frequency spectrum through a high local oscillator dual-frequency conversion mode, and the spurious component generated by frequency mixing is moved to a high-frequency area outside an intermediate-frequency passband, so that wide instantaneous bandwidth and high spurious suppression are realized. According to the invention, miniaturization of the SiP module is realized based on the HTCC technology; a secondary frequency conversion superheterodyne circuit architecture and a high local oscillator design are combined, so that the instantaneous working bandwidth is widened to 4GHz, and meanwhile, high spurious suppression is realized; in addition, the vertical interconnection structure is improved, long-distance low-loss transmission of radio-frequency signals is achieved, and the size is further reduced. The ultra-wideband low-noise amplifier has the advantages of miniaturization, wide instantaneous bandwidth, low noise amplification and high spurious suppression, and a solution is provided for miniaturization and low-cost mass production of an ultra-wideband radio frequency system.

The invention discloses a CGRA multi-task dynamic resource allocation method and a hardware circuit, and belongs to the technical field of dynamic resource allocation. The method specifically comprises the following steps: recording the attribute of each task by using a task attribute table; updating a task attribute table according to a central processing unit message, and generating a task queue and a Boolean value for triggering dynamic resource allocation; the number of processing units is calculated and allocated according to task priorities and the number of data flow diagram nodes; determining the shape of the distributed processing unit according to the number of the distributed processing units; pre-loading the configuration information into a configuration memory of the processing unit so as to match the shape of the allocated processing unit; and dynamic resource allocation is realized by using a finite-state machine. According to the hardware circuit, on the basis of an original CGRA circuit architecture, a dynamic resource distributor, a configuration transmission bus between processing units and configuration receiving circuits in the processing units are added. According to the method, dynamic resource changes caused by task creation and destruction can be flexibly handled.

The invention discloses a frequency duplex synthesis method for realizing a terahertz ultra-wideband frequency multiplier, and relates to the technical field of submillimeter wave / terahertz solid-state frequency multipliers, a'frequency division-frequency multiplication-frequency combination 'duplex circuit architecture is adopted, a frequency division circuit and a frequency combination circuit are both based on a hybrid network type waveguide duplexer design, and the frequency division-frequency multiplication-frequency combination duplex circuit design is adopted. The frequency multiplier circuit is realized by adopting a hybrid integrated frequency doubler, the cost is low, the cavity structure is completely processed by adopting a CNC milling process, and the solid-state characteristic is realized; therefore, under the condition that the frequency doubling / frequency conversion efficiency is not reduced, the frequency doubler capable of covering the full frequency band of 170-260GHz (WR-4 frequency band) can be realized, namely, the double advantages of wide frequency band and high efficiency of the frequency doubler are considered, and the technical problem that the wide frequency band and the high efficiency of a submillimeter wave / terahertz schottky frequency doubler at the present stage cannot be achieved at the same time is solved.

The invention discloses a high-voltage multi-section constant-current LED emergency lighting driving system and a control method. Relates to the technical field of power supply. Comprising LED lamp beads, an alternating current power supply part, an EPS power supply part and a driving IC. The alternating current power supply part and the EPS power supply part supply power to the same LED lamp bead through the same driving IC; according to the scheme, a traditional circuit structure is improved, the alternating current power supply part and the EPS power supply part supply power to the same LED lamp bead through the same driving IC, and the purposes of reducing cost and simplifying a circuit are achieved; wherein the alternating current power supply part accords with high-low voltage power grid input and meets sub-harmonic requirements; meanwhile, the EPS power supply part outputs constant voltage, the output power of the voltage changes along with the combination of the LED lamp beads, linear driving is shared to realize single-section constant current, and the purposes of reducing the cost and simplifying the circuit are realized on the premise of flexibly realizing EPS illumination application of different powers.

The present application provides a multi-channel clock output and input alignment zero-delay circuit, including: a bus, a phase detector, and a phase shifter. Multiple input clocks and output clocks can be transmitted to the phase detector through the bus. In the present application, the clock signals to be aligned are transmitted through the bus. Therefore, the clock signals to be aligned can be located at any position on the chip, and their positions can be relatively far apart. The circuit architecture of the multi-channel clock output and input alignment zero-delay circuit provided by the present application is simple and can be flexibly adjusted. It can achieve multiple different clock alignment signals simultaneously, achieve zero delay of the clock signals, and thus ensure the accuracy of clock signal time synchronization.

This invention discloses a bandgap reference circuit structure, belonging to the field of integrated circuit design technology. The circuit structure includes a bandgap reference core circuit, a chopper-equipped operational amplifier (op-amp), a bandgap reference startup circuit, a temperature-to-absolute-temperature (PTAT) bias current source, and a current source startup circuit. By optimizing the bandgap reference core circuit architecture, combining chopper technology to eliminate the effects of offset voltage and device mismatch, and with the matching startup circuit and low-voltage-adaptive bias current source, the reference voltage is essentially independent of the op-amp input offset voltage, improving circuit symmetry performance and load dynamic response speed. Furthermore, in most common complementary metal-oxide-semiconductor (CMOS) processes, it only requires a power supply voltage of 2V or higher to operate stably, significantly improving the accuracy and stability of the reference voltage.

The invention belongs to the field of integrated circuit design, particularly relates to a fractional frequency divider circuit based on a digital time converter, and aims to solve the performance bottleneck caused by quantization errors in a fractional frequency division phase-locked loop. The circuit comprises three core modules, namely a differential integral modulator, a pulse swallowing multi-modulus frequency divider and a constant-slope digital time converter, wherein the differential integral modulator generates a multi-modulus frequency divider control word and a digital time converter control word according to integer and fractional frequency control words; the pulse swallowing multimode frequency divider receives an output signal of the voltage-controlled oscillator, and outputs a signal D1 and a time sequence control signal after frequency division processing; the constant slope digital-to-time converter time-converts D1 based on a control word and a timing signal, and outputs a delayed clock signal to counteract a quantization error. The femtosecond-level time delay circuit adopts an optimized circuit architecture design, has the characteristics of simple structure and low power consumption, realizes femtosecond-level time delay precision and high linearity, effectively inhibits phase noise and stray, is adaptive to various analog fractional frequency division phase-locked loop structures, remarkably improves the frequency spectrum purity and the system suitability of a clock generator, and has a wide application prospect. And the application requirements of the high-performance fractional frequency division phase-locked loop in the fields of wireless communication, radar and the like are met.

The invention discloses a quantum image sensing method and device based on exposure modulation. The sensing end performs frame-by-frame exposure modulation on the same scene in continuous K frames, and regulates and controls the expected number of incident photons of each frame; the pixels output a 1-bit binary image in each frame and obey Poisson distribution. And the collection end takes K frames as a group to carry out maximum posteriori estimation to obtain reference intensity estimation of each pixel. In order to improve robustness and speed, an RED-PRO iterative algorithm based on FISTA acceleration is adopted in the reconstruction process, after gradient descent of a data consistency item, the data is projected to a pre-training de-noising device manifold, and a pixel adaptive step length is given based on Fisher information. According to the method, the signal-to-noise ratio is remarkably improved and artifacts are inhibited in a scene with low illumination, saturation and limited dynamic range, the 1-bit sensing circuit architecture does not need to be changed, and the existing QIS / SPAD sensor and the lens module can be compatible only through exposure modulation and software reconstruction.

The invention belongs to the technical field of focal plane detector readout circuits, and discloses a predictive search type SARADC circuit design method suitable for a focal plane detector, which comprises a sampling switch, a DAC array, a comparator, a predictive search module and a digital output module. Compared with a traditional SARADC circuit architecture, the SARADC circuit architecture has the advantages that a predictive search algorithm is used, the correlation of amplitude values between adjacent pixels is utilized, the number of ADC comparison times needed when the amplitude information of the current pixel is digitally quantized is greatly reduced, the requirements of an ADC circuit module for designing a high-speed DAC and a high-speed comparator are avoided, and the area and power consumption are reduced. By using the amplitude value conversion result of the adjacent pixels, the comparison frequency of the current pixel comparator is reduced, and the ADC conversion period of a single pixel is reduced, so that the output frame frequency of the whole focal plane detector reading circuit is improved.

This invention discloses a shunt amplifier and electronic device. By introducing at least one resistor adjustment unit, and defining its connection to at least one resistor branch in a first resistor network and / or a second resistor network, it adjusts the equivalent resistance value of the connected branch. This allows the equivalent resistance value of the resistor branch to be adjusted after circuit molding, thereby compensating for proportional resistor mismatch caused by process deviations and directly solving the proportional resistor mismatch problem caused by process deviations. This invention enables the adjustment unit to actively compensate for the corresponding resistor branch without changing the overall circuit architecture, correcting mismatch errors and improving resistor matching accuracy. Since the common-mode rejection ratio (CMRR) of a shunt amplifier is highly dependent on the accuracy of the resistor ratio, improving resistor matching accuracy directly optimizes the CMRR, enhances the amplifier's robustness to process fluctuations, and makes its performance more stable in high-precision, high-complexity applications.

The present invention discloses a two-dimensional AMR sensor switch chip signal architecture and detection method. In the signal circuit architecture, the clock signal output terminal of the fast clock circuit is connected to the clock signal input terminal of the first combinational logic operation module and the clock signal input terminal of the second combinational logic operation module, and the clock signal output terminal of the slow clock circuit is connected to the clock signal input terminal of the first combinational logic operation module; the first combinational logic operation module outputs an X-direction sampling signal, a Y-direction sampling signal, and a detection enable signal, and the second combinational logic operation module outputs a comparator enable signal, a chopping signal, and an XY-direction switching signal. Chopping offset cancellation technology is used to improve detection accuracy, and time-division multiplexing technology is used to share a processing signal chain, achieving low-power two-dimensional signal acquisition and detection in the X and Y directions, and flexible switching of directions according to actual needs.

A new architecture of an on-die process monitor circuit is described, without limitation, in 28 nm. The circuit can extract the threshold voltage, VTH, and random mismatch of a transistor using multiple extraction methods, such as but not limited to, the second derivative method. A sigma-delta modulator analog-to-digital converter may sample the output to enable on-die processing of the results. A VDS voltage control loop may be used to enable VTH extraction in both the linear and saturation regions of the device. The circuit may have a compact area of 5510 μm2.

The invention belongs to the technical field of circuit testing, and discloses a digital circuit wafer-oriented contact testing device, which comprises a probe card; a controllable power supply circuit framework and a contact test loop are integrated on the probe card; the controllable power supply circuit architecture is used for power supply multiplexing of various tested memory wafers, power supply switch adjustment under different working conditions and safety protection; and the contact test loop is used for detecting whether the probe on the probe card is connected with the signal of the tested memory wafer. The controllable power supply circuit architecture supports power supply multiplexing of multiple tested memory wafers, an independent power supply module does not need to be independently configured for each wafer or each test channel, the hardware layout of the test system is simplified, the overall building complexity is reduced, a contact test loop detects the signal connection state of a probe and the wafers in advance, and the test efficiency is improved. And misjudgment caused by poor contact such as installation deviation and inaccurate probe alignment can be directly eliminated, and a qualified wafer does not need to be misjudged as functional failure to be eliminated.

The invention relates to the technical field of power supply circuits, in particular to a modular circuit of a high-repetition-frequency pulse power supply and a control method of the modular circuit. According to the technical scheme, the device comprises a preceding-stage AC-DC charging unit, an energy storage capacitor, two pulse discharging modules connected in parallel and a discharging switch, and the preceding-stage AC-DC charging unit is used for converting alternating current input into direct current. According to the invention, by adopting a standardized and parallelizable modular circuit architecture, flexible and linear adjustment of the maximum output current of the system is realized, the product development and delivery cycle for different current requirements is remarkably shortened, and the customization and maintenance cost is reduced; meanwhile, the total power is dispersed to a plurality of independent modules through the design, the limit requirement for a single power device is lowered, and the reliability and maintainability of the whole system are improved; under the design of synchronous triggering and current sharing, all the modules can cooperatively output high-quality and high-consistency pulse current.

The invention provides a dumbbell counterweight identification circuit and a dumbbell. The dumbbell counterweight identification circuit comprises a dumbbell rod and a plurality of counterweight blocks, a counterweight resistor which is proportional to the weight of each counterweight block is arranged in each counterweight block; a microprocessor, a power supply, a display screen, two partial pressure detection modules and two ADC modules are arranged in the dumbbell rod; after a balancing weight is additionally arranged at one end of the dumbbell rod, a balancing weight resistor in the balancing weight is connected with a detection input end of a partial pressure detection module; the power supply input end of each partial pressure detection module is connected with a power supply, and the detection output end of each partial pressure detection module is connected with the microprocessor through one ADC module; and a comparison table of the weight of the balancing weight and the digital quantity output by the ADC is pre-stored in the microprocessor. Based on the ADC partial pressure detection principle, through combination of a high-precision digital-to-analog conversion technology and intelligent mapping of a comparison table, a simplified circuit structure basically composed of electronic modules is adopted, and intelligent dumbbell counterweight weight recognition with high precision, high reliability and low cost is achieved.

This invention provides a jitter injection circuit, a jitter injection method, a chip, and a testing system for high-speed chip interfaces, belonging to the field of chip testing technology. The jitter injection circuit includes: a signal input terminal for receiving a clock signal input to the chip; multiple series-connected buffer units, each including at least one inverter to buffer the clock signal; multiple switching elements corresponding to the buffer units and connected to the link between the node of the corresponding buffer unit and ground, changing the equivalent load of the buffer unit node by switching it on and off; and a control signal of the control unit synchronized with the clock signal and having a preset period multiple relationship, changing the propagation delay of the buffer units by switching different on and off combinations within different periods, thus forming a clock signal edge time distribution with different jitter amplitudes at the signal output terminal. The circuit architecture of this invention is simple, easy to integrate, and enables programmable multi-level jitter adjustment.

The invention discloses a set of transistor structures and a transistor circuit. The transistor circuit includes a transistor and a voltage source. The transistor includes a semiconductor substrate, a gate structure, a channel region and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first end and a second end. The first conductive region is electrically coupled to the first end of the channel region, and the first conductive region includes a top surface and a bottom surface, where the bottom surface of the first conductive region is lower than the semiconductor surface of the semiconductor substrate. The voltage source is electrically coupled to the transistor through a bottom surface of the first conductive region. Compared with the prior art, the complexity of multi-layer interconnection in a new circuit architecture formed by a complementary metal oxide semiconductor circuit formed by the transistors can be reduced, and the speed performance and the anti-noise capability of the new circuit architecture can be improved, so that more and better heat dissipation paths can be created in the new circuit architecture.