456 results about "Circuit architecture" patented technology

A novel integrated rectifier and boost converter circuit architecture is disclosed. The rectifier architecture includes a plurality of identical half-bridge rectifiers connected to receiving antennas to convert wireless AC power into DC power. The integrated rectifier may be coupled in series with a charging inductor in a boost converter. The inductor may discharge upon operation of two micro-controller-driven switching transistors using predetermined threshold and timing scheme to turn on/off. The rectifier architecture may provide high power densities, improve efficiency at larger load currents, and may be enabled in an integrated circuit with eight RF signal inputs, eight half-bridge rectifiers, and eight DC outputs ganged together as single feed into the boost converter. The rectifier circuit topology may include a comparator driven by the boost controller with a proprietary algorithm which suits control for a maximum power point tracking functionality, and an external micro-controller for additional control of the boost converter.

A design structure comprising an integrated circuit architecture, circuit structure, and/or instructions for fabrication thereof. The circuit structure includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

A micro integrated Global Positioning System (GPS)/Inertial Measurement Unit (IMU) System, which is adapted to apply to output signals proportional to rotation and translational motion of a carrier and GPS measurements of the carrier, respectively from angular rate sensors, acceleration sensors, and GPS chipset, is employed with MEMS angular rate and acceleration sensors and GPS chipset. Compared with a conventional IMU/GPS system, the system of the present invention uses an integrated processing scheme by means of digital closed loop control of the dither driver signals for MEMS angular rate sensors, a feedforward open-loop signal processing scheme of the IMU, digital temperature control and compensation, the earth's magnetic field-based heading damping, robust error estimator, and compact sensor and circuit architecture and dramatically shrinks the size of mechanical and electronic hardware and power consumption, meanwhile, obtains highly accurate motion measurements.

A series of methods of driving multiple LED devices with high efficiency balancing technique is disclosed. The regulation of the LED current is accomplished by switching operation to compensate the difference of the LED operating voltage. Reactive components are also employed to construct non-dissipative balancing networks to drive multiple LED strings with low losses. Additionally, a series of concept is presented to drive the LED devices from PFC voltage directly with low cost circuit architecture.

A noise reduction circuit for reducing the effects of low frequency noise such as wind noise in communications applications is described. In one embodiment, the noise reduction circuit features a high pass filter formed by exploiting the existing off-chip AC coupling capacitances in making the connection to the source of audio signals. The filter may be adaptive to environmental low frequency noise level through programming the shunt resistances. A low-noise wide dynamic range programmable gain amplifier is also described. Adaptive equalization of the audio signal is also described through the utilization of programmable front-end resistors and a back-end audio equalizer.

A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

This invention describes the deficiencies of current art for sensitive impedance sensors, particularly capacitive sensors, and describes several circuits that improve measurement of small value capacitances, especially in the presence of noise. It also shows various circuit architectures optimized for different capacitive sensing tasks. The circuits also describe a novel method to linearize a conventional charge-transfer capacitive sense circuit and a novel method to eliminate the effect of stray capacitance in charge-transfer capacitive sensors.

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Circuit structure and resulting circuitry for multiple-valued logic. The circuit structure allows the design and fabrication of any r-valued logic function of n-places where r is an integer greater than 1 and n is an integer greater than 0. This structure is called SUpplementary Symmetrical LOgic Circuit structure (SUS-LOC). In circuits incorporating SUS-LOC, circuit branches are realized that uniquely deliver circuit response and output. For some circuits, and due to the operating characteristics of the switch elements, additional circuit elements, or stages, must be incorporated to prevent "back biasing." SUS-LOC is fully active. Only active elements perform logic synthesis and those components not directly related to logic synthesis, such as resistors and/or other passive loads, are relegated the task of circuit protection. The fabrication of r-valued, multi-valued, or multiple-valued logic circuits, designed using the definitions of the SUS-LOC structure can be accomplished with known techniques, materials, and equipment.

An imaging and pulse detection array includes: a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in the plurality of pixels and configured to detect a pulse on at least one of the pixels in the plurality of pixels, and each of the pixels in the plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein the imaging circuit and the pulse detection circuit include a shared portion.

A current limiting circuit for a linear regulator includes an output stage transistor and a replica transistor, which have gates coupled to receive an output voltage from a linear amplifier and sources coupled to load circuitry. A drain of the output stage transistor is coupled to a V_DD supply terminal, while a drain of the replica transistor is coupled to the V_DD supply terminal through a first resistor. The output stage transistor and replica transistor are operated in saturation, such that proportional currents flow through these transistors. The voltage drop across the first resistor provides a first voltage, which is applied to a second amplifier. A reference voltage is also applied to the second amplifier. When the first voltage becomes less than the reference voltage, a feedback transistor is enabled to pull down the output voltage of the linear amplifier, thereby limiting the output current supplied to the load circuitry.

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.

The new single mode circuit (SMC) architecture is invented for photonic integrated circuits (PIC). This architecture allows using multimode waveguides or structures to construct a single mode operated PIC. The multimode sections used in such SMC based PIC possess strong lateral confinement so that the PIC can have high circuit density and high optical performance at the same time. A parallel mode converter structure is also invented here. Based on this parallel mode converter, a low loss optical splitter can be constructed for high index contrast waveguide system.

A regular expression pattern matching circuit based on a pipeline architecture is proposed, which is designed for integration to a data processing system, such as a computer platform, a firewall, or a network intrusion detention system (NIDS), for checking whether an input code sequence (such as a network data packet) is matched to specific patterns predefined by regular expressions. The proposed circuit architecture includes an incremental improvement on an old combination of a comparator circuit module and an NDFA (non-deterministic finite-state automata) circuit module, where the incremental improvement comprises a data signal delay circuit module installed to the comparator circuit module and an enable signal delay circuit module installed to the NDFA circuit module to thereby constitute a multi-sage pipeline architecture that allows a faster processing speed than the prior art.

An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions. It acts as an analog device to store directly nonvolatile information in SCL gates. It couples the diode tree logic functions. Finally, it stores and operates large amount of information efficiently. The mixed SCL type FPGA and MLC storages shall emerge as the most compact logic and memory arrays in Si technology. Low power, high performance, and high capacity ICs are designed to mix and replace conventional CMOS-TTL circuits. The idea of multi-value logic composed of binary, ternary, and quaternary hardware and firmware is also introduced.