99 results about "Circuit architecture" patented technology

The invention discloses an energy storage system parallel operation circuit and a control method thereof. The energy storage system parallel operation circuit comprises a master battery cluster loop, a slave battery cluster loop and a battery cluster pre-charging equalization loop. And the pre-charging equalization loop is provided with a controllable resistor bypass which is connected in parallel with the contactor and is controlled by the battery management system. A charging and discharging parallel operation strategy is divided, the voltage of a battery cluster is collected, a pre-charging equalization loop is connected, and primary and secondary closing operations are carried out based on the voltage state. The problem of circuit and device damage caused by impact current due to large inter-cluster voltage difference is solved through the master-slave configuration pre-charge equalization loop; meanwhile, the problem of long parallel operation time caused by separation of a pre-charging time sequence and an equalization time sequence is solved by combining a control method; through the dynamic secondary closing operation, the problem that balance is easily damaged by voltage fluctuation in the parallel operation process, and parallel operation fails is solved, parallel operation can be achieved without system restart in a loop under a complex scene in cooperation with a circuit architecture, and the parallel operation reliability, the operation stability and the charging efficiency of the energy storage system are effectively improved.

The invention discloses a broadband digital phase shifter based on an inductor sharing topology and an equivalent band-pass network, relates to the technical field of microwave integrated circuits, and is suitable for being applied to a Sub-GHz frequency band. The phase shifter comprises a phase shift circuit module and a driving circuit module, and the phase shift circuit module comprises six basic phase shift units including a fine phase shift unit and a coarse phase shift unit which cooperatively realize full-range multi-state phase shift. The fine phase shift unit adopts an inductor sharing topology, so that a phase shift path and a reference path share a circuit architecture, the design is simplified, and the chip layout is optimized; the coarse tuning phase shifting unit adopts an all-pass network as a reference path, a phase shifting path is an equivalent band-pass network formed by cascading a high-pass network and a low-pass network, and the 180-degree phase shifter adopts a double-inductor all-pass network to optimize amplitude-frequency response. And the driving circuit module outputs complementary voltage pairs through the level conversion circuit to drive the switching transistor to realize path switching. The antenna has the advantages of being compact in structure, stable in amplitude, excellent in radio frequency performance and high in adaptability.

The invention discloses a small-sized wide instantaneous bandwidth radio frequency receiving front-end SiP module based on an HTCC, and belongs to the technical field of microwaves and radio frequency. The radio frequency receiving front end is realized on the basis of an SiP module of the HTCC, the mirror image frequency is far away from the radio frequency signal frequency spectrum through a high local oscillator dual-frequency conversion mode, and the spurious component generated by frequency mixing is moved to a high-frequency area outside an intermediate-frequency passband, so that wide instantaneous bandwidth and high spurious suppression are realized. According to the invention, miniaturization of the SiP module is realized based on the HTCC technology; a secondary frequency conversion superheterodyne circuit architecture and a high local oscillator design are combined, so that the instantaneous working bandwidth is widened to 4GHz, and meanwhile, high spurious suppression is realized; in addition, the vertical interconnection structure is improved, long-distance low-loss transmission of radio-frequency signals is achieved, and the size is further reduced. The ultra-wideband low-noise amplifier has the advantages of miniaturization, wide instantaneous bandwidth, low noise amplification and high spurious suppression, and a solution is provided for miniaturization and low-cost mass production of an ultra-wideband radio frequency system.

This invention discloses a bandgap reference circuit structure, belonging to the field of integrated circuit design technology. The circuit structure includes a bandgap reference core circuit, a chopper-equipped operational amplifier (op-amp), a bandgap reference startup circuit, a temperature-to-absolute-temperature (PTAT) bias current source, and a current source startup circuit. By optimizing the bandgap reference core circuit architecture, combining chopper technology to eliminate the effects of offset voltage and device mismatch, and with the matching startup circuit and low-voltage-adaptive bias current source, the reference voltage is essentially independent of the op-amp input offset voltage, improving circuit symmetry performance and load dynamic response speed. Furthermore, in most common complementary metal-oxide-semiconductor (CMOS) processes, it only requires a power supply voltage of 2V or higher to operate stably, significantly improving the accuracy and stability of the reference voltage.

The invention belongs to the field of integrated circuit design, particularly relates to a fractional frequency divider circuit based on a digital time converter, and aims to solve the performance bottleneck caused by quantization errors in a fractional frequency division phase-locked loop. The circuit comprises three core modules, namely a differential integral modulator, a pulse swallowing multi-modulus frequency divider and a constant-slope digital time converter, wherein the differential integral modulator generates a multi-modulus frequency divider control word and a digital time converter control word according to integer and fractional frequency control words; the pulse swallowing multimode frequency divider receives an output signal of the voltage-controlled oscillator, and outputs a signal D1 and a time sequence control signal after frequency division processing; the constant slope digital-to-time converter time-converts D1 based on a control word and a timing signal, and outputs a delayed clock signal to counteract a quantization error. The femtosecond-level time delay circuit adopts an optimized circuit architecture design, has the characteristics of simple structure and low power consumption, realizes femtosecond-level time delay precision and high linearity, effectively inhibits phase noise and stray, is adaptive to various analog fractional frequency division phase-locked loop structures, remarkably improves the frequency spectrum purity and the system suitability of a clock generator, and has a wide application prospect. And the application requirements of the high-performance fractional frequency division phase-locked loop in the fields of wireless communication, radar and the like are met.

The invention discloses a quantum image sensing method and device based on exposure modulation. The sensing end performs frame-by-frame exposure modulation on the same scene in continuous K frames, and regulates and controls the expected number of incident photons of each frame; the pixels output a 1-bit binary image in each frame and obey Poisson distribution. And the collection end takes K frames as a group to carry out maximum posteriori estimation to obtain reference intensity estimation of each pixel. In order to improve robustness and speed, an RED-PRO iterative algorithm based on FISTA acceleration is adopted in the reconstruction process, after gradient descent of a data consistency item, the data is projected to a pre-training de-noising device manifold, and a pixel adaptive step length is given based on Fisher information. According to the method, the signal-to-noise ratio is remarkably improved and artifacts are inhibited in a scene with low illumination, saturation and limited dynamic range, the 1-bit sensing circuit architecture does not need to be changed, and the existing QIS / SPAD sensor and the lens module can be compatible only through exposure modulation and software reconstruction.

This invention discloses a shunt amplifier and electronic device. By introducing at least one resistor adjustment unit, and defining its connection to at least one resistor branch in a first resistor network and / or a second resistor network, it adjusts the equivalent resistance value of the connected branch. This allows the equivalent resistance value of the resistor branch to be adjusted after circuit molding, thereby compensating for proportional resistor mismatch caused by process deviations and directly solving the proportional resistor mismatch problem caused by process deviations. This invention enables the adjustment unit to actively compensate for the corresponding resistor branch without changing the overall circuit architecture, correcting mismatch errors and improving resistor matching accuracy. Since the common-mode rejection ratio (CMRR) of a shunt amplifier is highly dependent on the accuracy of the resistor ratio, improving resistor matching accuracy directly optimizes the CMRR, enhances the amplifier's robustness to process fluctuations, and makes its performance more stable in high-precision, high-complexity applications.

A new architecture of an on-die process monitor circuit is described, without limitation, in 28 nm. The circuit can extract the threshold voltage, VTH, and random mismatch of a transistor using multiple extraction methods, such as but not limited to, the second derivative method. A sigma-delta modulator analog-to-digital converter may sample the output to enable on-die processing of the results. A VDS voltage control loop may be used to enable VTH extraction in both the linear and saturation regions of the device. The circuit may have a compact area of 5510 μm2.

The invention provides a dumbbell counterweight identification circuit and a dumbbell. The dumbbell counterweight identification circuit comprises a dumbbell rod and a plurality of counterweight blocks, a counterweight resistor which is proportional to the weight of each counterweight block is arranged in each counterweight block; a microprocessor, a power supply, a display screen, two partial pressure detection modules and two ADC modules are arranged in the dumbbell rod; after a balancing weight is additionally arranged at one end of the dumbbell rod, a balancing weight resistor in the balancing weight is connected with a detection input end of a partial pressure detection module; the power supply input end of each partial pressure detection module is connected with a power supply, and the detection output end of each partial pressure detection module is connected with the microprocessor through one ADC module; and a comparison table of the weight of the balancing weight and the digital quantity output by the ADC is pre-stored in the microprocessor. Based on the ADC partial pressure detection principle, through combination of a high-precision digital-to-analog conversion technology and intelligent mapping of a comparison table, a simplified circuit structure basically composed of electronic modules is adopted, and intelligent dumbbell counterweight weight recognition with high precision, high reliability and low cost is achieved.

This invention provides a jitter injection circuit, a jitter injection method, a chip, and a testing system for high-speed chip interfaces, belonging to the field of chip testing technology. The jitter injection circuit includes: a signal input terminal for receiving a clock signal input to the chip; multiple series-connected buffer units, each including at least one inverter to buffer the clock signal; multiple switching elements corresponding to the buffer units and connected to the link between the node of the corresponding buffer unit and ground, changing the equivalent load of the buffer unit node by switching it on and off; and a control signal of the control unit synchronized with the clock signal and having a preset period multiple relationship, changing the propagation delay of the buffer units by switching different on and off combinations within different periods, thus forming a clock signal edge time distribution with different jitter amplitudes at the signal output terminal. The circuit architecture of this invention is simple, easy to integrate, and enables programmable multi-level jitter adjustment.

The invention discloses a set of transistor structures and a transistor circuit. The transistor circuit includes a transistor and a voltage source. The transistor includes a semiconductor substrate, a gate structure, a channel region and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first end and a second end. The first conductive region is electrically coupled to the first end of the channel region, and the first conductive region includes a top surface and a bottom surface, where the bottom surface of the first conductive region is lower than the semiconductor surface of the semiconductor substrate. The voltage source is electrically coupled to the transistor through a bottom surface of the first conductive region. Compared with the prior art, the complexity of multi-layer interconnection in a new circuit architecture formed by a complementary metal oxide semiconductor circuit formed by the transistors can be reduced, and the speed performance and the anti-noise capability of the new circuit architecture can be improved, so that more and better heat dissipation paths can be created in the new circuit architecture.

The utility model relates to communication technical field, concretely is a kind of gigabit ethernet port protection circuit.The protection circuit includes: difference signal positive electrode circuit and difference signal negative electrode circuit, for forming signal transmission path;Difference impedance matching circuit is used to suppress signal reflection;Power filter network circuit is used to filter high-frequency noise and suppress common-mode interference.The circuit architecture design of the utility model systematically solves the core technical problem in the high-speed transmission of gigabit ethernet port.In the signal transmission level, two-stage resistance-capacitance isolation and dynamic impedance matching mechanism construct the parameter self-adaptive signal transmission path, through the impedance buffer of series resistance, the direct current isolation of coupling capacitor and the dynamic adjustment of difference pair network, effectively suppress signal reflection and direct current bias interference, ensure the integrity of 10Gbps high-frequency signal in long-distance transmission.

The embodiment of the utility model provides a chip test circuit and a chip test board card, a first alarm link is designed for a target detection link, voltage value detection is performed through the first alarm link, and a preset level is transmitted to a test control chip through a matrix alarm circuit under the condition that the voltage of the target detection link is abnormal. A test control chip is triggered to determine a target detection link with abnormal voltage through a matrix alarm circuit, a corresponding power supply module is controlled to be powered off, alarm information is generated, the test control chip can independently control an abnormal power supply channel to be powered off, and other power supply channels working normally are not affected. The chip testing safety and the chip testing efficiency can be improved, an MCU is replaced by a framework of combining the testing control chip with the matrix warning circuit to perform anomaly detection and warning, a communication link and a peripheral circuit among a plurality of MCUs do not need to be designed, the number of needed chips is small, the circuit structure is simple, and the cost is low. And the complexity and the design and manufacturing cost of the chip test circuit are reduced.

This utility model relates to the field of general circuit technology, specifically to a stable and anti-interference fast power-on / off RC reset circuit; it includes an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistors R1 and R2, capacitor C, diode D1, and power supply equivalent impedance RL. The MOSFET interlock circuit includes transistors M1, M2, M3, M4, M5, and I1, where I1 is a logic gate OR gate. The RC reset circuit of this design adds a MOSFET interlock structure to the traditional circuit architecture to generate high and low levels, which are then used by logic gate circuits to generate high and low voltage signals, suppressing reset signal jitter that may be caused by power supply noise or environmental interference. At the same time, the RC reset circuit uses a MOS resistor instead of a traditional resistor and utilizes its own substrate diode as a capacitor discharge diode, which can accelerate the discharge of capacitor C. Furthermore, a resistor discharge branch connected in parallel with capacitor C is added to achieve fast reset of the RC circuit when the power supply is rapidly powered on or off.

The invention discloses a storage and calculation integrated reading module and a storage and calculation integrated array circuit. The storage and calculation integrated reading module is used for being connected with the weight module, the weight module comprises a first MTJ and a second MTJ, and the storage and calculation integrated reading module comprises a voltage division unit which is used for forming a first voltage division circuit with one of the first MTJ and the second MTJ and then forming a second voltage division circuit with the other one of the first MTJ and the second MTJ; the reading module is used for reading the first voltage of the first voltage division circuit and the second voltage of the second voltage division circuit; and the comparison module is used for comparing the first voltage with the second voltage and generating an output signal corresponding to a comparison result. According to the embodiment of the invention, the binary multiplication operation of the weight W and the input IN can be realized, the architecture of the unit circuit is simple, the number of devices is low, the cost is low, the operation steps of binary multiplication can be reduced, and the operation accuracy and efficiency are improved.

This disclosure relates to a power module, a power converter, a method, and a computer program for supplying a target amount of power across different power ranges using a hybrid circuit architecture.

The invention relates to the technical field of electromagnetic positioning, in particular to a five-degree-of-freedom sensor for electromagnetic positioning and an induction signal processing system, and the induction signal processing system adopts a three-stage circuit architecture: the first stage is an instrument amplifier pre-amplification circuit with input filtering and common-mode suppression functions; the low-noise amplifier is used for performing low-noise amplification on a microvolt-level original signal; the second stage is a Sallen-Key type active high-pass filter circuit and is used for suppressing power frequency and low frequency interference; and the third stage is a Sallen-Key type active low-pass filter circuit which is used for filtering high-frequency noise. Wherein the output of the pre-amplification circuit is connected to the third-stage low-pass filter circuit and then is cascaded with the second-stage high-pass filter circuit to jointly form a band-pass filter path, and finally, a stable analog signal with a high signal-to-noise ratio is output. The problems that a micro sensor is weak in signal, prone to interference and high in system complexity are effectively solved, and the performance and reliability of the electromagnetic positioning system in high-precision application scenes such as medical navigation and virtual reality are remarkably improved.

This invention relates to intravascular techniques where measuring the retraction distance is important, such as intravascular ultrasound (IVUS) imaging. The invention describes hardware, circuit architecture, and methods for wirelessly transmitting data related to the retraction distance of a catheter introduced into a blood vessel.

This invention provides a data writing circuit and a memory chip. Based on the existing data writing circuit architecture, the single-ended transmission circuit of the data input node I / O coupled to a memory such as DRAM or PSRAM is replaced with a double-ended transmission circuit (which has a single data input terminal and two data output terminals). Thus, when the double-ended transmission circuit is turned on, the potential of the first bit node b1 or the second bit node b1 can be quickly pulled down by rapidly pulling down the potential of the LIOT node or LIOB node of the memory. This allows the first bit node b1 and the second bit node b1 to quickly separate a larger voltage difference, thereby increasing the speed of writing "0" and "1" to the memory cell and greatly reducing the speed difference when writing "0" and "1" to the memory (making the speed of writing "0" and "1" approximately the same). This improves the performance of the memory and enables it to meet the requirements of higher performance products.

The present specification provides a circuit architecture, an oscillator, a chip, and an electronic device. The circuit architecture comprises: an oscillation circuit having at least one oscillation loop, the oscillation loop comprising at least one frequency modulation node; the at least one frequency modulation unit comprises a control subunit and an energy storage subunit; the control subunit is provided with a first end, a second end and a control end; the first end is electrically connected with the frequency modulation node, and the second end is electrically connected with the first end of the energy storage subunit; the control end is configured to receive a control voltage; the second end of the energy storage subunit is electrically connected with a reference potential end; and the control subunit is configured to respond to the control voltage and adjust the energy storage subunit so as to enable the equivalent capacitance at the frequency modulation node to change along with the control voltage. The circuit architecture has the advantages that the structure is simple, and the output frequency linearity can be kept in a wide voltage range.

Various implementations described herein are related to a device having a multi-transistor structure for use in circuit architecture. The multi-transistor structure may have a multi-transistor stack of at least one of N-type transistors or P-type transistors that are arranged in a multi-device stack configuration. Also, a physical layout of the multi-device stack configuration may provide a common-centroid configuration for process mismatch cancellation in at least one of the X-Y-Z axes.

To provide a circuit architecture related to a radio unit, a base station, and satellite communication in a radio communication system which is especially suitable for the base station of a large multi-input multi-output antenna, can reduce transmission power, and has green technical effect of energy saving and carbon reduction.SOLUTION: A circuit structure 400 for radio units is composed of a plurality of printed circuit boards 410 to 430, where allocated to the plurality of printed circuit boards are: a radio unit including an antenna module and an RF front-end module; an active antenna required for a base station and a satellite communication system; a digital circuit including a fronthaul interface module, a communication digital signal processing module, a beam forming module, and a baseband digital circuit module; and a power supply module. By appropriately arranging the respective modules on the plurality of printed circuit boards, it is possible to achieve necessary functions in cooperation and optimize the overall performance.SELECTED DRAWING: Figure 4

The invention relates to the technical field of integrated circuit design, in particular to a processing circuit architecture supporting multi-calculation precision dynamic switching, which comprises a control port module, a partial product generation module, a symbol compression module, an addition compression tree module and a final adder module. And single-cycle dynamic switching of various precisions is realized. The partial product generation module adopts a Booth coding algorithm to split an operation vector, and cooperates with boundary symbol selection logic to solve the problem of symbol expansion and auxiliary bit overlapping; the symbol compression module compresses the redundant extension bits through a preset coding mode; the addition compression tree module is formed by cascading multiple stages of compressors and inserting carry blocking logic; the final adder module is composed of a plurality of carry lookahead adders, and the output bit width is dynamically controlled through blocking logic. The architecture optimizes the parallel operation efficiency and the resource utilization rate, adapts to the deep learning training and reasoning full scene, and has the advantages of real-time performance and low power consumption.

The invention discloses an intelligent bionic giant robot cruise performance track control system and method, and belongs to the crossing field of robot control and performance art technologies. Comprising a cloud planning layer for global planning, a ground central control layer responsible for field command and wireless Mesh networking, a robot vehicle-mounted layer serving as a robot local brain and an actuator driving layer for driving execution. The core is that a robot vehicle-mounted layer adopts a highly-modularized circuit design and integrates a track analysis and decision-making unit, a local state sensing fusion device, a multi-machine cooperative communication gateway and an independent safety monitoring module. Through a method of combining centralized planning and distributed intelligent control, individual autonomous obstacle avoidance and real-time trajectory optimization of multiple robots under global collaborative performance are realized, and by means of hardware modular design, the reliability, maintainability and expansibility of the system are remarkably improved, and the system is suitable for large-scale popularization and application. The problems of poor flexibility, weak collaboration and difficult maintenance in the prior art are solved.

The invention belongs to the field of high-speed signal transceiving, and particularly discloses a high-bandwidth low-loss double-pole double-throw repeater for switching data paths, which is composed of two DPDTs, the DPDTs are distributed amplification circuit architectures, and due to the fact that the distributed amplification circuit architectures have good broadband characteristics, due to the use of an input matching network and an output matching network, the bandwidth of the DPDTs is greatly improved. The distributed amplification circuit has the characteristics of low input echo reflection and output echo reflection in a wide frequency range, so that the DPDT provided by the invention has the advantages of high bandwidth and low reflection. Meanwhile, different from a traditional transmission gate type switching circuit, the amplification unit used for controlling on or off of a data path has a certain gain, lossless transmission of signals can be achieved, and the DPDT is made to be low in loss and even free of loss.

A phase-shifting circuit and a radio frequency microwave system are provided. The phase-shifting circuit includes a first node circuit, a second node circuit, and a first signal channel and a second signal channel coupled between the first node circuit and the second node circuit. The first node circuit is configured to split an input signal to simultaneously output a first differential signal to the first signal channel, and output a second differential signal to the second signal channel. The first signal channel and the second signal channel are implemented based on an architecture of a differential circuit, and configured to perform at least one of a signal attenuation and a quadrant transformation on the first differential signal and the second differential signal for phase-shifting. The second node circuit is configured to synthesize a first phase shift signal output by the first signal channel and a second phase shift signal output by the second signal channel to obtain an output signal, and a phase difference between the output signal and the input signal is within a range of 0 deg-360 deg.

The invention discloses an in-memory multiply-accumulate and similarity calculation circuit based on dynamic logic, which is used for supporting the design of an in-memory calculation macro cell and an accelerator in a digital domain, and provides an in-memory calculation circuit architecture which supports a Booth coding rule for inputting similarity calculation. On the basis, a local input sharing calculation unit and a decoding and addition tree unit are designed, and element-by-element multiply-accumulate calculation and similarity calculation of fixed data are supported. Compared with a traditional multiply-accumulate circuit, the multiply-accumulate circuit disclosed by the invention adopts a calculation mode of firstly carrying out Booth coding on input data, then generating a multiply-accumulate partial product and finally carrying out decoding accumulation, and meanwhile, a partial product generation and similarity calculation circuit is designed based on dynamic logic, so that the partial product is multiplexed, and multiply-accumulate calculation is realized element by element with smaller calculation overhead; the face effect and the energy efficiency are both considered, and the comprehensive performance of the computing architecture and the circuit is improved.

The invention provides a magnetic core random access memory read reference circuit architecture design method and system, and relates to the technical field of circuit architectures.The method comprises the steps that a high-resistance reference unit column and a low-resistance reference unit column are arranged in each storage array, and each high-resistance reference unit column and the corresponding low-resistance reference unit column respectively comprise a transistor and polycrystalline silicon resistor series structure; configuring a reference bit line, adjusting the line width to enable the square resistance to be equal to that of a common bit line, and reading the number of transistors in a path to be the same as that of target units; obtaining a target reading current and a high-low resistance reference current in the reading operation; calculating a high-low resistance reference current intermediate value as a dynamic reference current, wherein the current is adaptively adjusted along with the change of parasitic resistance on a path; and comparing the target read current with the dynamic reference current through a sensitive amplifier to judge the data of the storage unit. According to the invention, the reading reliability and the fault-tolerant capability of the magnetic core random access memory system are improved.

The utility model provides a miniaturized rotary transformer analog circuit based on isolated power supplies and isolated operational amplifiers, which comprises a rotary transformer analog calculation circuit, two isolated operational amplifiers and a power amplification circuit connected with the isolated operational amplifiers, and each isolated operational amplifier and the power amplification circuit connected with the isolated operational amplifier adopt an independent isolated power supply to realize isolated power supply; a sine excitation signal EXC + / EXC-is input into a rotary transformer analog calculation circuit to generate two signals DAC1 and DAC2 containing motor rotor position information, the DAC1 and DAC2 respectively pass through respective isolation operational amplifiers and then output isolation signals, the isolation signals pass through respective power amplification circuits and then respectively output sine and cosine signals SIN + / SIN-and COS + / COS-containing motor rotor position information; through application of a novel isolation device and circuit architecture optimization, miniaturization, high integration level, high precision and high bandwidth rotary transformer simulation are realized.