31 results about "Circuit architecture" patented technology

This invention discloses a bandgap reference circuit structure, belonging to the field of integrated circuit design technology. The circuit structure includes a bandgap reference core circuit, a chopper-equipped operational amplifier (op-amp), a bandgap reference startup circuit, a temperature-to-absolute-temperature (PTAT) bias current source, and a current source startup circuit. By optimizing the bandgap reference core circuit architecture, combining chopper technology to eliminate the effects of offset voltage and device mismatch, and with the matching startup circuit and low-voltage-adaptive bias current source, the reference voltage is essentially independent of the op-amp input offset voltage, improving circuit symmetry performance and load dynamic response speed. Furthermore, in most common complementary metal-oxide-semiconductor (CMOS) processes, it only requires a power supply voltage of 2V or higher to operate stably, significantly improving the accuracy and stability of the reference voltage.

This invention discloses a shunt amplifier and electronic device. By introducing at least one resistor adjustment unit, and defining its connection to at least one resistor branch in a first resistor network and / or a second resistor network, it adjusts the equivalent resistance value of the connected branch. This allows the equivalent resistance value of the resistor branch to be adjusted after circuit molding, thereby compensating for proportional resistor mismatch caused by process deviations and directly solving the proportional resistor mismatch problem caused by process deviations. This invention enables the adjustment unit to actively compensate for the corresponding resistor branch without changing the overall circuit architecture, correcting mismatch errors and improving resistor matching accuracy. Since the common-mode rejection ratio (CMRR) of a shunt amplifier is highly dependent on the accuracy of the resistor ratio, improving resistor matching accuracy directly optimizes the CMRR, enhances the amplifier's robustness to process fluctuations, and makes its performance more stable in high-precision, high-complexity applications.

The invention discloses a set of transistor structures and a transistor circuit. The transistor circuit includes a transistor and a voltage source. The transistor includes a semiconductor substrate, a gate structure, a channel region and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first end and a second end. The first conductive region is electrically coupled to the first end of the channel region, and the first conductive region includes a top surface and a bottom surface, where the bottom surface of the first conductive region is lower than the semiconductor surface of the semiconductor substrate. The voltage source is electrically coupled to the transistor through a bottom surface of the first conductive region. Compared with the prior art, the complexity of multi-layer interconnection in a new circuit architecture formed by a complementary metal oxide semiconductor circuit formed by the transistors can be reduced, and the speed performance and the anti-noise capability of the new circuit architecture can be improved, so that more and better heat dissipation paths can be created in the new circuit architecture.

The utility model relates to communication technical field, concretely is a kind of gigabit ethernet port protection circuit.The protection circuit includes: difference signal positive electrode circuit and difference signal negative electrode circuit, for forming signal transmission path;Difference impedance matching circuit is used to suppress signal reflection;Power filter network circuit is used to filter high-frequency noise and suppress common-mode interference.The circuit architecture design of the utility model systematically solves the core technical problem in the high-speed transmission of gigabit ethernet port.In the signal transmission level, two-stage resistance-capacitance isolation and dynamic impedance matching mechanism construct the parameter self-adaptive signal transmission path, through the impedance buffer of series resistance, the direct current isolation of coupling capacitor and the dynamic adjustment of difference pair network, effectively suppress signal reflection and direct current bias interference, ensure the integrity of 10Gbps high-frequency signal in long-distance transmission.

This utility model relates to the field of general circuit technology, specifically to a stable and anti-interference fast power-on / off RC reset circuit; it includes an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistors R1 and R2, capacitor C, diode D1, and power supply equivalent impedance RL. The MOSFET interlock circuit includes transistors M1, M2, M3, M4, M5, and I1, where I1 is a logic gate OR gate. The RC reset circuit of this design adds a MOSFET interlock structure to the traditional circuit architecture to generate high and low levels, which are then used by logic gate circuits to generate high and low voltage signals, suppressing reset signal jitter that may be caused by power supply noise or environmental interference. At the same time, the RC reset circuit uses a MOS resistor instead of a traditional resistor and utilizes its own substrate diode as a capacitor discharge diode, which can accelerate the discharge of capacitor C. Furthermore, a resistor discharge branch connected in parallel with capacitor C is added to achieve fast reset of the RC circuit when the power supply is rapidly powered on or off.

This disclosure relates to a power module, a power converter, a method, and a computer program for supplying a target amount of power across different power ranges using a hybrid circuit architecture.

This invention relates to intravascular techniques where measuring the retraction distance is important, such as intravascular ultrasound (IVUS) imaging. The invention describes hardware, circuit architecture, and methods for wirelessly transmitting data related to the retraction distance of a catheter introduced into a blood vessel.

The present disclosure relates to a power module, a power converter, a method and a computer program for supplying a target power amount across different power ranges using a hybrid circuit architecture.

Providing dataflow based guidance for buffer allocation in a multicore circuit architecture includes converting, using computer hardware, an application specified in a high-level programming language into an intermediate representation. Buffers of dataflows of the intermediate representation are detected. Determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation. Buffer constraints are generated. The buffer constraints specify whether the buffers are independent and dictate a mapping of the buffers in the multicore circuit architecture.

Disclosed are a parallel circuit architecture for multi-phase power stage chips, a circuit board, and an electronic device, which relate to the technical field of electronic circuits. When it is detected that the current at a target current detection terminal is greater than the currents at the remaining current detection terminals, a duty cycle of a target pulse signal is reduced to equalize the current across each power stage chip. When it is detected that the current at the target current detection terminal is less than the currents at the remaining current detection terminals, it indicates that the duty cycle of the target pulse signal is excessively low, and therefore the duty cycle of the target pulse signal is increased to equalize the current across each power stage chip.

This invention belongs to the field of power electronics and semiconductor device technology. It proposes a multi-level, high-current pulse power supply circuit and a method for comparing the on-resistance of transistors. The circuit includes a DC power supply module, a level gating module, a pulse gating module, and a power module. Through close coordination of circuit architecture and timing control, this invention forms a novel method for measuring and comparing the on-resistance of transistors driven by a multi-level, high-current power supply circuit. It achieves rapid switching between different gate drive voltages and gate drive currents with nanosecond-level delays, efficiently driving both voltage-driven and current-driven transistors with a wider output voltage range and larger output current. Combined with the control of drain voltage stress value, drain voltage stress duration, and temperature, it enables high-precision comparison of transistor on-resistance under various operating conditions, resulting in more accurate and reliable test data.

This invention discloses an undervoltage protection circuit, a PCB board, and a controller, including a reference voltage unit, a voltage regulator unit, a switching unit, and a driving switching unit. The reference voltage unit is connected to the reference voltage input terminal of the voltage regulator unit. The anode terminal of the voltage regulator unit is grounded, and the cathode terminal of the voltage regulator unit is connected to the external power supply input terminal and the input terminal of the switching unit. The output terminal of the switching unit is connected to the driving switching unit. The reference voltage unit provides a reference voltage to the voltage regulator unit. The voltage regulator unit provides a switching signal to the switching unit based on the reference voltage and the input voltage. The switching unit controls the operating state of the driving switching unit based on the switching signal. The comparison control logic is achieved using the voltage regulator unit, which simplifies the overall circuit architecture and reduces component costs and design complexity. When an undervoltage condition is detected, the power supply to the subsequent stage is automatically cut off, reducing the reliance on manual intervention.

An antenna having a tuning circuit architecture and methods for using the same are described. In some embodiments, an antenna includes a metasurface having a plurality of radio-frequency (RF) radiating antenna elements. Each of the plurality of antenna elements includes a tuning circuit including a voltage-variable capacitor, a first fixed capacitor coupled in series with the voltage-variable capacitor, and a second fixed capacitor coupled in parallel with the voltage-variable capacitor.

An antenna having a tuning circuit architecture and methods for using the same are described. In some embodiments, an antenna includes a metasurface having a plurality of radio-frequency (RF) radiating antenna elements. Each of the plurality of antenna elements includes a tuning circuit including a voltage-variable capacitor, a first fixed capacitor coupled in series with the voltage-variable capacitor, and a second fixed capacitor coupled in parallel with the voltage-variable capacitor.

The capacitively-coupled static random access memory (SRAM-C) compute-in-memory (CIM) circuit includes at least one static random access memory (SRAM) configured to store a bit value, at least one capacitively-coupled (CC) circuit coupled to at least one SRAM, and an energy recovery logic (ERL) driver configured to recover signal energy by utilizing a ramped sinusoidal hot clock. The CC circuit includes a first and second capacitors, a first pair, a second pair, a third pair, a fourth pair of transistors. Each pair of transistors include a first and second transistors coupled to one another. the first capacitor is coupled to the first and second pairs of transistors and the second capacitor is coupled to the third and fourth pairs of transistors. The SRAM-C CIM circuit enhances efficiency and effectiveness of multiply-and-accumulate (MAC) operations of the SRAM-C CIM circuit.

The application provides a readout circuit architecture and a sense amplification circuit, comprising: a readout amplification unit, comprising: a first P-type transistor and a second P-type transistor; a first offset compensation unit, comprising: a first offset compensation tube and a second offset compensation tube; wherein the first P-type transistor is arranged in a first region, and the second P-type transistor is arranged in a second region; when the first region and the second region are arranged at intervals along a first direction, the first offset compensation tube and the second offset compensation tube are both arranged in a third region, and the third region is located between the first region and the second region; when the first region and the second region are arranged adjacent to each other along the first direction, the first offset compensation tube and the second offset compensation tube are arranged in a fourth region and a fifth region respectively. The application can improve the accuracy of the reading result and improve the performance.

This invention discloses a rock-based composite manhole cover for environmental information monitoring based on the Internet of Things (IoT), relating to the field of smart city infrastructure technology. The manhole cover includes: a cover body and a sensing and monitoring module; the cover body is made of basalt fiber-reinforced resin-based composite material with an internal hollow sandwich structure; the sensing and monitoring module is embedded in the lower surface of the cover body and includes a sensor group, a hardware wake-up circuit, a main control unit, and a wireless communication unit; the hollow sandwich structure is filled with phase change energy storage material; the hardware wake-up circuit is connected to the sensor group and the main control unit and is continuously powered at the microampere level, used to compare the output signal of the sensor group with a preset tilt angle threshold, and only generates a trigger signal and sends it to the main control unit when the output signal exceeds the preset tilt angle threshold. This invention achieves the goals of material durability, cost control, low sensor power consumption, and data accuracy by optimizing the material structure and circuit architecture.

This application provides a multi-channel, multi-phase buck DC circuit, circuit architecture, electronic equipment, and a control method for the multi-channel, multi-phase buck DC circuit. Each power supply is equipped with a corresponding adjustment unit. The adjustment unit has configuration pins, and the adjustment units are electrically connected to each other. Each adjustment unit is configured to determine its identity based on the voltage applied to the configuration pin, identifying one adjustment unit as the active unit and the others as passive units. The active unit is configured to generate and output a first control signal. The passive units are configured to determine the phase control start point of their corresponding power supply, thereby enabling at least two power supplies to achieve phase interleaving under a unified time base. This multi-channel, multi-phase buck DC circuit has the effects of reducing the rate of change of current and voltage, reducing electromagnetic interference radiation, reducing the amplitude of power supply ripple at the input terminal, and enhancing the robustness and electromagnetic compatibility of the system.

The USB bridge includes a first USB port coupled to a first USB host, a second USB port coupled to a second USB host, a microcontroller coupled to the first and second USB ports, the microcontroller communicating with the first and second USB hosts through the first and second USB ports to enable the first and second USB hosts to emulate individual USB ports of the first host and the second host as a plurality of virtual communication ports, and a host-to-host function circuit coupled to the microcontroller, the host-to-host function circuit configured to implement a host-to-host transfer function using the USB ports emulated as the virtual communication ports.

This application discloses a high-resolution PWM signal generator based on an FPGA, comprising a carrier comparison module, a selection module, and a delay module. The carrier comparison module generates a first PWM signal based on a first value, and generates a first timing control signal and a second timing control signal based on a second value. The selection module selectively outputs the first PWM signal with no delay or with a delay of half a system clock cycle, based on the first timing control signal. The delay module sets a delay period less than half a cycle according to the second timing control signal to provide a high-resolution PWM signal based on the output signal and the delay period. Thus, only a single delay module is needed, simplifying the circuit architecture and eliminating the need to increase the system clock speed, achieving a low-cost PWM signal generator.

A reconfigurable circuit architecture configured for dynamically correcting and extending an existing instruction set includes an embedded Field-Programmable Gate Array (eFPGA) and a microprocessor. The embedded FPGA supports dynamic partial reconfiguration technology to configure a predefined bitstream or apply the predefined bitstream for correcting a current instruction, and execute an execution logic of the corrected current instruction to produce an actual function after the correction. This correction may include correcting errors in the execution logic of the current instruction or expanding functionalities beyond those originally associated with the existing instruction set. When the actual function is determined to be inconsistent with a predefined function, the microprocessor searches a bitstream set stored in a memory unit for a bitstream consistent with the predefined function to serve as the predefined bitstream.

In one embodiment, an integrated circuit package includes an assembly embedded in the package substrate that includes a bridge circuitry die to interconnect multiple integrated circuit dies of the package and an interposer coupled to the bridge circuitry die. The interposer includes high aspect ratio vias (e.g., greater than 20:1), and may be formed of glass. The assembly may be embedded within a core layer of the package substrate.

This disclosure relates to the field of USB 2.0 protocol implementation, specifically to a state management circuit architecture for a USB device, comprising: a state detection unit, configured to receive and determine a state signal based on a differential signal pair, and determine the target state of the USB based on the state signal; the differential signal pair includes a differential signal D+ and a differential signal D-; the state signal is any one of SE0, J, and K; the target state is any one of a suspended state, a wake-up state, a reset state, a general working state, and a wake-up request state; a high-speed handshake unit, configured to control the USB to perform high-speed handshake detection after the reset state, and to close the high-speed handshake unit after the high-speed handshake detection, so that the USB re-enters the general working state; and a state transition control unit, configured to manage the current state of the USB and transition the current state of the USB to the target state.

This invention discloses a three-state event-driven homogeneous parallel integrated circuit architecture, belonging to the field of integrated circuit technology. This invention aims to address the technical shortcomings of traditional synchronous clock architectures, such as high power consumption and poor scalability, as well as the low efficiency of existing asynchronous architectures. The core of this architecture includes a scalable homogeneous computing unit array, an event-driven asynchronous interconnect network, a three-state parallel bus, and a system bridge unit. This architecture abandons a global clock and adopts a three-state logic encoding and event-driven mechanism to achieve autonomous operation of processing units and low-power communication. This invention combines high computing density, low power consumption, and strong scalability, and can be widely applied in high-performance computing and edge intelligent terminal fields.

A capacitive coupling isolation device and a receiving circuit are provided. The capacitive coupling isolation device includes an external coupling capacitor and the receiving circuit. The external coupling capacitor is electrically connected to a transmitting circuit and the receiving circuit. The receiving circuit includes a protection circuit architecture, which includes an input bonding pad structure and a filter resistor. The input bonding pad structure is formed by alternatively disposing patterned metal layers and dielectric layers, and the input bonding pad structure includes a pad capacitor and a filter capacitor. The pad capacitor is electrically connected to the external coupling capacitor and a filter capacitor. The filter capacitor and the filter resistor are both electrically connected to the pad capacitor and a ground end. The filter capacitor and filter resistor form a low-pass filter. The external coupling capacitor is a built-in package capacitor.

This invention relates to a water circuit control system and method for fuel cell system development and testing, comprising: a chilled water circulation module, a pure water replenishment module, a pure water circulation module, and a fuel cell system; the chilled water circulation module is positioned before the plate heat exchanger of the pure water circulation system to remove heat from the test water circuit; the pure water replenishment module supplies pure water to the water circuit system and completes venting before testing, and controls and adjusts the circulating water volume during testing; the pure water circulation module provides pure water circulation to the fuel cell system, and accurately monitors, controls, and adjusts the flow rate and temperature of the pure water. This invention, applied to the water circuit control system for fuel cell system development and testing, improves the efficiency and stability of the test preparation phase, reduces system modification and debugging time caused by water circuit mismatch, and ensures that a stable pure water circulation can be quickly and reliably established in fuel cell system tests with different water circuit architectures.