391 results about "Circuit architecture" patented technology

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: acquiring original data from a host system; executing a plurality of randomization operations on the original data to obtain a plurality of write-in data; based on a plurality of directions of a three-dimensional circuit architecture of the rewritable nonvolatile memory module, executing randomization verification operation on each piece of write-in data to verify the data uniformity of each piece of write-in data in each direction so as to obtain target write-in data in the plurality of pieces of write-in data, wherein the randomized quality of the target write data is determined to be qualified; and storing the target write data to a plurality of target memory cells among the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

The invention relates to the field of electronic design automation (EDA), and provides an AMS circuit automatic design method using a large language model. The method aims at solving the problem that an existing AMS circuit design is insufficient in automation degree, and mainly comprises the steps that a schematic circuit diagram and text description are extracted from literatures, and a data set containing the schematic circuit diagram, a netlist and annotation information is constructed; performing connectivity detection on the schematic circuit diagram, and extracting a netlist; carrying out annotation processing to obtain annotation information; constructing a knowledge graph for storing circuit information; obtaining a design strategy by using a large language model, and describing a circuit architecture; according to the design strategy and the local annotation, relevant circuits and test platforms are retrieved, a complete circuit topology is assembled, and simulation is carried out; size optimization is carried out based on constraints, and a Bayesian optimization algorithm is used for solving; and if the initial topological structure cannot meet the performance target, carrying out topological reconstruction. According to the invention, the automation level and efficiency of analog and mixed signal circuit design are improved.

The invention discloses a broadband multi-level three-dimensional vertical interconnection structure based on an HTCC technology, and belongs to the field of radio frequency front-end system integration. The structure comprises a PCB mother board, a ball grid array and an SiP module which are sequentially arranged from bottom to top, in the SiP module, the chips are distributed among different levels, and a connection mode of the chips among the different levels is set; a radio frequency signal is transmitted upwards through the PCB mother board, and after flowing through the lower-layer bare chip, the radio frequency signal is orderly transmitted upwards through the strip line and the signal via hole in the HTCC and finally transmitted to the surface-layer chip, so that a complete and efficient vertical interconnection signal transmission system is formed. According to the invention, the layout flexibility of interconnection lines among the chips is improved, the wiring crosstalk among the chips is reduced, the three-dimensional integration scene of bare chips in the HTCC is greatly widened, high-density SiP packaging is realized, and the strict technical requirements on radio frequency signal transmission, processing and chip interconnection under a complex circuit architecture can be met.

The invention discloses a display device and a control method of the display device. The display device comprises a plurality of sub-pixel circuits, and each sub-pixel circuit comprises a light-emitting element, a pulse width modulation (PWM) circuit, a plurality of sub-pixel circuits and a plurality of sub-pixel circuits, a pulse width modulation (PWM) driving circuit and a pulse amplitude modulation (PWM) driving circuit; the invention relates to a PAM drive circuit. The PAM driving circuit is used for controlling the current value of the light-emitting element. The PWM driving circuit is used for controlling the light-emitting time of the light-emitting element. The PWM drive circuit and the PAM drive circuit receive a data signal to perform a PWM control mode or a PAM control mode on the light emitting element according to a value of the data signal, and provide a circuit architecture (16T3C) of 16 transistors and 3 capacitors. The control method of the display device comprises a reset operation, a plurality of compensation operations, a plurality of light-emitting control operations, a stabilizing operation and a closing operation.

The embodiment of the invention provides a power amplifier, a radio frequency module and electronic equipment. The power amplifier comprises a signal input end, a signal output end and a plurality of tube cores which are connected in parallel; the tube core comprises electrode finger strips extending along a first direction, and the electrode finger strips comprise a grid electrode finger strip, a source electrode finger strip and a drain electrode finger strip; in the second direction, the signal input end and the signal output end are located on the two sides of the multiple tube cores respectively, and the second direction is perpendicular to the first direction. The extension direction of the electrode finger strips is perpendicular to the signal input / output direction, so that the performance of the electrode finger strips can be optimized to the maximum extent and the requirement of high power can be met under the limited layout area, and the flexible possibility is created for the circuit architecture design.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

The invention discloses a novel chopping correlation double-sampling stable multi-path amplifying circuit and method, and relates to integrated circuit design. A Miller compensation capacitor in a chopping stable multi-path CSMP amplification circuit architecture is utilized to design a chopping correlation double-sampling circuit, and compared with a traditional correlation double-sampling circuit, a group of sampling capacitors and sampling switches are reduced. Large capacitance and large resistance required by a traditional high-pass filter circuit are eliminated, and the layout area and the current required for driving a high-pass filter capacitor are reduced; and thermal noise caused by large resistance in the passive high-pass filter is reduced, and the input equivalent noise density is improved. Through an offset calibration technology, the stability of the CSMP architecture is ensured, and the offset voltage is reduced at the same time; output ripples are suppressed by using the high-pass performance of the novel chopping correlation double-sampling circuit, 1 / f noise is reduced, and input equivalent noise density is reduced. The advantages of the chopping correlation double sampling technology and the stable multi-path amplification circuit are combined, and the advantages of low offset, low output ripple and low input equivalent noise density are achieved.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

The invention provides a solid-state transformer. The solid-state transformer comprises a first-stage circuit, a first direct-current bus and a second-stage circuit, the first-stage circuit structure is used for receiving alternating-current electric energy and converting the alternating-current electric energy into first direct-current electric energy. The first DC bus is electrically connected to first DC electric energy. The second-stage circuit is electrically connected to the first-stage circuit through a first DC bus, and is configured to perform isolated step-down DC / DC conversion on the first DC electric energy to generate second DC electric energy. The first stage circuit is configured to operate with a modulation index greater than 1, and the modulation index is defined as a ratio of twice an AC voltage provided by the AC power to a voltage on the first DC bus.

The invention discloses an energy storage system parallel operation circuit and a control method thereof. The energy storage system parallel operation circuit comprises a master battery cluster loop, a slave battery cluster loop and a battery cluster pre-charging equalization loop. And the pre-charging equalization loop is provided with a controllable resistor bypass which is connected in parallel with the contactor and is controlled by the battery management system. A charging and discharging parallel operation strategy is divided, the voltage of a battery cluster is collected, a pre-charging equalization loop is connected, and primary and secondary closing operations are carried out based on the voltage state. The problem of circuit and device damage caused by impact current due to large inter-cluster voltage difference is solved through the master-slave configuration pre-charge equalization loop; meanwhile, the problem of long parallel operation time caused by separation of a pre-charging time sequence and an equalization time sequence is solved by combining a control method; through the dynamic secondary closing operation, the problem that balance is easily damaged by voltage fluctuation in the parallel operation process, and parallel operation fails is solved, parallel operation can be achieved without system restart in a loop under a complex scene in cooperation with a circuit architecture, and the parallel operation reliability, the operation stability and the charging efficiency of the energy storage system are effectively improved.

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: firstly, obtaining original data from a host system; then, a plurality of randomization operations are performed on the original data to obtain a plurality of write-in data. Next, based on a plurality of directions of a three-dimensional circuit architecture of the rewritable nonvolatile memory module, a randomization verification operation is performed on each write data to obtain a target write data among the plurality of write data, where the randomization quality of the target write data is determined to be qualified. Finally, the target write data is stored in a plurality of target memory cells of the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

A capacitive coupling isolation device and a receiving circuit are provided. The capacitive coupling isolation device includes an external coupling capacitor and the receiving circuit. The external coupling capacitor is electrically connected to a transmitting circuit and the receiving circuit. The receiving circuit includes a protection circuit architecture, which includes an input bonding pad structure and a filter resistor. The input bonding pad structure is formed by alternatively disposing patterned metal layers and dielectric layers, and the input bonding pad structure includes a pad capacitor and a filter capacitor. The pad capacitor is electrically connected to the external coupling capacitor and a filter capacitor. The filter capacitor and the filter resistor are both electrically connected to the pad capacitor and a ground end. The filter capacitor and filter resistor form a low-pass filter. The external coupling capacitor is a built-in package capacitor.

Filter devices and fabrication methods are disclosed. A filter device includes a piezoelectric plate and a conductor pattern on a front surface of the piezoelectric plate. The conductor pattern includes interdigital transducers (IDTs) of a plurality of transversely-excited film bulk acoustic resonators (XBARs) and a plurality of conductors connecting the plurality of XBARs in a ladder filter circuit architecture. The plurality of conductors includes a first conductor adjacent to a second conductor. An opening is provided through the piezoelectric plate between the first conductor and the second conductor.

The invention discloses a memristor-based brain-like neural morphological circuit architecture, which comprises a plurality of operational amplifiers, a plurality of resistors and a plurality of brain-like neural network circuit system units with row and column structures, the brain-like neural network circuit system unit comprises a voltage source, a memristor and an NMOS (N-channel Metal Oxide Semiconductor) tube; the voltage source is used for providing input for the cranial nerve-like morphological circuit architecture; the NMOS transistor is used for regulating the positive and negative of the synaptic weight represented by the memristor; the last row of cranial nerve-like network circuit system units of the cranial nerve-like morphological circuit architecture are connected with an arithmetic unit and a resistor, and the resistor is connected between the operational amplifiers. The electrical behavior of the metal oxide memristor is better shown through the improved memristor model, and compared with other traditional architectures, the cranial nerve-like morphological circuit architecture built based on the memristor model greatly reduces the scale of the circuit architecture, reduces the energy loss of system operation, and improves the reliability of the system. And the entity cost is greatly reduced.

The invention discloses a broadband digital phase shifter based on an inductor sharing topology and an equivalent band-pass network, relates to the technical field of microwave integrated circuits, and is suitable for being applied to a Sub-GHz frequency band. The phase shifter comprises a phase shift circuit module and a driving circuit module, and the phase shift circuit module comprises six basic phase shift units including a fine phase shift unit and a coarse phase shift unit which cooperatively realize full-range multi-state phase shift. The fine phase shift unit adopts an inductor sharing topology, so that a phase shift path and a reference path share a circuit architecture, the design is simplified, and the chip layout is optimized; the coarse tuning phase shifting unit adopts an all-pass network as a reference path, a phase shifting path is an equivalent band-pass network formed by cascading a high-pass network and a low-pass network, and the 180-degree phase shifter adopts a double-inductor all-pass network to optimize amplitude-frequency response. And the driving circuit module outputs complementary voltage pairs through the level conversion circuit to drive the switching transistor to realize path switching. The antenna has the advantages of being compact in structure, stable in amplitude, excellent in radio frequency performance and high in adaptability.

A memory device having a row decoder circuit architecture is provided. The memory device includes a peripheral circuit structure and a cell array structure provided on the peripheral circuit structure and vertically overlapping the peripheral circuit structure. The cell array structure may include a plurality of memory blocks including a plurality of vertical channel transistor structures and a plurality of capacitor structures respectively connected to the vertical channel transistor structures. The peripheral circuit structure includes a row decoder connected to a plurality of word lines of the plurality of memory blocks, and the row decoder includes a first circuit group commonly connected to the plurality of memory blocks and a second circuit group connected to each of the plurality of memory blocks.

The invention relates to the technical field of electric car braking, and discloses an electric car braking system based on multi-redundancy guarantee and self-adaptive control and a control method, and the electric car braking system comprises a redundant circuit module, a distributed driving module, an efficient transmission module and a self-adaptive control center. The reliability is remarkably improved, seamless switching of a main circuit and a standby circuit within 50 ms is achieved through a circuit dual-redundancy architecture, the distributed multi-motor driven torque reconstruction algorithm is matched, the braking efficiency retention rate under a single fault is improved, the circuit fault survival rate reaches 100%, the braking efficiency and safety are optimized, the mechanical loss is reduced to 8% or below through an efficient transmission module, and the reliability is improved. The braking distance of 100 km / h is shortened to 29 m, the energy utilization efficiency is improved, the energy consumption is further reduced through the low-friction transmission design, the dynamic adaptability and the collaboration are enhanced, a self-adaptive control center solves the multi-system instruction conflict through multi-sensor fusion and fuzzy PID adjustment with the sampling frequency of 1 kHz, the braking stability is improved by 40% or above, and the braking stability is improved by 20% or above. And the response time of the key control instruction under the emergency working condition is shortened to 75mS.

A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a dynamic delay adaptive asynchronous time sequence control circuit for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). According to the circuit disclosed by the invention, through an innovative circuit architecture and a control method, remarkable breakthrough is realized in the aspects of conversion precision and speed. According to the circuit, a unique two-stage dynamic delay adjustment mechanism is adopted, intelligent optimization of delay time is achieved based on real-time comparison frequency monitoring, the effective conversion rate under 16-bit precision is improved by 25% or above, and meanwhile it is kept that ENOB is not lower than 15 bits. The innovative current charging capacitance type delay unit is combined with the PVT compensation technology, and the delay time stability is superior to + / -3% within the working temperature range of-40 DEG C to 125 DEG C. Through a dynamic adjustment algorithm of cooperative work of a shift register and a lookup table, the system can automatically adapt to establishment time change of 10 ns to 50 ns, and compared with a fixed delay scheme, invalid waiting time is saved by more than 30%.

Systems and methods are presented herein that include utilizing a specialized circuit architecture for the purpose of locating lost items through voice command recognition. The system can be customized with minimal, low power components to continuously monitor for a locating phrase and produce an audible alert when the locating phrase is detected. The system can be included in a stand-alone portable device that can be attached to electronic and non-electronic portable objects, or the system can be embedded with other circuitry into a portable electronic device. The system can be powered by battery such that it is practical for the device to function as a locating device, continuously monitoring for the locating phrase. Voice recognition can be performed completely within the system, providing the benefit of privacy.

The application provides a pulse density modulation interface implementation method and device of an analog-to-digital converter, electronic equipment and a storage medium. The method comprises the following steps: designing a circuit architecture of an analog-to-digital converter, and setting working variable parameters for components in the circuit architecture; determining a transfer function of an output signal and a transfer function of noise based on the working variable parameters; in the case that an oversampling rate (OSR) is a first set value, a filter order is a second set value, and a quantization bit number is a third set value, calculating an optimal solution of the transfer function of the noise; determining a value corresponding to the working variable parameters of the components according to the optimal solution; and selecting corresponding components for the circuit architecture based on the value, and generating a pulse density modulation interface of an analog-to-digital converter. The application can accurately design a PDM interface, and improves the signal processing performance of the interface.

Architectures and techniques relate to selectively implementing certain components to filter emissions. For example, a circuit can include a filter associated with a first frequency range, a first switch, and a second switch. The first switch can be configured to, in a filter state, route a signal through the filter and configured to, in a bypass state, route the signal to an output node while bypassing the filter. The second switch can be configured to, in the filter state, route the signal from the filter to the output node.

The invention discloses a small-sized wide instantaneous bandwidth radio frequency receiving front-end SiP module based on an HTCC, and belongs to the technical field of microwaves and radio frequency. The radio frequency receiving front end is realized on the basis of an SiP module of the HTCC, the mirror image frequency is far away from the radio frequency signal frequency spectrum through a high local oscillator dual-frequency conversion mode, and the spurious component generated by frequency mixing is moved to a high-frequency area outside an intermediate-frequency passband, so that wide instantaneous bandwidth and high spurious suppression are realized. According to the invention, miniaturization of the SiP module is realized based on the HTCC technology; a secondary frequency conversion superheterodyne circuit architecture and a high local oscillator design are combined, so that the instantaneous working bandwidth is widened to 4GHz, and meanwhile, high spurious suppression is realized; in addition, the vertical interconnection structure is improved, long-distance low-loss transmission of radio-frequency signals is achieved, and the size is further reduced. The ultra-wideband low-noise amplifier has the advantages of miniaturization, wide instantaneous bandwidth, low noise amplification and high spurious suppression, and a solution is provided for miniaturization and low-cost mass production of an ultra-wideband radio frequency system.

The invention discloses an inverter architecture allowing a bus to be externally connected and a control method, the inverter architecture comprises a communication module and a circuit architecture of a power generation system, the communication module is preset with a communication interface, and a bus interface is reserved at a direct current bus position of the circuit architecture; the energy storage module is suitable for being respectively connected with the communication interface and the bus interface so as to access the inverter architecture; the communication module is suitable for performing charging and discharging control on the energy storage module through the communication interface; the energy storage module is suitable for charging and discharging through the bus interface. The control method is used for controlling the inverter architecture. The inverter architecture has the beneficial effects that the bus of the circuit architecture is allowed to be externally connected, and the inverter architecture can be used as a power generation system or an energy storage power generation system according to whether the energy storage module is connected or not, so that the whole system structure is very flexible.

The invention discloses a CGRA multi-task dynamic resource allocation method and a hardware circuit, and belongs to the technical field of dynamic resource allocation. The method specifically comprises the following steps: recording the attribute of each task by using a task attribute table; updating a task attribute table according to a central processing unit message, and generating a task queue and a Boolean value for triggering dynamic resource allocation; the number of processing units is calculated and allocated according to task priorities and the number of data flow diagram nodes; determining the shape of the distributed processing unit according to the number of the distributed processing units; pre-loading the configuration information into a configuration memory of the processing unit so as to match the shape of the allocated processing unit; and dynamic resource allocation is realized by using a finite-state machine. According to the hardware circuit, on the basis of an original CGRA circuit architecture, a dynamic resource distributor, a configuration transmission bus between processing units and configuration receiving circuits in the processing units are added. According to the method, dynamic resource changes caused by task creation and destruction can be flexibly handled.

The invention discloses a frequency duplex synthesis method for realizing a terahertz ultra-wideband frequency multiplier, and relates to the technical field of submillimeter wave / terahertz solid-state frequency multipliers, a'frequency division-frequency multiplication-frequency combination 'duplex circuit architecture is adopted, a frequency division circuit and a frequency combination circuit are both based on a hybrid network type waveguide duplexer design, and the frequency division-frequency multiplication-frequency combination duplex circuit design is adopted. The frequency multiplier circuit is realized by adopting a hybrid integrated frequency doubler, the cost is low, the cavity structure is completely processed by adopting a CNC milling process, and the solid-state characteristic is realized; therefore, under the condition that the frequency doubling / frequency conversion efficiency is not reduced, the frequency doubler capable of covering the full frequency band of 170-260GHz (WR-4 frequency band) can be realized, namely, the double advantages of wide frequency band and high efficiency of the frequency doubler are considered, and the technical problem that the wide frequency band and the high efficiency of a submillimeter wave / terahertz schottky frequency doubler at the present stage cannot be achieved at the same time is solved.

The invention provides an ultra-low-frequency noise resistance-free band-gap reference power supply, which is applied to the technical field of band-gap reference power supplies, in the band-gap reference power supply, BJTs with different emitter junction areas are firstly utilized, when collectors work under equal current bias and work at different current densities, a BE junction voltage difference can be generated between two transistors, and the BE junction voltage difference can be generated between the two transistors; then, the BE junction voltage difference does not need to act on a resistor to avoid low-frequency 1 / f noise and thermal noise introduced into the resistor, that is, the BE junction voltage difference is used for lifting the potential where the base-emitter voltage of the transistor is located so as to obtain band-gap reference voltage, and finally the band-gap reference voltage can be obtained by utilizing the characteristic that the base-emitter voltage of the transistor is a negative temperature coefficient. By combining the characteristic that the BE junction voltage difference is a positive temperature coefficient, a new circuit architecture with the positive temperature coefficient and the negative temperature coefficient overlapped to achieve the compensation effect is jointly formed, and therefore the band-gap reference voltage source with the zero temperature coefficient can be obtained only by selecting proper circuit parameters.

The invention discloses a high-voltage multi-section constant-current LED emergency lighting driving system and a control method. Relates to the technical field of power supply. Comprising LED lamp beads, an alternating current power supply part, an EPS power supply part and a driving IC. The alternating current power supply part and the EPS power supply part supply power to the same LED lamp bead through the same driving IC; according to the scheme, a traditional circuit structure is improved, the alternating current power supply part and the EPS power supply part supply power to the same LED lamp bead through the same driving IC, and the purposes of reducing cost and simplifying a circuit are achieved; wherein the alternating current power supply part accords with high-low voltage power grid input and meets sub-harmonic requirements; meanwhile, the EPS power supply part outputs constant voltage, the output power of the voltage changes along with the combination of the LED lamp beads, linear driving is shared to realize single-section constant current, and the purposes of reducing the cost and simplifying the circuit are realized on the premise of flexibly realizing EPS illumination application of different powers.