2888 results about "Comparator" patented technology

The invention provides a display device and a driving chip of a display panel. The display device comprises the display panel and the driving chip. The driving chip comprises a first comparator and a second comparator; the driving chip is used for dividing the output channels corresponding to the at least two data lines into a first channel with positive polarity and a second channel with negative polarity; a first comparator for comparing the first voltage with a first reference voltage to output a first level; the second comparator is used for comparing the second voltage with a second reference voltage and outputting a second level; and the driving chip is also used for continuously monitoring the first level and the second level so as to detect whether a short circuit between the data lines occurs in the display panel or not. The data line is divided into the positive and negative polarity channels through the driving chip, the comparator is used for comparing the channel voltage with the reference voltage, the level change is monitored to detect the short circuit, an amplifier and a complex switch assembly do not need to be additionally arranged, the circuit structure is simplified, and the manufacturing cost is reduced.

The invention provides an ultrasonic fingerprint chip and an integral clock generation method and device of the ultrasonic fingerprint chip. Appropriate fingerprint pixel units can be selected from a plurality of fingerprint pixel units to serve as first-class pixel units and second-class pixel units, and the first-class pixel units and the second-class pixel units are respectively connected with a first-class detection circuit and a second-class detection circuit. Wherein a first integrator in the first type of detection circuit is sequentially connected with a first comparator, a time delay regulator, a clock dominant frequency duplicator and a frequency dividing circuit; the frequency dividing circuit is connected with the second type detection circuit; a second integrator in the second type detection circuit is connected with an amplification structure; the amplification structure is also connected with a second comparator; and the second comparator is connected with the time delay regulator in the first-class detection circuit. The circuit can automatically generate and obtain the integral clock signal which is matched with the ultrasonic fingerprint echo signal and is high in precision and good in effect, so that the received ultrasonic fingerprint echo signal is precisely processed, and a target signal with high quality is obtained.

The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

The invention discloses an overcurrent protection control circuit of a low-dropout linear regulator and the low-dropout linear regulator, and relates to the field of voltage regulators. A first sampling module is connected with a drain electrode, a grid electrode and a source electrode of a power control tube in the low-dropout linear regulator and a first current comparator; the first current comparator is further connected with the grid electrode of the first protection switch and the input voltage end of the low dropout linear regulator, the source electrode of the first protection switch is connected with the grid electrode of the power control tube, the drain electrode of the first protection switch is grounded, and the source electrode of the power control tube is connected with the voltage output end of the low dropout linear regulator; the second sampling module is respectively connected with the drain electrode of the power control tube, the grid electrode of the power control tube and the clamping module, the clamping module is connected with the grid electrode of the second protection switch through the second current comparator and is also connected with the source electrode of the power control tube, the drain electrode of the second protection switch is grounded, and the source electrode of the second protection switch is connected with the grid electrode of the power control tube. The reliability of current limiting can be improved.

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

The present invention provides a DCDC converter using a dual-mode adaptive off-time timer, comprising: a PWM comparator, an on-time timer, a current detection module, an off-time timer logic control circuit, a drive control circuit, a dual-mode adaptive off-time timer, an inductor LOUT, an NMOS transistor MH, an NMOS transistor ML, a resistor RFB2, a resistor RFB1, and a capacitor COUT. The present invention is implemented by means of the PWM comparator, the on-time timer, the current detection module, the off-time timer logic control circuit, the drive control circuit, and the dual-mode adaptive off-time timer. The off-time of the internal dual-mode adaptive off-time timer has the function of adaptively adjusting an input signal and an output feedback signal, and a minimum off-time timer and an overcurrent off-time timer are simultaneously implemented by using one off-time timer.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

The invention provides a radon gas detection method and device, electronic equipment and a storage medium. The method comprises the following steps: collecting a plurality of first electric signals from electric signals flowing through a comparator according to a preset time interval in a target time range; in response to the received interrupt signal from the comparator, determining a second electric signal corresponding to the occurrence moment of the interrupt signal from the plurality of first electric signals; determining a first noise value according to the plurality of third electric signals; the first range value is compensated according to the first noise value, a second range value is determined, the first range value is used for representing a signal peak range of particles corresponding to radon in a noise elimination state, and the plurality of third electric signals are signals different from the second electric signals in the plurality of first electric signals; determining a fourth electric signal whose signal peak value satisfies a second range value from the second electric signals; and determining the concentration value of the radon gas according to the number of the fourth electric signals. The accuracy of radon gas concentration detection can be improved.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. In a sampling stage, upper electrode plates of a plurality of first capacitors are connected with an input voltage Vin, part of lower electrode plates are connected with the input voltage Vin, and part of the lower electrode plates are connected with a reference voltage Vref; the upper electrode plates of the plurality of second capacitors are connected with a reference voltage Vref, part of the lower electrode plates are connected with an input voltage Vin, and part of the lower electrode plates are connected with the reference voltage Vref; in the pre-switching stage, an upper pole plate switch is switched off, and lower pole plate voltages of the multiple first capacitors and the multiple second capacitors are switched according to a preset mode, so that the upper pole plate voltages of the multiple first capacitors are all changed into a first preset voltage Vp, and the upper pole plate voltages of the multiple second capacitors are all changed into a second preset voltage Vn; in the comparison stage, the first preset voltage Vp and the second preset voltage Vn are input into the comparator for first-stage comparison. Through preset switching logic, single-ended analog-to-digital converter input can be converted into differential comparator input.

An inductor-inductor-capacitor (LLC) converter may include a control system that holds a duty cycle of control signals at a desired ratio, such as 50%. The control system may include a counter that is configured to count up and down and is further configured to generate event signals that are received at the inputs of a latch. An event signal may cause and output value of the latch to change from high to low or vice versa. There may be further circuits to add delay and / or inversion to generate multiple control signals from the output of the latch. Furthermore, the counter may be configured to switch from counting up to counting down in response to a comparator output.

The invention belongs to the technical field of distributed optical fiber sensing (DAS) system signals, and discloses a time axis phase unwrapping method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps of phase data acquisition, stable group formation, phase progressive unwrapping, assembly line and cache cooperative processing and quality measurement closed-loop correction. According to the system, real-time phase extraction of interference signals is achieved through the FPGA demodulation unit, phase change is dynamically unwrapped through the reliable period screening unit and the phase progressive unwrapping unit, a self-adaptive unwrapping mechanism is formed in combination with anomaly judgment and threshold updating logic, and through collaborative design of an annular cache and a three-level assembly line comparator, the interference signal is obtained. According to the method, parallel transmission and time sequence synchronization of data are achieved, the precision and stability of phase unwrapping can be effectively improved in a complex noise environment, hardware delay and resource occupation are remarkably reduced, and the method is suitable for real-time signal unwrapping processing of a high-precision distributed optical fiber sensing system.

The invention relates to the field of switching power supply management integrated circuits, in particular to a self-adaptive conduction time generating circuit for a BUCK type DC-DC converter, which comprises a charging circuit (1) and a sampling circuit (2), and is characterized in that the charging circuit (1) generates charging current in direct proportion to input voltage through a charging capacitor (C1) and a comparator (OP2), and charges the C1 to obtain first charging voltage; the sampling circuit (2) samples and filters the voltage of the switch node (SW), and outputs a first sampling voltage in direct proportion to the output voltage; and the comparator (OP2) compares the first charging voltage with the first sampling voltage, and outputs a turn-off signal to control the upper power tube to be turned off when the first charging voltage and the first sampling voltage are equal, so that the self-adaptive turn-on time is obtained. By dynamically adjusting the conduction time, the electromagnetic interference in the traditional constant conduction time control is effectively suppressed, the noise immunity and reliability of the system are improved, and meanwhile, the method has the advantages of quick response and high efficiency.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

An error correction method for a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter (SAR ADC) are disclosed, which relate to integrated circuit technology. The successive approximation register analog-to-digital converter error correction method includes the following steps: a. detecting whether a comparator completes a data comparison within a specified time; if so, performing step b; if not, performing step c; b. after the comparator outputs data, starting a next data comparison cycle, and returning to step a; and c. interrupting the conversion, waiting for a signal to start a next conversion, starting the next data comparison cycle, and returning to step a. The method and SAR ADC can effectively prevent problems relating to (1) slow comparator speed caused by dead voltage and (2) burr interference.

The invention discloses an optical Gray code encoder temperature compensation method and system based on an NTC resistance network, and the method comprises the steps: calibrating a PD signal drift law in a working temperature range, designing an NTC voltage division circuit matched with the law, and integrating the NTC voltage division circuit to a comparator, thereby achieving the real-time offset of the PD signal temperature drift. According to the scheme, the defects that in the prior art, complexity is high and cost is high are overcome, compensation precision within + / -0.5% is achieved only through basic electronic elements, the response speed reaches the microsecond level, cost is reduced by 60% or above, the method is suitable for wide-temperature-range scenes ranging from-40 DEG C to 85 DEG C, and a low-cost and high-precision temperature compensation solution is provided for precise measurement of high-end equipment.

The invention discloses a charging management circuit and a charger. The charging management circuit comprises a flyback converter, a first sampling feedback module, a second sampling feedback module and an optocoupler. The first sampling feedback module comprises a comparator, a first switch unit, a thermosensitive voltage dividing unit and a current sampling resistor. The duty ratio of a PWM chip is controlled through an optocoupler to achieve constant-current charging in the first charging stage. The resistance of the thermosensitive voltage dividing unit is increased when the temperature rises, the charging current is automatically reduced, and temperature self-adaptive protection is achieved. And when the charging current is reduced to a preset value, the second sampling feedback module takes over the control optocoupler to realize constant-voltage charging in a second charging stage. Constant-current and constant-voltage two-stage charging can be achieved, the function of automatically adjusting the charging current through the temperature is achieved, the charger is effectively prevented from being overheated in the high-temperature environment, and the safety of the charger and a battery is protected.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The utility model discloses a constant-current and constant-voltage circuit without software control, which comprises a Buck power level circuit, a voltage sampling circuit, a current sampling circuit and an error amplifying circuit, and the error amplifying circuit is provided with a first error amplifier and a second error amplifier. The output end of the first error amplifier and the output end of the second error amplifier are electrically connected with the Buck power level circuit, the Buck power level circuit is electrically connected with the voltage sampling circuit and the current sampling circuit, the voltage sampling circuit is electrically connected with the first error amplifier, and the current sampling circuit is electrically connected with the second error amplifier. An FREQ pin of a Buck chip U4 is grounded, a 0.76 V voltage is obtained through voltage division by a resistor R27 and a resistor R29, so that the switching frequency of a Buck power level circuit is invalid, the voltage is controlled through a first error amplifier, the current is controlled through a second error amplifier, the first error amplifier and the second error amplifier carry out operation, and then a PWM comparator in the Buck chip U4 is controlled through a COMP pin of the Buck chip U4. Therefore, voltage and current are controlled.

The invention discloses a CAN bus activity detection and wake-up circuit and method, and belongs to the technical field of CAN bus communication, the CAN bus activity detection and wake-up circuit comprises a CAN bus interface circuit, a signal detection and processing circuit and a controller, the input end of the CAN bus interface circuit is connected with a CAN bus; the signal detecting and processing circuit comprises a voltage comparator, the non-inverting input end and the inverting input end of the voltage comparator respectively receive a CANH signal and a CANL signal which are electrically isolated by the CAN bus interface circuit, and the output end of the voltage comparator is connected to a wake-up pin of the controller; the controller is used for monitoring the level state of the wake-up pin, and when the level of the wake-up pin is in an effective state, the electronic equipment is controlled to be switched from the sleep mode to the normal working mode. By introducing an electrical isolation and voltage difference detection mechanism, the problem of false wake-up caused by common-mode interference or bus noise in the prior art is solved, and reliable wake-up under low power consumption is realized.

The invention discloses a logarithmic pixel signal quantization method and module based on gain dynamic adjustment, and an image sensor. The logarithmic pixel signal quantization method comprises the following steps of: converting light current into logarithmic voltage by logarithmic amplification by using a logarithmic response unit; the voltage type comparator compares the logarithmic voltage with a threshold voltage, outputs a gain regulation and control signal for gain configuration of the programmable gain amplifier and input reference voltage switching, enables the programmable gain amplifier to work in different gain modes, and inputs a flag bit to the N-bit analog-to-digital converter; based on the current gain mode, the programmable gain amplifier amplifies the logarithmic voltage and translates the logarithmic voltage into the quantization range of the N-bit analog-to-digital converter to be output; the N-bit analog-to-digital converter samples an output voltage signal of the programmable gain amplifier, combines the output voltage signal with a flag bit, and outputs an N + 1-bit equivalent digital code value signal. According to the invention, high-sensitivity quantization of low-light-intensity signals and high-precision conversion of high-light-intensity signals are realized at the same time.

The invention discloses a battery deformation monitoring method and device, a storage medium and computer equipment, and the method comprises the steps: enabling a flexible capacitive sensor to be attached to the surface of a target monitoring battery, and sensing the capacitance change caused by the deformation of the battery; the capacitance change is converted into a frequency signal through an LC oscillation circuit; a high-speed comparator is adopted to convert the frequency signal into a square wave; and the microcontroller captures the frequency of the square wave and inversely calculates the capacitance value, the capacitance change rate is calculated by combining a sliding window algorithm, median filtering and a temperature compensation technology, and if the capacitance change rate exceeds a preset threshold value, the battery deforms, so that the high-accuracy and high-reliability real-time monitoring and early warning effects on the battery deformation phenomenon are achieved.

The invention relates to an ultra-low power consumption control method and system for a coal mine vibration sensor, and belongs to the technical field of dust treatment. The problems that a detection circuit cannot sleep and standby power consumption is too large due to continuous vibration signals are solved. According to the technical scheme, a vibration signal direct-current component is removed through an alternating-current coupling module, an alternating-current signal is converted into a one-way pulse signal through a rectification amplification module, and a stable direct-current voltage Vk is generated through a low-pass filtering module. The threshold value comparison module compares the Vk with a preset threshold value Vref in real time, and when the output level of the comparator jumps, the MCU is awakened to process the vibration state and sleep again. The system adopts a dual-mode switching mechanism: switching to a low-level wake-up mode after a high-level trigger processing vibration existence event, and switching to a high-level wake-up mode after a low-level trigger processing vibration disappearing event. According to the method, deep dormancy in a continuous vibration environment is realized, invalid wake-up times are reduced, the influence of diode voltage drop is eliminated, and the target of ultra-low standby power consumption is achieved.

The invention relates to the technical field of control system monitoring, and discloses a control system real-time monitoring method based on multi-unit cooperation, which comprises the following steps: receiving an initial adjustment instruction, recording a first moment, and inputting a monitoring signal sequence of a controlled unit into a comparator for setting a dynamic dead zone threshold; extracting a second moment when the signal amplitude exceeds the threshold value, and calculating a time domain difference value of the two moments to obtain response delay time; calculating a deviation value between the response delay time and a standard period to generate a feed-forward gain compensation parameter; when the polarity of a signal is reversed, a differential control instruction is issued according to a feed-forward gain compensation parameter, and a local communication receiving port is blocked. Physical action delay time is converted into bottom-layer mechanical retardation measurement, irreversible friction loss of a physical device is offset through feed-forward compensation; and high-frequency redundant pseudo signals are accurately filtered out to ensure the smoothness of a communication bus and maintain the stability of multi-unit cooperative adjustment under complex working conditions.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

The invention discloses a load transient detection circuit of a COT Buck, a corresponding COT Buck and a switching power supply. The load transient detection circuit comprises an input end, three resistors connected in series, two comparators and a switched capacitor sampling hold circuit, wherein the input end is grounded after passing through the three resistors in sequence. A node between the input end and the first resistor and a node between the second resistor and the third resistor are connected to the input ends of the first comparator and the second comparator through a switched capacitor sampling hold circuit structure. Valley voltage information and peak voltage information of inductive current are obtained through the switched capacitor sampling hold circuit, whether a load is transiently changed or not is judged by comparing inductive current ripples with a valley value and a peak value, and it is guaranteed that the switching power supply has appropriate transient detection trigger threshold voltage under any load. According to an output signal of the load transient detection circuit, the COT Buck can increase the turn-on or turn-off time so as to enhance the transient response speed.

The invention discloses a programmable low-temperature-drift under-voltage locking circuit, and the circuit comprises a reference current generation module which is used for outputting an initial reference current, and the input end of the reference current generation module is connected with a first reference voltage; the zero-temperature-drift current source array is used for generating reference current according to the initial reference current and the second reference voltage and mirroring the reference current to a plurality of parallel branches; the trimming module is used for adjusting the total current of the parallel branches by using a programmable resistor and a capacitor; the sampling module is used for sampling the total current and the power supply voltage of the parallel branches output by the trimming module; and the comparison output module is used for comparing the power supply voltage with a sampling voltage generated according to the programmable resistor and the total current of the parallel branches, and outputting a pair of differential signals. Through the reference current generation module, the zero-temperature-drift current source array, the trimming module, the sampling network and the voltage comparator, the problems that in an existing resistance voltage division type undervoltage locking scheme, a threshold value is fixed and cannot be adjusted, and the scheme is sensitive to temperature changes are solved.

The embodiment of the invention provides a power driving circuit, and relates to the technical field of vehicles. The device is suitable for the technical field of various new energy vehicles such as electric vehicles, hybrid power vehicles and fuel cell vehicles. The circuit comprises a power supply, a sampling resistor, an MOS tube, a current monitoring unit, a comparator, a triode and a micro-control unit. The power supply is connected with the MOS tube through the sampling resistor, and the MOS tube is used for being connected with a power load; the sampling resistor is connected with a first signal input end of the micro-control unit through the current monitoring unit, and a second signal input end of the micro-control unit is connected with an output end of the MOS tube; the output end of the current monitoring unit is connected with the input end of the comparator, the output end of the comparator is connected with the input end of the triode, and the output end of the triode is connected with the MOS tube. The method provided by the invention effectively solves the problems that the cost of power driving power is relatively high and the protection requirement of the domain control device cannot be met in the prior art.

An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter including: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in the comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier configured to generate, at an output terminal of the transconductance amplifier, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the transconductance amplifier and a ramp voltage generated by the ramp signal generator.