8101 results about "Comparator" patented technology

The invention relates to an ultrasonic flow metering device and a metering method thereof, and relates to the field of ultrasonic measuring devices. According to the metering device, through a cross-correlation operation circuit, a microcontroller, a double-threshold comparator, a peak detector, a gain adjustment circuit and a head wave threshold adjustment circuit, self-adaptive processing and adjustment of echo signals and head wave thresholds are achieved, and the accuracy and reliability of flow metering are improved. The metering method adopts an adaptive adjustment strategy of echo signal amplifier gain based on an output signal of an echo signal peak detection circuit, and a head wave threshold adaptive adjustment strategy based on a correlation operation value of echo signal sampling data and pre-stored reference wave data. According to the scheme, the stability of the echo signal and the rationality of the head wave threshold value are guaranteed, the method has adaptability to echo contour feature changes caused by transducer aging or contamination, and then the reliability of the flow metering process is guaranteed.

The invention discloses a phase change memory and electronic equipment, the phase change memory comprises a comparator, a second switch, a third switch, a memory circuit, a selected digital line, a first switch and an unselected digital line, the memory circuit, the selected digital line, the first switch and the unselected digital line are connected in sequence, and the reference voltage of the unselected digital line is set in a reading operation through the first switch and the third switch; the reference voltage is in positive correlation with the second negative voltage, the second negative voltage is smaller than the first negative voltage, and compared with the reference voltage which is in positive correlation with the first negative voltage, the lower reference voltage can be generated, so that the overshoot current flowing through the memory cell at the opening moment is reduced, and the reading interference suffered by the memory cell is reduced.

Described embodiments include a control circuit with a first comparator having a first comparator input receiving a first threshold voltage, and a second comparator input coupled to an output voltage terminal. A second comparator has a third comparator input receiving a second threshold voltage, and a fourth comparator input coupled to a current output terminal. A first logic circuit provides a true signal at its output responsive to a particular number of its inputs receiving a true input. A second logic circuit has inputs coupled to the first comparator output, and to the first logic output. A variable resistance circuit has an output coupled to a mode detection output. An amplifier has inputs coupled to the variable resistance circuit output, and a third reference voltage source. A duty cycle generation circuit provides a respective pulse width modulation (PWM) signal at each of its respective duty cycle outputs.

An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter, including: a comparator configured to compare a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in a comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier (TA) configured to generate, at an output terminal of the TA, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the TA and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the TA and a ramp voltage having a gradient proportional to a switching frequency of the Buck converter.

The invention discloses a dual-mode analog front end with a full-speed clock-free decision feedback equalizer (UC-DFE). The dual-mode analog front end comprises a terminating impedance matching network, a linear processing link, the UC-DFE and a signal output module, the terminating impedance matching network realizes broadband impedance matching and electrostatic protection; the linear processing link comprises a CTLE and a VGA and is used for compensating channel attenuation and expanding signal bandwidth; the UC-DFE comprises a summator, a static comparator, a delay unit and a feedback tap, and realizes high-speed signal processing and feedback equalization; and the signal output module converts the balanced signal into a target coding format and outputs the signal. According to the invention, the overall performance of the circuit is improved, the problems of time sequence tension, bandwidth limitation and the like of the traditional DFE architecture at a high speed are solved, and the circuit is suitable for 128Gbps high-speed PAM4 and NRZ signal transmission and shows better comprehensive performance.

A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to the technical field of high-voltage integrated circuits, and provides an under-voltage protection high-voltage integrated circuit. Comprising an RC filter circuit, a Schmidt circuit, a filter, a level conversion circuit, a temperature protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit, a bootstrap circuit, a dead zone interlocking circuit, a time delay circuit, a pulse circuit, a first high-voltage DMOS, a second high-voltage DMOS, an RS trigger, an output circuit and an AND gate. The under-voltage protection circuit comprises a voltage stabilizing circuit, a power supply voltage detection circuit, a comparator and a first NMOS tube. The input end of the voltage stabilizing circuit serves as the input end of the under-voltage protection circuit to be connected with power supply voltage, and the output end of the voltage stabilizing circuit is connected with the input end of the power supply voltage detection circuit and the negative input end of the comparator. According to the invention, the working stability and reliability of the HIVC in an application occasion with relatively large temperature change are improved, and the market competitiveness of a product is improved.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

An integrated circuit includes an error amplifier having a reference input, a feedback input, and an error output. A comparator has first and second comparator inputs and a comparator output. The first comparator input is coupled to the error output. A control circuit has a control input and a control output. The control input is coupled to the comparator output. The compensation circuit has a compensation control input and a compensation output. The compensation control input is coupled to the control output. The compensation output is coupled to at least one of the reference input, the feedback input, or the error output.

In an example, a method includes enabling a first voltage supply and a second voltage supply. The method also includes selecting, with a decision comparator, a selected voltage supply from either the first voltage supply or the second voltage supply based on which of the first voltage supply or the second voltage supply ramps up first. The method includes monitoring the selected voltage supply with the decision comparator. The method also includes, responsive to a voltage from the selected voltage supply dropping below a dropout voltage level of a low dropout regulator, switching to an other voltage supply with the decision comparator.

The invention belongs to the technical field of plasma sources, and provides a high-power high-stability remote plasma source fuzzy hysteresis control method and a circuit, when a reaction cavity is successfully ignited, a plasma source system is controlled to work at constant-frequency variable-duty-ratio constant-power output, and the method comprises the following steps: according to a sampled current value, a duty ratio, a predicted current value and a predicted duty ratio, calculating a constant-frequency variable-duty-ratio constant-power output value; respectively obtaining error control variables e and ec; the error control variables e and ec serve as input values of a fuzzy controller, and the actual control quantity hr output by the fuzzy controller is obtained; obtaining compensation variables # imgabs0 # and # imgabs1 # of the current and the duty ratio based on the error control variables e and ec; and taking the actual control quantity hr as the ring width value of a hysteresis comparator, and respectively compensating the current # imgabs4 # and the duty ratio # imgabs5 # at the moment k by outputting compensation variables # imgabs2 # and # imgabs3 # according to a preset rule. According to the method provided by the invention, a power window in a relatively wide range can be ensured, so that the working stability of the remote plasma source is improved, and the uniformity of a semiconductor manufacturing process is improved.

The invention provides a system and a method for verifying bifurcation characteristics of PCIe Switch, and relates to the technical field of PCIe. The forking characteristic verification system of the PCIe Switch comprises a DUT module, a first EP verification agent component, a second EP verification agent component, a first RC verification agent component, a second RC verification agent component, a first PHY verification agent component, a second PHY verification agent component and a configuration module. A configuration module, a first protocol comparator and a second protocol comparator, wherein the configuration module is used for configuring the bifurcation form of the uplink port and the downlink port and the behavior of each verification agent component; the first protocol comparator is used for verifying the bifurcation characteristic of the uplink port, and the second protocol comparator is used for synchronously verifying the bifurcation characteristic of the downlink port. The method has the advantages that the verification convergence speed is increased, and the verification rate is increased.

The present application relates to the technical field of integrated circuits, relates to a computing-in-memory circuit based on BNN algorithm acceleration, and solves the problems in the prior art of a large circuit area, high energy consumption, and low energy efficiency of computing-in-memory. The circuit comprises: selecting a first algorithm network and a second algorithm network from a flexible RRAM storage array; inputting a plurality of rows of data into the first algorithm network and a multiply-accumulate module to obtain a multiply-accumulate result, and inputting the multiply-accumulate result into a shifter; the shifter shifting the multiply-accumulate result, outputting the shifting result to an adder-subtractor to obtain a sum-calculation result and outputting the sum-calculation result to a comparator; the comparator performing binarization on the sum-calculation result, outputting the binarized sum-calculation result to a second algorithm network, performing recalculation to output a column accumulate current, and sending the column accumulate current to a maximum value comparator output module; and the maximum value comparator output module determining a column having the maximum column sum as a classification result. While keeping the original network precision, the required circuit area is greatly reduced, the energy consumption is reduced, and the energy efficiency of the entire computing-in-memory circuit is improved.

The invention provides a cable defect detection device based on double-path coupling frequency domain reflection, and belongs to the technical field of power cable detection. Comprising a master control module, a double-path coupling signal generator, a first coupler, a second coupler, a first signal comparator and a second signal comparator, the master control module is electrically connected with the double-path coupling signal generator; the input end of the first coupler is connected with the double-path coupling signal generator, the coupling port of the first coupler is connected with a cable to be tested, the output end of the first coupler is connected with the input end of the first signal comparator, and the output end of the first signal comparator is connected with the input end of the second signal comparator; the input end of the second coupler is connected with the double-path coupling signal generator, and the output end of the second coupler is connected with the second signal comparator; the output end of the first signal comparator and the output end of the second signal comparator are both electrically connected with the master control module. According to the invention, the problem of phase ambiguity of single-path measurement is overcome by using a double-path signal comparison structure, and the accuracy and reliability of cable defect detection are remarkably improved.

Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.

The invention provides a display device and a driving chip of a display panel. The display device comprises the display panel and the driving chip. The driving chip comprises a first comparator and a second comparator; the driving chip is used for dividing the output channels corresponding to the at least two data lines into a first channel with positive polarity and a second channel with negative polarity; a first comparator for comparing the first voltage with a first reference voltage to output a first level; the second comparator is used for comparing the second voltage with a second reference voltage and outputting a second level; and the driving chip is also used for continuously monitoring the first level and the second level so as to detect whether a short circuit between the data lines occurs in the display panel or not. The data line is divided into the positive and negative polarity channels through the driving chip, the comparator is used for comparing the channel voltage with the reference voltage, the level change is monitored to detect the short circuit, an amplifier and a complex switch assembly do not need to be additionally arranged, the circuit structure is simplified, and the manufacturing cost is reduced.

A voltage mode weak-PUF circuit with rich challenge-response pairs comprises four decoders, two PUF arrays, a sequential control circuit and a voltage comparator. One-to-two PUF arrays are used to replace existing one-to-one PUF arrays to increase the number of challenge-response pairs by 2N times, from 2N realized by the one-to-one PUF arrays to 2N×2N, wherein N=a+b. Each PUF cell comprises m*n PUF cells and n transmission gates, and adopts a simple common-source amplifier structure formed by a first PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein any one PUF cell in one PUF array can be compared with any one PUF cell in the other PUF array to generate an output response. The number of output responses is 2N, so the proportion of the PUF cells for generating one challenge-response pair is 2N / 2N=1 / 2N, and the reuse rate of the same PUF cell is merely 1 / 2N.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

A control system for an AC-DC converter includes a mixed-signal power controller and first and second gate drivers. The controller has a digital module and an analog module. The analog module has a current sensor generating a current sense voltage based on a sensed switch current. The digital module has a DC voltage sensor generating a DC sense voltage based on a DC bus voltage, and an AC voltage sensor generating an AC sense voltage and a binary polarity signal based on the AC voltage. The digital module induces the first gate driver to output first and second control signals for controlling a high-side switch and a low-side switch of a current shaping half-bridge based on first and second clock signals and the comparator voltage, such that an inductor current flowing through an inductor is proportional to a current command value.

A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

The invention belongs to the field of integrated circuits, and particularly relates to a CIM (common information model) circuit for random computation and an MAC (media access control) operational circuit suitable for machine learning training, and the CIM circuit comprises a storage computation array, a random quantization circuit and a peripheral circuit. Wherein the storage and calculation array adopts an SRAM (Static Random Access Memory) array with data storage and logical operation functions. The random quantization circuit comprises a random voltage generator, a twin comparator array, a random accumulation circuit and a transcoding circuit. The random voltage generator generates a random voltage, the twin comparator array generates a random bit stream of an operation result output by the SRAM array by using the random voltage, and the random accumulation circuit accumulates a product result in a random domain according to each random bit stream; and the transcoding circuit transcodes the random bit stream of the final result into a corresponding numerical value. The invention also introduces a transposition design to realize more efficient full parallel operation. According to the CIM circuit, the problems of low area efficiency and high power consumption of various existing CIM circuits adopting full adders are solved.

A method may include, when in a low-power mode of a power converter, monitoring an output voltage of the power converter; comparing, with a single comparator, the output voltage to a first threshold voltage and cause the power converter to enter a magnetization phase of the low-power mode responsive to the output voltage falling below the first threshold voltage; and during the magnetization phase and a demagnetization phase of the low-power mode, comparing, with the single comparator, the output voltage to a second threshold voltage lower than the first threshold voltage and cause the power converter to enter the high-power mode responsive to the output voltage falling below the second threshold voltage.

The invention relates to the technical field of mode control, and discloses a metro operation dual-mode control method and system based on pulse width modulation coding. The method comprises the following steps: defining an initialization voltage range through a power supply measurement module, and adopting a dual redundancy measurement module to realize manual control and automatic operation channel voltage dual-path calibration; the signal collector collects a real-time current signal, and the signal comparator performs anomaly detection to generate a mode selection control signal; the pulse width modulation encoder calculates a duty ratio parameter and generates a current-limiting pulse width modulation signal; the multiple protectors judge the fault state, and the delay controller adjusts the disconnection time sequence of the relay; the time sequence controller establishes a mode switching rule, and the relay linkage controller optimizes an output state; the data collector extracts operation parameters, and the communication interface completes data electrical isolation transmission. Seamless switching between the manual control mode and the automatic operation mode is achieved through the pulse width modulation coding technology, and the stability and reliability of the system in the mode switching process are ensured.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

The present invention relates to the field of mixed-signal compute-in-memory, and relates to a storage computing unit, comprising a 1-bit multiplication unit, a capacitor, an accumulation bus, and a control line, and further comprising a differential capacitor and a differential accumulation bus. The storage computing unit makes the use of an approximation standard 6T SRAM storage unit possible, thereby improving the energy efficiency, computing area efficiency, and storage density. Further provided are a storage computing array comprising a plurality of storage computing units and a plurality of 1-bit SAR logic units, a storage computing macro module comprising the storage computing array and a plurality of comparators, and a storage computing upper-level macro module comprising the storage computing macro module and a plurality of dynamic comparator clock generating units. According to the storage computing array and corresponding SAR logic units and dynamic comparator clock generating units of the present invention, the wiring is simplified, the interconnection parasitics are reduced, the energy efficiency is improved, and the number of metal layers for interconnection is reduced, thereby reducing costs.

Wireless circuitry is provided that includes a transformer having a primary coil and a secondary coil, a first group of switchable capacitors coupled to a first terminal of the primary coil, a second group of switchable capacitors coupled to a second terminal of the primary coil, and capacitance measurement circuitry selectively coupled to a center tap of the primary coil during a measurement mode. The capacitance measurement circuitry can include a current source, a current sink, a comparator, a voltage generator for providing one or more threshold / reference voltages to the comparator, a frequency measurement circuit, and a capacitance calculation circuit configured to compute a capacitance of the first and second groups of switchable capacitors.

The invention relates to a PCB over-temperature protection device, method and equipment, and relates to the technical field of servers, the device comprises at least one control circuit and a complex programmable logic device CPLD, and the control circuit comprises a thermistor and at least one voltage comparator; the thermistor is arranged in a monitoring area of a printed circuit board (PCB) and is used for converting the temperature of the monitoring area into a target voltage signal; the forward input end of the voltage comparator receives a target voltage signal, the reverse input end of the voltage comparator receives a reference voltage signal corresponding to the voltage comparator, and the voltage comparator is used for outputting a high level when the target voltage signal is higher than the reference voltage signal; the CPLD comprises a plurality of input pins respectively corresponding to the voltage comparators, each input pin is electrically connected with the output end of the corresponding voltage comparator, and the CPLD is used for triggering over-temperature protection operation corresponding to the input pin when the high level is received through the input pin, so that the timeliness of PCB over-temperature protection is improved.

A controller for controlling a multi-phase power conversion system includes a pulse width modulation (PWM) comparator configured to generate a PWM signal based on a ramp signal, a voltage reference signal and a feedback voltage from the power conversion system. A circuit may be configured to generate, based on the PWM signal, PWM signals by delaying the PWM signal with different delay times, and feed the PWM signals to respective switching power converters of the multi-phase power conversion system, to regulate an output voltage of the power conversion system. Each switching power converter may include a control circuit configured to adjust a pulse width of a received PWM signal based on a reference current and an output current of a corresponding switching power converter, to generate an adjusted PWM signal, based on which, an output voltage of the corresponding switching power converter is regulated.