4349 results about "Comparator" patented technology

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention provides a cable defect detection device based on double-path coupling frequency domain reflection, and belongs to the technical field of power cable detection. Comprising a master control module, a double-path coupling signal generator, a first coupler, a second coupler, a first signal comparator and a second signal comparator, the master control module is electrically connected with the double-path coupling signal generator; the input end of the first coupler is connected with the double-path coupling signal generator, the coupling port of the first coupler is connected with a cable to be tested, the output end of the first coupler is connected with the input end of the first signal comparator, and the output end of the first signal comparator is connected with the input end of the second signal comparator; the input end of the second coupler is connected with the double-path coupling signal generator, and the output end of the second coupler is connected with the second signal comparator; the output end of the first signal comparator and the output end of the second signal comparator are both electrically connected with the master control module. According to the invention, the problem of phase ambiguity of single-path measurement is overcome by using a double-path signal comparison structure, and the accuracy and reliability of cable defect detection are remarkably improved.

Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.

The invention provides a display device and a driving chip of a display panel. The display device comprises the display panel and the driving chip. The driving chip comprises a first comparator and a second comparator; the driving chip is used for dividing the output channels corresponding to the at least two data lines into a first channel with positive polarity and a second channel with negative polarity; a first comparator for comparing the first voltage with a first reference voltage to output a first level; the second comparator is used for comparing the second voltage with a second reference voltage and outputting a second level; and the driving chip is also used for continuously monitoring the first level and the second level so as to detect whether a short circuit between the data lines occurs in the display panel or not. The data line is divided into the positive and negative polarity channels through the driving chip, the comparator is used for comparing the channel voltage with the reference voltage, the level change is monitored to detect the short circuit, an amplifier and a complex switch assembly do not need to be additionally arranged, the circuit structure is simplified, and the manufacturing cost is reduced.

A control system for an AC-DC converter includes a mixed-signal power controller and first and second gate drivers. The controller has a digital module and an analog module. The analog module has a current sensor generating a current sense voltage based on a sensed switch current. The digital module has a DC voltage sensor generating a DC sense voltage based on a DC bus voltage, and an AC voltage sensor generating an AC sense voltage and a binary polarity signal based on the AC voltage. The digital module induces the first gate driver to output first and second control signals for controlling a high-side switch and a low-side switch of a current shaping half-bridge based on first and second clock signals and the comparator voltage, such that an inductor current flowing through an inductor is proportional to a current command value.

The invention provides an ultrasonic fingerprint chip and an integral clock generation method and device of the ultrasonic fingerprint chip. Appropriate fingerprint pixel units can be selected from a plurality of fingerprint pixel units to serve as first-class pixel units and second-class pixel units, and the first-class pixel units and the second-class pixel units are respectively connected with a first-class detection circuit and a second-class detection circuit. Wherein a first integrator in the first type of detection circuit is sequentially connected with a first comparator, a time delay regulator, a clock dominant frequency duplicator and a frequency dividing circuit; the frequency dividing circuit is connected with the second type detection circuit; a second integrator in the second type detection circuit is connected with an amplification structure; the amplification structure is also connected with a second comparator; and the second comparator is connected with the time delay regulator in the first-class detection circuit. The circuit can automatically generate and obtain the integral clock signal which is matched with the ultrasonic fingerprint echo signal and is high in precision and good in effect, so that the received ultrasonic fingerprint echo signal is precisely processed, and a target signal with high quality is obtained.

In an example, a level shifter includes a low side having first and second inputs. The level shifter also includes a high side, where the high side has a latch having first and second terminals. The high side also includes a current comparator including first and second current mirrors. The high side includes isolation circuitry including first and second transistors, in which the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

The invention relates to the technical field of hydrogen transportation monitoring, in particular to a real-time monitoring and positioning method and system for hydrogen leakage of a hydrogen transportation trailer, and the method comprises the steps: automatically generating a signal collection request according to a preset real-time monitoring period, and synchronously obtaining a plurality of original sensing signals in real time through a vehicle-mounted sensor array, the method comprises the following steps: respectively preprocessing a plurality of original sensing signals to obtain a plurality of target quantized data, carrying out feature extraction on the plurality of target quantized data to obtain a feature variable set, carrying out fusion decision on the feature variable set by adopting a preset target decision model to generate a fusion decision result, and performing confidence evaluation on the fusion decision result through a probability threshold comparator, generating an early warning signal when a comprehensive score exceeds a dynamic early warning threshold, sending the early warning signal and target sensing data to a remote monitoring platform, and displaying an early warning trigger position and state of the hydrogen transport trailer on the remote monitoring platform. And the hydrogen trailer transportation safety and the emergency treatment efficiency are improved.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

The invention discloses a charge control method and a digital control system based on a dual-active bridge resonant converter, and belongs to the technical field of dual-active bridge resonant converter control. According to the method, a resettable integrating circuit is used for sampling resonance current and converting the resonance current into integrating voltage which is in a linear relation with charge injection quantity, and an integrating capacitor is discharged and reset before each time of injection; superposing the integral voltage and the ramp voltage; comparing the superposed signal with a threshold voltage output by a current loop through a comparator, and when the superposed signal reaches a threshold value, triggering to generate a PWM signal and switching the working mode of the converter; a switching tube is controlled to act according to a PWM signal, a switching time sequence is dynamically adjusted, effective control over transmission power is achieved, and a digital control system for achieving the method is established. According to the method, rapid dynamic response, efficient power transmission and stable operation of the dual-active bridge resonant converter are realized by controlling resonance current integration and a switching time sequence, and the energy conversion efficiency and the system reliability are effectively improved.

The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

The invention provides a system and a method for detecting and preventing early explosion of an electronic detonator chip. The method comprises the following steps: S1, detecting a current charging voltage; s2, selecting a reference voltage, comparing the reference voltage with the current charging voltage, and obtaining a comparison result based on a comparator; and S3, taking an early explosion prevention measure according to a comparison result. According to the invention, the multi-gear reference circuit and the comparator are used, high-precision detection of voltage change of the energy storage capacitor is realized, and the digital control logic circuit is matched to detect that the voltage of the energy storage capacitor drops abnormally and rapidly, so that an early explosion symptom is identified; by arranging the bypass switch, the energy storage capacitor is short-circuited to the ground when an early explosion symptom is recognized, so that energy of the energy storage capacitor is not released through the ignition element, early explosion is prevented, and good practicability is achieved.

The invention discloses an ALU, a processor, a chip, equipment and a texel index calculation method, and belongs to the technical field of chips. The ALU comprises a first comparator, a first divider, a first summator and a texel adjusting unit. A first comparator to determine a first value, the first value being determined based on a smaller value of the integer portion of the input texture coordinate and the maximum offset; the first divider is used for calculating a ratio between the input offset and the first divisor to obtain a first ratio; the first summator is used for calculating the quotient of the first ratio and the sum of the first numerical value and the second numerical value to obtain a first calculation result; and the texel adjusting unit is used for determining a target texel index corresponding to the input texture coordinate according to at least one of the first calculation result and the addressing mode. According to the method, the first calculation result can be determined based on the smaller value in the two, and the value of the integer part of the input texture coordinate can be reduced within a certain limit, so that the bit width of the calculation unit is reduced.

The invention discloses an overcurrent protection control circuit of a low-dropout linear regulator and the low-dropout linear regulator, and relates to the field of voltage regulators. A first sampling module is connected with a drain electrode, a grid electrode and a source electrode of a power control tube in the low-dropout linear regulator and a first current comparator; the first current comparator is further connected with the grid electrode of the first protection switch and the input voltage end of the low dropout linear regulator, the source electrode of the first protection switch is connected with the grid electrode of the power control tube, the drain electrode of the first protection switch is grounded, and the source electrode of the power control tube is connected with the voltage output end of the low dropout linear regulator; the second sampling module is respectively connected with the drain electrode of the power control tube, the grid electrode of the power control tube and the clamping module, the clamping module is connected with the grid electrode of the second protection switch through the second current comparator and is also connected with the source electrode of the power control tube, the drain electrode of the second protection switch is grounded, and the source electrode of the second protection switch is connected with the grid electrode of the power control tube. The reliability of current limiting can be improved.

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

The invention relates to the field of digital power supplies, and particularly provides a method for identifying CCM and DCM modes in a high-power digital power supply, which comprises the following steps: acquiring an inductive current sampling voltage signal and a reference voltage signal, and detecting the level conversion states of the two through a comparator module; if the comparison result accords with a preset error range, recording a DCM mode identifier and calculating an average sampling current value; adjusting an interrupt priority order to match a time sequence characteristic of the capture event, and generating a current state parameter of a mode switching boundary; calculating a correction factor of the average sampling current by combining the overflow times of the counter and rising edge fluctuation frequency data; a duty ratio parameter is updated based on the corrected current value, and a new PWM control signal is generated and output; when the duty ratio deviation exceeds a switching threshold value, dynamically adjusting an interrupt priority parameter and updating a reference value of a counter; and generating a real-time tracking data set of the inductive current zero point according to the final adjustment parameter.

The invention provides an automatic frequency locking circuit based on a time-to-voltage converter and a phase-locked loop, and relates to the technical field of phase-locked loops, a first frequency-halving unit and a second frequency-halving unit respectively carry out frequency-halving processing on a reference signal and a frequency division signal of a current comparison period to obtain a first square wave signal and a second square wave signal; the first square wave signal and the second square wave signal are transmitted to the time-to-voltage converter; the time voltage converter comprises a phase generation unit, a first charge pump and a second charge pump, the phase generation unit generates an enable signal according to the first square wave signal and the second square wave signal, and the first charge pump and the second charge pump respond to control of the enable signal and collect single pulse signals from the first square wave signal and the second square wave signal respectively so as to supply power to the input end of the comparator; the comparator compares power supply voltages of the two input ends to achieve frequency comparison of the reference signal and the frequency division signal. And selection in a plurality of phase signals is not needed, and required digital circuit modules are reduced, so that the delay of the reference signal and the frequency division signal in the conversion process is reduced.

A circuit for slew rate detection and phase control in a multi-phase converter is provided. The circuit includes a first comparator configured to trigger when an output voltage of the multi-phase converter falls to a first output voltage level threshold value. The circuit further includes a second comparator configured to trigger when the output voltage falls to a second output voltage level threshold value which is lower than the first output voltage level threshold value. The circuit further includes a timer configured to start to run for a predefined time window, when the output voltage of the multi-phase converter falls below first output voltage level threshold value. The circuit further includes phase control logic configured to distinguish the ramp rate of the output voltage of the multi-phase converter as corresponding to a slow-rate ramp, a mid-rate ramp or a fast-rate ramp based on the outputs of the first comparator, the second comparator and the timer and enable phases synchronously or asynchronously based on the distinguishing of the ramp rate of the output voltage of the multi-phase converter as corresponding to the mid-rate ramp or the fast-rate ramp.

The present invention provides a DCDC converter using a dual-mode adaptive off-time timer, comprising: a PWM comparator, an on-time timer, a current detection module, an off-time timer logic control circuit, a drive control circuit, a dual-mode adaptive off-time timer, an inductor LOUT, an NMOS transistor MH, an NMOS transistor ML, a resistor RFB2, a resistor RFB1, and a capacitor COUT. The present invention is implemented by means of the PWM comparator, the on-time timer, the current detection module, the off-time timer logic control circuit, the drive control circuit, and the dual-mode adaptive off-time timer. The off-time of the internal dual-mode adaptive off-time timer has the function of adaptively adjusting an input signal and an output feedback signal, and a minimum off-time timer and an overcurrent off-time timer are simultaneously implemented by using one off-time timer.

The invention discloses a parallel constant-voltage digital audio power amplifier and a broadcasting system. Comprising a line input module, a line output module, a first analog-to-digital conversion circuit, a second analog-to-digital conversion circuit, a third analog-to-digital conversion circuit, a digital signal processor, a single-chip microcomputer, a digital-to-analog conversion circuit, an error comparator, a modulator, an integrating circuit, a pulse width modulation input half-bridge output stage, and a first carrier frequency selection and gain adjustment module. A second carrier frequency selection and gain adjustment module, a first LC filter, a high-frequency compensation network, a communication bus and a power switch. The technical problems that an existing multi-channel parallel digital constant-voltage power amplifier is only limited to power amplifier channels in the same power amplifier, the parallel connection mode only uses the first channel as a main power amplifier and only uses the other channels as slave power amplifiers, and certain limitation exists are solved.

The utility model discloses a grounding detection device for an auxiliary circuit of a railway locomotive. The grounding detection device comprises a plurality of loads, an A / D converter, a judging device and a plurality of current detectors, the input end of each current detector is connected with the shell of the corresponding load and is used for acquiring the grounding current leaked from the shell of the load; the input end of the A / D converter is connected with the output end of the current detector, and the A / D converter is used for converting the grounding current into a digital signal from an electric signal; the judger is connected with the output end of the A / D converter and comprises comparators in one-to-one correspondence with the A / D converter, each comparator is internally provided with a threshold value, the comparators are all compared with the corresponding digital signals, when the input digital signals are not larger than the threshold values, the comparators output first signals, and when the input digital signals are larger than the threshold values, the comparators output second signals. And the comparator outputs a second signal so as to simplify the process of ground fault detection and improve the easiness of load detection.

In described examples, an integrated circuit (IC) includes a comparator, a shift calculator, an aligner, a compressor, and an adder. The comparator determines a largest one of multiple exponents. The shift calculator subtract the exponents from the determined largest exponent to provide a set of shift values. The aligner shifts a subset of a set of data values in a least significant bit direction responsive to respective ones of the shift values to generate a first number of aligned data values. The compressor generates a second number of compressed data values responsive to the first number of aligned data values. The second number is less than the first number. An adder sums the compressed data values.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

The invention provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer, the first comparator and the second comparator are respectively configured with different reference voltages, and the input end of the first comparator and the input end of the second comparator are used for receiving voltage signals generated by the same wheel speed sensor; and the signal analyzer is used for analyzing the wheel speed information according to the first comparison signal output by the first comparator and the second comparison signal output by the second comparator. Thus, the input signal is subjected to multi-threshold judgment by using a double-comparator structure, so that sensor signals of different current levels can be identified and analyzed uniformly, and compatible processing of sensor signals of multiple protocols is realized. Therefore, the problem that the overall system cost is increased due to hardware redundancy and system complexity increase in a traditional scheme is avoided, and the universality and the integration capacity of the interface module are effectively improved in a low-cost mode.

Flash analog to digital converters and other types of integrated circuits having multiple comparators may employ calibration methods and firmware to efficiently compensate the various offset voltages of the multiple comparators. One illustrative integrated circuit includes: multiple comparators each configured to provide a comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the multiple comparators including a current comparator and a previous comparator; and a controller configured to perform a search to select a calibration setting for each of the comparators in turn, the controller determining an initial search window for the current comparator based on a calibration setting selected for the previous comparator.

The invention discloses a phase current reconstruction method for high-modulation-ratio three-resistance sampling of a permanent magnet synchronous motor. The phase current reconstruction method comprises the following steps: S1, obtaining a preliminary sampling frame; s2, generating boundary input data; s3, initializing a rule weight parameter set; s4, obtaining a weighted candidate current interval set; s5, performing cross check on the weighted candidate current interval set and the output of the comparator array, eliminating inference branches which do not conform to the polarity and amplitude limit of hardware, obtaining a candidate current interval set subjected to boundary reduction, and fusing the candidate current interval set with a reconstructed three-phase current vector of a previous pulse width modulation period to generate a reconstructed three-phase current vector of a current period; and S6, periodically and circularly executing the steps S1 to S5, and completing real-time closed-loop control of the phase current reconstruction method for high-modulation-ratio three-resistance sampling of the permanent magnet synchronous motor after the error of the reconstructed three-phase current vector is continuously kept to be smaller than a preset value under the high-modulation-ratio driving condition. According to the invention, steady-state fitting in the current estimation process is realized, and abrupt change points are prevented from generating abnormal output.

The invention provides a radon gas detection method and device, electronic equipment and a storage medium. The method comprises the following steps: collecting a plurality of first electric signals from electric signals flowing through a comparator according to a preset time interval in a target time range; in response to the received interrupt signal from the comparator, determining a second electric signal corresponding to the occurrence moment of the interrupt signal from the plurality of first electric signals; determining a first noise value according to the plurality of third electric signals; the first range value is compensated according to the first noise value, a second range value is determined, the first range value is used for representing a signal peak range of particles corresponding to radon in a noise elimination state, and the plurality of third electric signals are signals different from the second electric signals in the plurality of first electric signals; determining a fourth electric signal whose signal peak value satisfies a second range value from the second electric signals; and determining the concentration value of the radon gas according to the number of the fourth electric signals. The accuracy of radon gas concentration detection can be improved.

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.