1096results about "Physical parameters compensation/prevention" patented technology

The invention belongs to the technical field of signal acquisition and processing, and discloses a low-noise biopotential signal acquisition system and a low-noise biopotential signal processing method. An original bioelectricity signal of a human body is collected through an electrode array, and analog-to-digital conversion is carried out after the signal is processed by a multi-stage self-adaptive filtering and amplifying circuit. A digital signal is sequentially subjected to adaptive wavelet transform denoising and empirical mode decomposition to obtain a multi-level intrinsic mode function set, an intrinsic mode function of a characteristic frequency band is extracted from the multi-level intrinsic mode function set, and the signal is reconstructed. Introducing a dual noise reduction mechanism combining adaptive wavelet transform and empirical mode decomposition; a signal quality real-time evaluation system is established, and system parameters including the gain of a variable gain amplifier and the bandwidth of a dynamic band-pass filter are dynamically adjusted through closed-loop feedback. The self-adaptive optimization of the whole biopotential signal acquisition process is realized, various interferences are effectively inhibited, the signal characteristics are reserved, and the signal-to-noise ratio is remarkably improved.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

The invention discloses a high-precision analog domain gain error shaping analog-to-digital converter and an implementation method thereof, and relates to the field of integrated circuit design. The high-precision analog domain gain error shaping analog-to-digital converter adopts a fully differential structure; comprising a first-stage sub analog-to-digital converter, a residual error amplifier and a second-stage sub analog-to-digital converter which are connected in sequence. A first-stage sub analog-to-digital converter is designed into a coarse-fine quantization architecture of an NS SAR ADC and a DAC, an input signal is sampled and quantized through the coarsely quantized NS SAR ADC to generate a first-stage digital code, and then the first-stage digital code is read to the finely quantized DAC. And the finely quantized DAC performs DAC array switching according to the first-stage digital code, and directly obtains the shaped first-stage quantization noise to realize gain error shaping. The method does not need to predict the first-stage quantization noise any more, solves the problem that the truncation error is not matched with the gain, and achieves a better gain error shaping effect.

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention discloses a dynamic sliding window filtering method and device, and a medium. The method comprises the following steps: calculating and updating a sliding window length given value in real time based on a currently collected power grid frequency; comparing the obtained sliding window length given value with the current sliding window length; if the sliding window length given value is equal to the current sliding window length, the current sliding window length is kept unchanged; if the sliding window length given value is larger than the current sliding window length, the sliding window length is gradually increased according to a set mode; if the sliding window length given value is smaller than the current sliding window length, the sliding window length is gradually shortened according to a set mode. The device and the medium are both used for implementing the method. The beneficial effects of the application are that compared with a traditional fixed sliding window length, the technical scheme of the application can adaptively adjust the sliding window length according to the change of the power grid frequency, so that the data acquisition accuracy of the sliding window can be improved, and effective elimination of ripples can be realized.

The invention relates to the technical field of electronic information, and discloses a multichannel sampling interference suppression method based on a single-chip microcomputer ADC, and the method comprises the following steps: dynamic sequence generation: generating different channel sampling sequences for each sampling period, and enabling the adjacent probabilities of any two channels in a time sequence to be equal; data acquisition: sequentially executing each round of sampling, and recording the sampling value of each channel in each round; and error spreading: carrying out statistical processing on sampling values obtained by multi-round sampling of each channel, and outputting a final sampling value after interference suppression. According to the method, active suppression of adjacent channel interference is realized through dynamic sequence generation, data acquisition and error sharing, the insertion of a dependent reference channel is avoided, the scanning efficiency of ADC multi-channel sampling and the dynamic scene adaptability are improved, a high-precision sampling value is finally output, and the requirements of single-chip microcomputer multi-channel ADC application are met.

In general, according to one embodiment, a semiconductor integrated circuit includes the following configuration. A first converter samples a first digital value from an analog signal based on a first clock signal. A second converter samples a second digital value from the analog signal based on a second clock signal differing from the first clock signal by a first phase. A first processing circuit calculates phase shifts of the first and second clock signals based on the first and second digital values and using a first frequency of a third clock signal. A second processing circuit generates a control signal for correcting the phase shifts of the first and second clock signals based on the phase shifts calculated by the first processing circuit and using a second frequency of a fourth clock signal. The second frequency is 2m times the first frequency.

The invention discloses a grid voltage bootstrapped switch circuit with compensation and an ADC, and belongs to the technical field of integrated circuits. The circuit comprises a compensation charge pump circuit and a grid voltage bootstrapped switch circuit. A charge pump branch power supply end in the grid voltage bootstrap switch circuit is connected to an output compensation voltage end of the compensation charge pump circuit; when the input clock signal CLK1 is low and the input clock signal CLK2 is high in level, the power supply end of the charge pump branch is switched off, and the capacitor in the charge pump circuit is compensated for charging; when the level of the CLK1 is high and the level of the CLK2 is low, the power supply end of the charge pump branch is switched on, a bootstrap capacitor in the grid voltage bootstrap switch circuit is charged, and the Vboost provides compensation voltage. The compensation charge pump circuit provides higher power supply voltage for the grid voltage bootstrap switch, grid voltage drop of the sampling switch tube caused by parasitic capacitance at the positive end of the bootstrap capacitor can be compensated back, input parasitic capacitance is reduced, on-resistance of the sampling switch tube is reduced, and sampling linearity is improved.

An error correction method for a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter (SAR ADC) are disclosed, which relate to integrated circuit technology. The successive approximation register analog-to-digital converter error correction method includes the following steps: a. detecting whether a comparator completes a data comparison within a specified time; if so, performing step b; if not, performing step c; b. after the comparator outputs data, starting a next data comparison cycle, and returning to step a; and c. interrupting the conversion, waiting for a signal to start a next conversion, starting the next data comparison cycle, and returning to step a. The method and SAR ADC can effectively prevent problems relating to (1) slow comparator speed caused by dead voltage and (2) burr interference.

A switched-element digital-to-analog converter (DAC) circuit for use, for example, in a successive-approximation register, SAR, analog-to-digital converter, ADC. The DAC circuit comprises a pool of unary circuit elements (410), each having a common nominal weighting value, and switching (420) and multiplexer (430) arrangements configured so that each unary circuit element (410) in the pool can be independently associated with any one of two or more bits of the switched-element DAC.

A circuit for detecting metastability in an asynchronous successive approximation register analog-to-digital converter; wherein the dual output comparator is arranged to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and drive one of the first comparison signal and the second comparison signal to a set state based on the comparison. When the first comparison signal is in the set state, the first output end is in the set state. When the second comparison signal is in the set state, the second output end is in the set state. If a predetermined duration elapses after the dual output comparator starts comparison, and if both the first comparison signal and the second comparison signal are in a reset state, the control logic outputs a set state at both the first output and the second output. This allows the metastability of the comparator to be detected in the asynchronous SAR ADC. The control logic may effectively terminate the comparison if a predetermined duration is reached. In other words, the control logic may overwrite the comparator output to provide a defined output indicative of metastability.

The invention discloses a broadband sampling system and method based on non-frequency-conversion frequency interleaving, and the method comprises the steps: transmitting an input analog signal to a non-frequency-conversion frequency interleaving collection system, and dividing the input signal into a plurality of sub-band signals according to the frequency through a plurality of analog decomposition filters which are configured in parallel; according to the method, each path of sub-band signal is sampled and quantized through an independent ADC (Analog to Digital Converter), then the quantized digital signal is sent to an interpolator, the sampling rate is increased to a unified sampling rate through interpolation processing, overlapping band correction is carried out to eliminate interference between sub-bands, finally data splicing is completed, and high-fidelity reconstruction of an original broadband signal is realized.

The invention relates to the technical field of amplifiers, and discloses an analog-to-digital converter combination instrument amplifier which comprises a first-stage amplifier, the first-stage amplifier is in signal connection with a second-stage amplifier, the second-stage amplifier is in signal connection with a front-end low-pass filter (LPF), the front-end low-pass filter (LPF) is in signal connection with an analog-to-digital converter (ADC), and the analog-to-digital converter (ADC) is in signal connection with the analog-to-digital converter. And an unbalanced input-to-balanced differential circuit output module is arranged between the second-stage amplifier signal and a front-end low-pass filter (LPF). From the perspective of signal processing and conversion, a precise signal transition bridge is constructed by adding an unbalanced input-to-balanced differential circuit output module, unbalanced signals output by a second-stage amplifier are converted into double-end balanced differential signals, common-mode noise interference is effectively resisted through a differential transmission mode, the signal purity is guaranteed, and the signal quality is improved. The front-end low-pass filter and the analog-to-digital converter are adaptive to differential signals, so that the signal transmission is stable and anti-interference, and the analog-to-digital conversion is more accurate.

The invention provides a digital-to-analog converter which comprises a first reference voltage node, a second reference voltage node, a plurality of change-over switches, a plurality of resistor units and a plurality of capacitor units, the resistor units and the capacitor units are sequentially connected in series to form a series circuit, and the plurality of change-over switches respectively receive multi-digit digital code values in digital signals and output first reference voltage or second reference voltage. And finally, an analog voltage signal is output through an output node of the digital-to-analog converter to realize digital-to-analog conversion, and meanwhile, capacitors in the capacitor units are connected in parallel between the two corresponding resistor network nodes and carry out rapid charging and discharging on the two resistor network nodes, so that the voltage switching efficiency of the resistor network nodes is improved, and the reliability of the digital-to-analog converter is improved. The delay in the digital signal transmission process is reduced, so that the purpose of reducing burrs is achieved, the digital-to-analog converter does not need to be additionally provided with a preprocessing module and a filter, the design cost is reduced, and the conversion efficiency is improved.

The invention provides a high-precision low-delay successive approximation analog-to-digital converter based on sampling noise elimination, and the analog-to-digital converter comprises a main capacitor group which generates an original combined signal according to an original sampling signal and primary sampling noise in a secondary sampling stage; the pre-quantization capacitor bank is used for driving a bottom plate switch of the pre-quantization capacitor bank according to the detection control signal, switching a capacitor weight through a weight control signal to execute pre-quantization operation on the original combined signal and outputting a swing suppression signal; the novel sampling noise elimination module is used for receiving the swing suppression signal, performing gain amplification, generating a purification amplification signal, detecting the differential swing of the original combined signal in real time, and generating a detection control signal and a pre-quantization code according to the differential swing; the successive approximation quantization module is used for generating a main quantization code and a weight control signal according to the purification and amplification signal in a quantization stage; and the digital processing module is used for fusing the pre-quantized code and the main quantized code to obtain a final digital code. And the energy efficiency and the conversion precision of analog signal conversion are obviously improved.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an apparatus is provided for adaptive signal conditioning for biopotential acquisition. The apparatus includes an analog circuit configured to amplify biopotential signals, and a mixed-signal circuit (e.g., which can include an adaptive digital algorithm) coupled to the analog circuit and configured to suppress aggressor signals such as baseline wandering signals and power-line-induced noise in the biopotential signals before amplification of the biopotential signals.

The invention discloses a high-precision voltage and current characteristic quantity extraction and anti-interference sampling circuit compensation method, and belongs to the technical field of voltage and current sampling, and the method comprises the steps: employing a 24-bit ADC to collect voltage and current signals at the sampling frequency of 1 kHz to 10 kHz; electromagnetic interference is inhibited through the metal shielding cover and the wave absorbing material; dynamically correcting the sampling data through a temperature compensation model; dynamically correcting the sampling data based on an LMS algorithm; voltage and current effective values are calculated through a root mean square algorithm in a sliding window mode, a processing result is output in real time, and the problems that existing sampling precision is low and the error compensation effect is limited are solved.

The invention discloses a high-precision feed-forward noise shaping successive approximation analog-to-digital converter. The analog-to-digital converter comprises a first CDAC module, a second CDAC module, a first feed-forward capacitor, a second feed-forward capacitor, a first integrating capacitor, a second integrating capacitor, a first elimination capacitor, a second elimination capacitor, a dynamic amplifier module and a dynamic comparator module. By adopting the technical scheme of the invention, the sampling noise which cannot be optimized by noise shaping is suppressed, and a better precision effect is generated.

A method is disclosed for programming analog-valued weights in a non-volatile memory array using feedback-based estimation and adaptive pulse modulation. The method includes initializing a target weight, applying one or more programming pulses to a memory cell, estimating a weight state of the memory cell based on analog-to-digital conversion, determining a residual error between the estimated weight state and the target weight, and computing a subsequent programming pulse based on the residual error. The subsequent pulse may be adjusted by selecting a programming voltage from a quantized set of levels responsive to the recent weight response dynamics. The programming process may iterate until convergence may be achieved within a defined threshold. The technique supports precise control of conductance programming using closed-loop feedback and may be compatible with pulse-width, amplitude, and polarity modulation schemes.

Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.

The invention relates to the technical field of broadband signal synthesis and high-speed digital-to-analog conversion, in particular to an oversampling-based real-time frequency interleaving digital-to-analog conversion system aliasing suppression method and system, and aims to solve the problem of spectrum aliasing caused by non-ideal characteristics of a digital sub-band decomposition filter and an analog filter under a real-time architecture of the system. In the invention, the sub-band decomposition is completed by adopting the linear phase complementary filter bank, so that distortion introduced by a transition band of a digital filter is avoided; by restraining system parameters such as passband and stopband frequencies and local oscillation frequency of a sub-band decomposition filter, a protection band is set by an oversampling mechanism, a frequency margin is reserved for a transition band of the filter, and aliasing components are suppressed. According to the method, extraction aliasing of a digital domain and mirror image aliasing of an analog domain are avoided at the same time from the system architecture, the frequency spectrum purity of output signals is improved, the method is suitable for a real-time system for processing continuous data streams, and technical support is provided for achieving a high-performance broadband signal source.

An analog signal generation device according to the present invention includes a DA converter that adjusts a signal level of a digital signal according to a DAC correction amount and then converts the digital signal into an analog signal, a detector that detects the analog signal and outputs a detection signal, a storage unit that stores a characteristic equation for calculating the DAC correction amount, and a control unit, in which in a case where the differential voltage when the digital signal having a signal level of a predetermined value is input to the DA converter is larger than a threshold value, the control unit calculates a new DAC correction amount based on the differential voltage by using the characteristic equation, and in a case where the differential voltage does not fall within the threshold value, the control unit corrects the characteristic equation.

A time-interleaved ADC mismatch correction method and time-interleaved ADC relating to the technical field of integrated circuits are disclosed. The time-interleaved ADC mismatch correction method and time-interleaved ADC solve problems with high-order filter modules and signal overflow or saturation risks. The applied technical scheme uses time-interleaved ADC output signal(s) and a fitted signal to calculate a set of filtering coefficients, and uses this set of filtering coefficients to correct the ADC output signal in real time. The applied technical scheme compensates for differences in the frequency response of each channel, rather than the frequency response itself, and the filter order is smaller, the implementation is simpler, and the circuit design complexity and device cost are greatly reduced. The technical solution has a wide range of adaptability, can correct and improve broadband interleaving performance, and avoids the signal overflow / saturation risk because the compensation range is small.

The invention discloses an attenuation compensation method and system for a signal transmission function in an analog-to-digital converter, and relates to the technical field of analog-to-digital converter circuit design and signal processing, and the method comprises the steps: setting the attenuation gain of an integrator, and carrying out the pre-attenuation processing of an analog signal in an analog domain of the integrator; performing analog-to-digital conversion on the pre-attenuated signal through a quantizer, and outputting a digital code stream; and performing gain compensation on the digital code stream in the digital domain, and constructing a digital domain recovery path corresponding to the analog domain attenuation parameter. Through the analog front end of the sigma-delta analog-to-digital converter, overload distortion, modulator instability or modulation out-of-control caused by the fact that a signal peak value exceeds a dynamic range of a quantizer is avoided, the system stability is improved, high-precision analog-to-digital conversion of a controlled amplitude signal is realized, a corresponding gain compensation factor is set according to an analog domain attenuation parameter, and the gain compensation precision is improved. Linear recovery processing of a low-amplitude digital signal is realized, and attenuation introduced by an analog domain is compensated.