628results about "Physical parameters compensation/prevention" patented technology

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention discloses a dynamic sliding window filtering method and device, and a medium. The method comprises the following steps: calculating and updating a sliding window length given value in real time based on a currently collected power grid frequency; comparing the obtained sliding window length given value with the current sliding window length; if the sliding window length given value is equal to the current sliding window length, the current sliding window length is kept unchanged; if the sliding window length given value is larger than the current sliding window length, the sliding window length is gradually increased according to a set mode; if the sliding window length given value is smaller than the current sliding window length, the sliding window length is gradually shortened according to a set mode. The device and the medium are both used for implementing the method. The beneficial effects of the application are that compared with a traditional fixed sliding window length, the technical scheme of the application can adaptively adjust the sliding window length according to the change of the power grid frequency, so that the data acquisition accuracy of the sliding window can be improved, and effective elimination of ripples can be realized.

An error correction method for a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter (SAR ADC) are disclosed, which relate to integrated circuit technology. The successive approximation register analog-to-digital converter error correction method includes the following steps: a. detecting whether a comparator completes a data comparison within a specified time; if so, performing step b; if not, performing step c; b. after the comparator outputs data, starting a next data comparison cycle, and returning to step a; and c. interrupting the conversion, waiting for a signal to start a next conversion, starting the next data comparison cycle, and returning to step a. The method and SAR ADC can effectively prevent problems relating to (1) slow comparator speed caused by dead voltage and (2) burr interference.

The invention relates to the technical field of amplifiers, and discloses an analog-to-digital converter combination instrument amplifier which comprises a first-stage amplifier, the first-stage amplifier is in signal connection with a second-stage amplifier, the second-stage amplifier is in signal connection with a front-end low-pass filter (LPF), the front-end low-pass filter (LPF) is in signal connection with an analog-to-digital converter (ADC), and the analog-to-digital converter (ADC) is in signal connection with the analog-to-digital converter. And an unbalanced input-to-balanced differential circuit output module is arranged between the second-stage amplifier signal and a front-end low-pass filter (LPF). From the perspective of signal processing and conversion, a precise signal transition bridge is constructed by adding an unbalanced input-to-balanced differential circuit output module, unbalanced signals output by a second-stage amplifier are converted into double-end balanced differential signals, common-mode noise interference is effectively resisted through a differential transmission mode, the signal purity is guaranteed, and the signal quality is improved. The front-end low-pass filter and the analog-to-digital converter are adaptive to differential signals, so that the signal transmission is stable and anti-interference, and the analog-to-digital conversion is more accurate.

The invention provides a digital-to-analog converter which comprises a first reference voltage node, a second reference voltage node, a plurality of change-over switches, a plurality of resistor units and a plurality of capacitor units, the resistor units and the capacitor units are sequentially connected in series to form a series circuit, and the plurality of change-over switches respectively receive multi-digit digital code values in digital signals and output first reference voltage or second reference voltage. And finally, an analog voltage signal is output through an output node of the digital-to-analog converter to realize digital-to-analog conversion, and meanwhile, capacitors in the capacitor units are connected in parallel between the two corresponding resistor network nodes and carry out rapid charging and discharging on the two resistor network nodes, so that the voltage switching efficiency of the resistor network nodes is improved, and the reliability of the digital-to-analog converter is improved. The delay in the digital signal transmission process is reduced, so that the purpose of reducing burrs is achieved, the digital-to-analog converter does not need to be additionally provided with a preprocessing module and a filter, the design cost is reduced, and the conversion efficiency is improved.

The invention provides a high-precision low-delay successive approximation analog-to-digital converter based on sampling noise elimination, and the analog-to-digital converter comprises a main capacitor group which generates an original combined signal according to an original sampling signal and primary sampling noise in a secondary sampling stage; the pre-quantization capacitor bank is used for driving a bottom plate switch of the pre-quantization capacitor bank according to the detection control signal, switching a capacitor weight through a weight control signal to execute pre-quantization operation on the original combined signal and outputting a swing suppression signal; the novel sampling noise elimination module is used for receiving the swing suppression signal, performing gain amplification, generating a purification amplification signal, detecting the differential swing of the original combined signal in real time, and generating a detection control signal and a pre-quantization code according to the differential swing; the successive approximation quantization module is used for generating a main quantization code and a weight control signal according to the purification and amplification signal in a quantization stage; and the digital processing module is used for fusing the pre-quantized code and the main quantized code to obtain a final digital code. And the energy efficiency and the conversion precision of analog signal conversion are obviously improved.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an apparatus is provided for adaptive signal conditioning for biopotential acquisition. The apparatus includes an analog circuit configured to amplify biopotential signals, and a mixed-signal circuit (e.g., which can include an adaptive digital algorithm) coupled to the analog circuit and configured to suppress aggressor signals such as baseline wandering signals and power-line-induced noise in the biopotential signals before amplification of the biopotential signals.

A method is disclosed for programming analog-valued weights in a non-volatile memory array using feedback-based estimation and adaptive pulse modulation. The method includes initializing a target weight, applying one or more programming pulses to a memory cell, estimating a weight state of the memory cell based on analog-to-digital conversion, determining a residual error between the estimated weight state and the target weight, and computing a subsequent programming pulse based on the residual error. The subsequent pulse may be adjusted by selecting a programming voltage from a quantized set of levels responsive to the recent weight response dynamics. The programming process may iterate until convergence may be achieved within a defined threshold. The technique supports precise control of conductance programming using closed-loop feedback and may be compatible with pulse-width, amplitude, and polarity modulation schemes.

Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.

The invention relates to the technical field of broadband signal synthesis and high-speed digital-to-analog conversion, in particular to an oversampling-based real-time frequency interleaving digital-to-analog conversion system aliasing suppression method and system, and aims to solve the problem of spectrum aliasing caused by non-ideal characteristics of a digital sub-band decomposition filter and an analog filter under a real-time architecture of the system. In the invention, the sub-band decomposition is completed by adopting the linear phase complementary filter bank, so that distortion introduced by a transition band of a digital filter is avoided; by restraining system parameters such as passband and stopband frequencies and local oscillation frequency of a sub-band decomposition filter, a protection band is set by an oversampling mechanism, a frequency margin is reserved for a transition band of the filter, and aliasing components are suppressed. According to the method, extraction aliasing of a digital domain and mirror image aliasing of an analog domain are avoided at the same time from the system architecture, the frequency spectrum purity of output signals is improved, the method is suitable for a real-time system for processing continuous data streams, and technical support is provided for achieving a high-performance broadband signal source.

The invention discloses an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter, and relates to the field of electric energy metering chips, the electric meter sampling filter chip comprises a programmable anti-aliasing filter module, a digital control and interface module and a cooperative control unit, through binary weighted control of a switched capacitor array, the cut-off frequency can be dynamically adjusted within the range of 1 kHz to 100 kHz, and the cut-off frequency can be adjusted within the range of 1 kHz to 100 kHz. Switching of a Bessel mode, a Butterworth mode and a Chebyshev mode is physically achieved by reconstructing a feedback network, a programmable AAF, an ADC, control logic and a digital interface are integrated into a single chip, and the number of external elements such as an RC network and an operational amplifier is reduced; aDC sampling data is analyzed through FFT, the signal-to-noise ratio is calculated in real time, the filter mode is automatically switched, a hardware interrupt pin triggers notification after configuration is completed, MCU polling is replaced, and frequency response is ensured to be accurate and controllable through laser trimming of a switched capacitor array.

The invention relates to the technical field of signal acquisition, in particular to a multi-channel signal synchronous acquisition method and system based on an FPGA, and the method comprises the steps: obtaining a multi-channel signal source, connecting a device, and outputting an original analog signal; performing frequency equalization and noise suppression preprocessing on the signal; sampling and correcting a time domain and a frequency domain by using a synchronous acquisition model and an analog-to-digital converter to obtain a corrected digital signal; the storage efficiency is optimized through labeling, block compression and high-speed caching, finally, the data is written into a persistent storage module, and data analysis processing is completed based on a remote instruction. Through time reference adaptive calibration, a distributed clock architecture and a dynamic data flow management strategy, the robustness, expansibility and transmission efficiency of signal acquisition are improved, and the real-time performance and reliability requirements in a complex industrial environment are met.

The invention relates to the field of high-speed serial interface chips, and discloses an error calibration method of an ultra-high-speed phase interpolator. The method comprises the steps of amplitude calibration, edge searching, reference clock delay calibration, multi-phase cyclic calibration, linear interpolation and the like, a reference clock rising edge zero crossing point is used as a high-precision time reference, delay control words of a selected discrete phase are adjusted one by one, a mapping lookup table covering a full-phase range is generated through linear interpolation, and the time delay control words of the selected discrete phase are adjusted one by one. And compensation of the nonlinear error of the phase interpolator is realized. According to the invention, high-precision linearity calibration can be completed before normal operation of the chip, the clock recovery precision is significantly improved, the nonlinear error is reduced from + / -1.5 LSB to + / -0.5 LSB, the error rate of the system is reduced, and the power consumption and the area overhead are low.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Various techniques are described for correcting distortion in an analog input signal after digitization in a receiver signal chain. The techniques include a system that stores concatenated distortion correction terms, allowing for efficient data handling and processing. The techniques further include a system that has a smaller number of replica memories compared to primary memories, which store operational data. The replica memories are updated with new data and may be swapped with primary memories to update them without interrupting system operations. The techniques further include a dither system that uses two memories to store and process the dithered signals, which are then combined to produce a noise-corrected digital output. The techniques further include a system to correct distortions in analog input signals processed through multiple parallel paths.

The invention relates to an audio decoding output stage circuit and audio equipment, the audio decoding output stage circuit comprises an I / V conversion module and a low-pass filtering module, and the I / V conversion module comprises a conversion circuit, a crossed diamond amplification circuit, an overcurrent protection circuit and a Roche network circuit; the conversion circuit comprises a JFET (Junction Field Effect Transistor) audio operational amplifier chip and an I / V (Input / Output) conversion resistor and is used for converting an input current into an analog voltage signal; the crossed diamond amplifying circuit can reduce the input offset voltage; the over-current protection circuit can carry out over-current protection; the rowbell network circuit can prevent high-frequency self-oscillation of the power output stage; and the low-pass filtering module comprises a filtering circuit and an ultrahigh frequency filtering circuit arranged at the output end of the audio decoding output stage circuit. The scheme can bring high-performance sound performance, and has the advantages of lower distortion, higher conversion rate, low output impedance and large pushing current.

A signal folding device receives an input signal, and performs frequency modulation on a plurality of first analog signals based on the input signal to obtain a plurality of modulated first analog signals, where a frequency difference between two adjacent first analog signals in the plurality of modulated first analog signals is the same. The signal folding device may filter the plurality of modulated first analog signals based on a specified bandwidth to obtain a second analog signal, and demodulate the second analog signal to obtain an output signal. The output signal is a folded signal of the input signal within a target amplitude, and the second analog signal is an analog signal within the bandwidth.

Systems and methods for providing multiple stable reference voltages are disclosed. In one aspect, a bandgap reference circuit generates a first reference voltage, which is calibrated with an adjustable resistor bank. Settings for this adjustable resistor bank may be stored in a memory and reused at multiple locations with theoretically identical resistor banks for other circuits requiring reference voltages. Recognizing that there may be voltage network variations induced by distances from bandgap reference circuit, process variations between resistor banks, or the like, each resistor bank may be separately calibrated, and settings stored in memory. By providing separate resistor banks for each location that needs a reference voltage, the need for duplicative and space intensive bandgap reference circuits is minimized. Further, by providing separate resistor banks, variations in the local voltage are minimized providing more stable and reliable operation of circuits in the die.

The invention relates to a model training method and device and a signal conversion method. The model training method comprises the following steps: inputting an original digital signal sent by a digital signal source into an initial model to obtain a sample digital signal output by the initial model; performing digital-to-analog conversion on the sample digital signal through a digital-to-analog conversion circuit in the signal processing chip to obtain a sample analog signal corresponding to the sample digital signal; determining a predicted value of a nonlinear distortion index of the digital-to-analog conversion circuit according to the sample digital signal and the sample analog signal; wherein the nonlinear distortion index comprises a total harmonic distortion index and / or an intermodulation distortion index; and performing parameter adjustment on the initial model according to the predicted value and the expected value of the nonlinear distortion index to obtain a digital signal conversion model. The digital signal conversion model obtained through training of the method can process original digital signals so as to compensate nonlinear distortion of a digital-to-analog conversion circuit.

An imaging circuit arrangement is provided, comprising a column of image pixels coupled to a pixel output line, a first data converter circuit with an input coupled to the pixel output line and configured to output a first bit set, an integrator with an input coupled to the first data converter, and a second data converter circuit with an input coupled to the integrator and configured to output a second bit set. The first data converter circuit can be an analog-to-digital converter with a successive approximation register. The integrator can include an amplifier for charging an integrating capacitor. The second bit set can be scaled based on a calibrated value before being combined with the first bit set.

A signal processing circuit for a measurement instrument is described. The signal processing circuit comprises a measurement input, a first measurement channel, a second measurement channel, and a noise canceling circuit. The first measurement channel comprises a first wideband analog-to-digital converter (ADC) and a first transformation circuit. An output signal of the first measurement channel is a first frequency domain signal. An output signal of the second measurement channel is a second frequency domain signal. The first frequency domain signal and the second frequency domain signal are a complex-valued signal, respectively. The noise canceling circuit is configured to receive the first frequency domain signal and the second frequency domain signal and to determine a combined average of the first frequency domain signal and of the second frequency domain signal over a predetermined number of frequency bins, thereby obtaining a complex-valued average signal. Further, a measurement system is described.

Aspects of the subject disclosure may include, for example, first and second operational amplifiers; and a differential pair of NPN transistors in a feedback path of the TLA configured to convert an input current signal into an output voltage signal, where a first emitter of a first NPN transistor of the pair of NPN transistors is connected to an inverting input of the first operational amplifier, and where a second emitter of a second NPN transistor of the pair of NPN transistors is connected to a non-inverting input of the second operational amplifier. Other embodiments are disclosed.

The invention relates to an electronic circuit and a method for suppressing offset variations in a buffer.

The application provides a new hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a dynamic working closed-loop cascode FIA as a residual amplifier to reduce power consumption by eliminating the static current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through the nested second-order CIFF and second-order EF noise shaping loops to achieve high precision in noise shaping at the same oversampling rate, and integrates the sampling noise cancellation (SNC) method to reduce the capacitance of the sampling capacitor to save chip area; the architecture adopts a closed-loop cascode FIA as a residual amplifier and CIFF and EF as noise shaping loops to solve the problem that the traditional noise shaping SAR ADC is difficult to simultaneously achieve high precision and low power consumption. In addition, the sampling KT / C noise cancellation (SNC) technology is integrated to reduce the capacitance of the sampling capacitor and save chip area.

The invention relates to the technical field of sequential control, and discloses a sequential logic control circuit for a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter), which comprises an analog signal acquisition circuit for receiving and preprocessing an initial input signal; the noise shaping circuit is used for performing frequency spectrum shaping on quantization noise in the analog signal and generating the analog signal subjected to noise shaping; the successive approximation type analog-to-digital converter is used for performing bit-by-bit comparison with the analog signal subjected to noise shaping and gradually completing conversion from the analog signal to the digital signal from the highest bit to the lowest bit; and the clock control circuit is used for coordinating sequential logic among the analog signal acquisition circuit, the noise shaping circuit and the successive approximation type analog-to-digital converter. According to the method, frequency spectrum remodeling is carried out on the quantization noise in the signal, the signal-to-noise ratio of the signal is remarkably improved on the premise that the hardware complexity is not additionally increased, and then interference of the noise on follow-up analog-to-digital conversion is reduced.

In an embodiment, an apparatus (112) includes: a transmitting data path configured to transmit an outgoing data packet; and a receiving data path configured to receive an incoming data packet; a controller (212) configured to determine timing information of the incoming data packet; and dithering circuitry (116) configured to dither a reference signal according to the timing information to vary a frequency of the signal over time to generate a dithered recovered signal.

A kind of analog-digital converter is disclosed.The analog-digital converter includes: comparator, is configured to: input signal is compared with reference signal, and output comparison signal indicating corresponding comparison result;Control logic is configured to output control signal for adjusting reference signal based on comparison signal;And reference signal adjusting circuit is configured to adjust reference signal based on control signal.Comparator includes: first preamplifier, is configured to: using first transistor with first size, the difference between input signal and reference signal is amplified;Second preamplifier, is configured to: using second transistor with second size different from first size, the difference between input signal and reference signal is amplified;And latch, is configured to: using at least one of the output of first preamplifier and the output of second preamplifier, comparison signal is generated.First preamplifier and second preamplifier share latch.