1463results about "Physical parameters compensation/prevention" patented technology

The invention relates to an anti-electromagnetic interference intelligent cooling fan system based on dynamic filter circuit design. The system comprises a dual analysis module used for performing time domain and frequency domain dual analysis on a rotating speed feedback signal of a double-ball fan to obtain a multi-dimensional electromagnetic interference characteristic model, and configuring filter network parameters to obtain a target three-stage cascade dynamic filter network; the signal purification module is used for collecting first fan operation parameters and inputting the first fan operation parameters into a target three-stage cascade dynamic filter network for signal purification to obtain filtered Hall sensor signals and filtered power supply signals; the closed-loop control calculation module is used for performing closed-loop control calculation to obtain a non-linear PWM duty ratio control quantity and a phase distribution parameter; and the phase difference control module is used for carrying out phase difference control to obtain a multi-fan cooperative control strategy. According to the invention, high-precision control and anti-interference capability in a wide rotating speed range are realized, and the problem of mutual influence of electromagnetic interference when multiple fans are connected in parallel is solved.

The invention belongs to the technical field of signal acquisition and processing, and discloses a low-noise biopotential signal acquisition system and a low-noise biopotential signal processing method. An original bioelectricity signal of a human body is collected through an electrode array, and analog-to-digital conversion is carried out after the signal is processed by a multi-stage self-adaptive filtering and amplifying circuit. A digital signal is sequentially subjected to adaptive wavelet transform denoising and empirical mode decomposition to obtain a multi-level intrinsic mode function set, an intrinsic mode function of a characteristic frequency band is extracted from the multi-level intrinsic mode function set, and the signal is reconstructed. Introducing a dual noise reduction mechanism combining adaptive wavelet transform and empirical mode decomposition; a signal quality real-time evaluation system is established, and system parameters including the gain of a variable gain amplifier and the bandwidth of a dynamic band-pass filter are dynamically adjusted through closed-loop feedback. The self-adaptive optimization of the whole biopotential signal acquisition process is realized, various interferences are effectively inhibited, the signal characteristics are reserved, and the signal-to-noise ratio is remarkably improved.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

Method and apparatus for skew error measurement and correction in a digital-to-analog converter (DAC) using a time-to-digital converter (TDC). A DAC includes a main DAC and a TDC. The main DAC includes a plurality of DAC cells. The main DAC is configured to generate an analog output signal based on digital input data. The TDC is coupled to an output of the main DAC and configured to measure a timing error of the main DAC. The timing error may be measured on a DAC cell basis or a subset of DAC cells basis.

A signal processing circuit for a measurement instrument is described. The signal processing circuit comprises a measurement input, a first measurement channel, a second measurement channel, and a noise canceling circuit. The first measurement channel comprises a first wideband analog-to-digital converter (ADC) and a first transformation circuit. An output signal of the first measurement channel is a first frequency domain signal. An output signal of the second measurement channel is a second frequency domain signal. The first frequency domain signal and the second frequency domain signal are a complex-valued signal, respectively. The noise canceling circuit is configured to receive the first frequency domain signal and the second frequency domain signal and to determine a combined average of the first frequency domain signal and of the second frequency domain signal over a predetermined number of frequency bins, thereby obtaining a complex-valued average signal. Further, a measurement system is described.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

The invention provides a continuous time pipeline analog-to-digital converter based on a multipath interleaving time domain. The continuous time pipeline analog-to-digital converter comprises a continuous time level ADC, a time domain ADC and a digital reconfigurable filter, the continuous time-stage ADC performs high-order quantization on an input signal and then outputs the input signal to the digital reconfigurable filter, and performs filtering processing on a residual signal in the input signal and then outputs the residual signal to the time-domain ADC; the time domain ADC is used for quantizing the residual signals passing through the continuous time level ADC and then outputting the quantized residual signals to the digital reconfigurable filter; and the digital reconfigurable filter is used for carrying out digital filtering on the quantization result of the continuous time level ADC and carrying out data reconstruction on the quantization code value output by the time domain ADC. The architecture not only retains the characteristics of ultrahigh energy efficiency and digitization of a time domain ADC, but also benefits from the continuous time ADC architecture, and the resistive input impedance and the inherent anti-aliasing filtering effect of the continuous time ADC architecture are beneficial to the realization of a high-speed ADC in a completely integrated wireless receiver.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

The invention discloses a high-precision analog domain gain error shaping analog-to-digital converter and an implementation method thereof, and relates to the field of integrated circuit design. The high-precision analog domain gain error shaping analog-to-digital converter adopts a fully differential structure; comprising a first-stage sub analog-to-digital converter, a residual error amplifier and a second-stage sub analog-to-digital converter which are connected in sequence. A first-stage sub analog-to-digital converter is designed into a coarse-fine quantization architecture of an NS SAR ADC and a DAC, an input signal is sampled and quantized through the coarsely quantized NS SAR ADC to generate a first-stage digital code, and then the first-stage digital code is read to the finely quantized DAC. And the finely quantized DAC performs DAC array switching according to the first-stage digital code, and directly obtains the shaped first-stage quantization noise to realize gain error shaping. The method does not need to predict the first-stage quantization noise any more, solves the problem that the truncation error is not matched with the gain, and achieves a better gain error shaping effect.

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

The invention discloses a digital-to-analog converter chip which comprises an analog power supply for supplying power to an analog power supply domain, a digital power supply for supplying power to a digital power supply domain and a clock power supply for supplying power to a clock power supply domain, the digital power supply domain comprises a first linear voltage regulator, and the clock power supply domain comprises a second linear voltage regulator. Power supply output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected with a power supply detection circuit; the power supply detection circuit is used for outputting a power supply establishment signal; the digital power domain comprises a second AND gate unit, and the clock power domain comprises a third AND gate unit; wherein the second AND gate unit is used for enabling the first linear voltage regulator to start; and the third AND gate unit is used for enabling the second linear voltage regulator to start. The problem that in the prior art, the LDO of the digital power domain and the LDO of the clock power domain are likely to be different in voltage building time in the power-on starting process, and consequently overvoltage of a low-voltage device is caused is solved, and the reliability of a digital-to-analog converter chip is improved.

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

Some embodiments of the present disclosure include a digital-to-analog conversion system configured to reduce inter-symbol interference (ISI) in high-speed continuous-time DACs. The system can include a main DAC with multiple sub-DACs, each configured to process a portion of a digital input sequence and generate part of an output waveform. To address ISI errors introduced by the sub-DACs, the system can include an ISI mitigation feedback loop. The ISI mitigation feedback loop can include an analog-to-digital converter (ADC) that generates a digital sequence from the output waveform and an analog correction signal generated by a correction DAC. A fractional decimation filter can be used to adjust a sampling rate and attenuate high-frequency components. A digital error estimator can generate an error cancellation sequence by correlating encoder information with the input sequence. The correction DAC can use the error cancellation sequence to generate the analog correction signal.

Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.

A method for calibrating a machine-learning unit includes generating an analog calibration signal from an input sequence; generating a digital calibration signal by taking digital samples representing the value of the analog calibration signal at a predetermined sample rate; and applying the analog calibration signal as an input to a physical parallel array analog-to-digital converter (PA ADC) to produce a digital response. The method further includes producing an output by the machine-learning unit, at least in part based on the digital response; modifying a parameter of the machine-learning unit to reduce an error between the output and the digital calibration signal; and determining that the error is not less than a predetermined threshold.

The embodiment of the invention provides a signal processing device, a signal processing method, electronic equipment and a storage medium. The signal processing device comprises a signal processing circuit used for receiving a first transmission parameter of an input signal associated transmission path through an input interface; based on a predetermined frequency parameter, performing frequency resampling on the first transmission parameter to obtain a second transmission parameter, and determining a first frequency response of the transmission path based on the second transmission parameter; wherein the first frequency response is associated with embedding processing or de-embedding processing of the input signal; performing conjugate symmetry processing on the first frequency response to obtain a complex conjugate symmetry second frequency response corresponding to the first frequency response; converting the second frequency response from a frequency domain to a time domain to obtain a unit pulse response of the transmission path; determining filtering parameters of the digital filter based on the unit pulse response; and the digital filter is used for processing the input signal based on the filtering parameter to obtain an output signal.

The invention relates to the technical field of analog-to-digital converters, in particular to an on-chip adjustable non-uniform quantization analog-to-digital converter based on a memristor. Comprising a memristor array unit, an input signal conversion circuit, an output signal control conversion circuit and an on-chip adjustment circuit, the input signal conversion circuit is used for connecting an original input signal and a reference voltage and performing amplitude conversion on the input signal and the reference voltage; the memristor array unit is used for receiving the converted input signal and reference voltage and dividing the reference voltage into a plurality of reference voltage nodes; the output signal control conversion circuit is used for connecting a plurality of reference voltage nodes and outputting a digital signal in a bus form; and the on-chip adjusting circuit is used for carrying out gating adjustment on the memristor array unit, so that non-uniform quantization of data is realized, and quantization noise is effectively reduced.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention discloses a dynamic sliding window filtering method and device, and a medium. The method comprises the following steps: calculating and updating a sliding window length given value in real time based on a currently collected power grid frequency; comparing the obtained sliding window length given value with the current sliding window length; if the sliding window length given value is equal to the current sliding window length, the current sliding window length is kept unchanged; if the sliding window length given value is larger than the current sliding window length, the sliding window length is gradually increased according to a set mode; if the sliding window length given value is smaller than the current sliding window length, the sliding window length is gradually shortened according to a set mode. The device and the medium are both used for implementing the method. The beneficial effects of the application are that compared with a traditional fixed sliding window length, the technical scheme of the application can adaptively adjust the sliding window length according to the change of the power grid frequency, so that the data acquisition accuracy of the sliding window can be improved, and effective elimination of ripples can be realized.

The invention relates to the technical field of electronic information, and discloses a multichannel sampling interference suppression method based on a single-chip microcomputer ADC, and the method comprises the following steps: dynamic sequence generation: generating different channel sampling sequences for each sampling period, and enabling the adjacent probabilities of any two channels in a time sequence to be equal; data acquisition: sequentially executing each round of sampling, and recording the sampling value of each channel in each round; and error spreading: carrying out statistical processing on sampling values obtained by multi-round sampling of each channel, and outputting a final sampling value after interference suppression. According to the method, active suppression of adjacent channel interference is realized through dynamic sequence generation, data acquisition and error sharing, the insertion of a dependent reference channel is avoided, the scanning efficiency of ADC multi-channel sampling and the dynamic scene adaptability are improved, a high-precision sampling value is finally output, and the requirements of single-chip microcomputer multi-channel ADC application are met.

An analog to digital converter including a digital to analog converter (DAC), a comparator, and a controller. The DAC includes a sample node and a capacitor array controlled by a digital control input. The comparator compares a voltage of the sample node with a reference voltage to generate a comparison value. The controller presets the digital control input, prompts the DAC to sample the input voltage onto the sample node, resets the digital control input, and performs a conversion by successively adjusting the digital control input based on the comparison value to determine a digital output. A preset value is subtracted from the digital output to provide an adjusted digital output. A sample predictor predicts the next sample to determine the preset value used to adjust the sample node within a full scale range after DAC reset.

In general, according to one embodiment, a semiconductor integrated circuit includes the following configuration. A first converter samples a first digital value from an analog signal based on a first clock signal. A second converter samples a second digital value from the analog signal based on a second clock signal differing from the first clock signal by a first phase. A first processing circuit calculates phase shifts of the first and second clock signals based on the first and second digital values and using a first frequency of a third clock signal. A second processing circuit generates a control signal for correcting the phase shifts of the first and second clock signals based on the phase shifts calculated by the first processing circuit and using a second frequency of a fourth clock signal. The second frequency is 2m times the first frequency.

The invention discloses a grid voltage bootstrapped switch circuit with compensation and an ADC, and belongs to the technical field of integrated circuits. The circuit comprises a compensation charge pump circuit and a grid voltage bootstrapped switch circuit. A charge pump branch power supply end in the grid voltage bootstrap switch circuit is connected to an output compensation voltage end of the compensation charge pump circuit; when the input clock signal CLK1 is low and the input clock signal CLK2 is high in level, the power supply end of the charge pump branch is switched off, and the capacitor in the charge pump circuit is compensated for charging; when the level of the CLK1 is high and the level of the CLK2 is low, the power supply end of the charge pump branch is switched on, a bootstrap capacitor in the grid voltage bootstrap switch circuit is charged, and the Vboost provides compensation voltage. The compensation charge pump circuit provides higher power supply voltage for the grid voltage bootstrap switch, grid voltage drop of the sampling switch tube caused by parasitic capacitance at the positive end of the bootstrap capacitor can be compensated back, input parasitic capacitance is reduced, on-resistance of the sampling switch tube is reduced, and sampling linearity is improved.

The invention provides a temperature sensor for rapid calibration and a calibration method of the temperature sensor, and the temperature sensor comprises a bias module which is used for providing a bias current for a temperature sensing module; the temperature sensing module is used for determining a first VBE voltage and a second VBE voltage according to the bias current, generating a voltage signal in positive correlation with the temperature through a VBE voltage difference between the first VBE voltage and the second VBE voltage, and transmitting the voltage signal to the analog-to-digital conversion module and the instrument amplifier respectively; the analog-to-digital conversion module is used for determining a first temperature value through the voltage signal and the original reference voltage of the temperature sensor; the instrument amplifier is used for determining a second temperature value through the voltage signal; wherein the temperature difference value between the first temperature value and the second temperature value is used for calibrating the original reference voltage to obtain the target reference voltage. According to the embodiment of the invention, the environment requirement for temperature sensor chip calibration can be greatly reduced, the calibration time of the chip is shortened, and the production efficiency of the chip is improved.

The invention discloses a digital measurement system channel error automatic calibration method, a storage medium and a system, and aims to automatically calibrate zero drift and multiplying power change errors from the angle of reducing DMS analog measurement channel tool errors. The method comprises the following steps of: firstly, connecting an input end of the DMS with a digital-to-analog converter (DAC), a circuit ground and a reference source Vref respectively, then measuring corresponding output voltages Dos, Dx and Dref of the DMS, and finally obtaining a calibration voltage Ui after error elimination by utilizing a formula # imgabs0 #. The calibration circuit required by the invention is simple in structure, low in cost, suitable for different types of DMS equipment, free of synchronism requirements on a measurement system, low in operation difficulty, capable of calibrating relative errors and absolute errors, high in automation degree, and capable of improving the measurement precision of the DMS on the premise of considering the measurement time; and the working reliability and stability of the measuring equipment are improved.

The invention discloses a radar pulse signal sampling and storing method and device based on an FPGA in the technical field of signal processing. The method comprises the steps that S1, radar pulse signals are acquired and sampled, and radar pulse data to be stored are acquired after processing; s2, a half-power point is obtained from the radar pulse data, data storage is started when the signal amplitude is larger than or equal to the half-power point for the first time, and the half-power point is obtained by subtracting a set value from the amplitude of a pulse signal corresponding to a first standard maximum value point of the rising edge of the radar pulse data. Compared with a conventional method, the sampling storage method can effectively avoid the influence of the pulse signal amplitude on the position of the rising edge of the detection signal, so that the initial position of data storage is relatively stable, the position of an interference target which is delayed and forwarded later is also relatively stable, and a relatively good interference effect is achieved.

The invention relates to the field of electronic signal processing, and discloses a 3D rocker sensor-based digital quantity center point adaptive verification system, which comprises a data acquisition layer used for acquiring an analog signal of a 3D rocker sensor through an analog-to-digital converter and converting the analog signal into a digital signal; the data preprocessing layer is used for carrying out filtering processing and center point correction on the acquired digital signals and dynamically adjusting the maximum value and the minimum value of the signals; the signal conversion layer is used for converting the corrected signal into a standardized data format so as to adapt to a control system; and the signal output layer is used for smoothing the standardized signal and compensating the signal according to action recognition. Through a digital quantity dynamic correction technical scheme based on the 3D rocker sensor, real-time correction of a rocker signal center point is realized, signal deviation caused by drifting and external interference is eliminated, signal stability and processing precision are improved, and meanwhile, robustness and use reliability of a system are improved.