1998results about "Physical parameters compensation/prevention" patented technology

The invention relates to an anti-electromagnetic interference intelligent cooling fan system based on dynamic filter circuit design. The system comprises a dual analysis module used for performing time domain and frequency domain dual analysis on a rotating speed feedback signal of a double-ball fan to obtain a multi-dimensional electromagnetic interference characteristic model, and configuring filter network parameters to obtain a target three-stage cascade dynamic filter network; the signal purification module is used for collecting first fan operation parameters and inputting the first fan operation parameters into a target three-stage cascade dynamic filter network for signal purification to obtain filtered Hall sensor signals and filtered power supply signals; the closed-loop control calculation module is used for performing closed-loop control calculation to obtain a non-linear PWM duty ratio control quantity and a phase distribution parameter; and the phase difference control module is used for carrying out phase difference control to obtain a multi-fan cooperative control strategy. According to the invention, high-precision control and anti-interference capability in a wide rotating speed range are realized, and the problem of mutual influence of electromagnetic interference when multiple fans are connected in parallel is solved.

The invention belongs to the technical field of signal acquisition and processing, and discloses a low-noise biopotential signal acquisition system and a low-noise biopotential signal processing method. An original bioelectricity signal of a human body is collected through an electrode array, and analog-to-digital conversion is carried out after the signal is processed by a multi-stage self-adaptive filtering and amplifying circuit. A digital signal is sequentially subjected to adaptive wavelet transform denoising and empirical mode decomposition to obtain a multi-level intrinsic mode function set, an intrinsic mode function of a characteristic frequency band is extracted from the multi-level intrinsic mode function set, and the signal is reconstructed. Introducing a dual noise reduction mechanism combining adaptive wavelet transform and empirical mode decomposition; a signal quality real-time evaluation system is established, and system parameters including the gain of a variable gain amplifier and the bandwidth of a dynamic band-pass filter are dynamically adjusted through closed-loop feedback. The self-adaptive optimization of the whole biopotential signal acquisition process is realized, various interferences are effectively inhibited, the signal characteristics are reserved, and the signal-to-noise ratio is remarkably improved.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

An interleaved Analog-to-Digital Converter (ADC) has a reference channel receiving an attenuated analog input. The reference channel is also calibrated to remove capacitor-ratio mismatch, static, and dynamic mismatches and produces a linear replica of the data channels with negligible nonlinear errors due to attenuation. Nonlinear errors on the data channels are corrected by Harmonic Distortion HD2 and HD3 coefficients. A counter increments when the sign bit of a nonlinear-corrected channel code is negative. The count is doubled and reduced by a number of samples to generate a HD2 cost function that adjusts the HD2 coefficient in a LMS loop. A HD3 correlation is generated by multiplying the reference channel output by its difference with the nonlinear-corrected channel code. The sign of the correlation code increments a second counter which generates a HD3 cost function whose sign bit adjusts the HD3 coefficient. These 2 counters generate cost functions, eliminating sample storage.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

The invention provides an analog-to-digital converter, a conversion method and an electronic product. The analog-to-digital converter comprises a differential analog-to-digital conversion module and a compensation module, the differential analog-to-digital conversion module is used for eliminating sampling thermal noise based on a double-sampling mode and realizing analog-to-digital conversion of an input signal; the compensation module receives the compensation signal, the output end of the compensation module is connected to the input end of a pre-amplifier in the differential analog-to-digital conversion module, and the compensation module compensates the change of the input signal coupled to the input end of the pre-amplifier based on a differential mode; wherein the input signal and the compensation signal which are connected to the same input end of the pre-amplifier are differential signals. According to the analog-to-digital converter, the conversion method and the electronic product, the sampling thermal noise elimination technology is adopted, the signal bandwidth limited by the saturation problem of the amplifier is increased by adopting the first-order approximate compensation module based on the differentiating circuit, and the analog-to-digital converter has the advantages of being small in sampling capacitance, low in noise, large in signal bandwidth and the like.

Method and apparatus for skew error measurement and correction in a digital-to-analog converter (DAC) using a time-to-digital converter (TDC). A DAC includes a main DAC and a TDC. The main DAC includes a plurality of DAC cells. The main DAC is configured to generate an analog output signal based on digital input data. The TDC is coupled to an output of the main DAC and configured to measure a timing error of the main DAC. The timing error may be measured on a DAC cell basis or a subset of DAC cells basis.

A signal processing circuit for a measurement instrument is described. The signal processing circuit comprises a measurement input, a first measurement channel, a second measurement channel, and a noise canceling circuit. The first measurement channel comprises a first wideband analog-to-digital converter (ADC) and a first transformation circuit. An output signal of the first measurement channel is a first frequency domain signal. An output signal of the second measurement channel is a second frequency domain signal. The first frequency domain signal and the second frequency domain signal are a complex-valued signal, respectively. The noise canceling circuit is configured to receive the first frequency domain signal and the second frequency domain signal and to determine a combined average of the first frequency domain signal and of the second frequency domain signal over a predetermined number of frequency bins, thereby obtaining a complex-valued average signal. Further, a measurement system is described.

The invention belongs to the technical field of integrated circuits, and particularly relates to a multichannel ultrasonic imaging special integrated circuit suitable for integrated packaging. The application-specific integrated circuit is formed by cascading a plurality of multi-channel single chips, the multi-channel single chips adopt four ultrasonic channel input architectures, and each channel comprises an ultrasonic analog front end, an analog-to-digital converter and an ultrasonic digital signal processing module; the ultrasonic analog front end comprises four sub-modules, namely a low-noise amplifier, a voltage control attenuator, a programmable gain amplifier and an anti-aliasing low-pass filter; the analog-to-digital converter adopts a three-stage successive approximation register pipeline cascade structure to realize 14-bit digital output; the ultrasonic digital signal processing module is used for processing the ultrasonic signals quantized by the ADC, including ADC data preprocessing, data demodulation, signal interpolation and extraction, beam forming, test signal generation and the like; the number of channels is expanded through SIP packaging, and the method can be used for ultrasonic imaging of medical ultrasonic diagnosis and has high flexibility and expandability.

The invention discloses a passive feed-forward noise shaping SAR ADC structure and a quantification method thereof. The structure comprises a second-order noise shaping circuit based on a charge pump, a sampling switch circuit, a DAC capacitor array, a six-input comparator and a logic control circuit. The method comprises the following steps: sampling an input analog signal to an upper pole plate of a DAC capacitor array; carrying out inter-board capacitor voltage switching processing according to the control signal, and outputting a successive approximation voltage signal; obtaining quantization residual voltage in inter-board capacitor voltage switching processing, performing second-order noise shaping filtering processing, and outputting a first-order integral voltage signal and a second-order integral voltage signal; comparing the successive approximation voltage signal, the first-order integral voltage signal and the second-order integral voltage signal to obtain a digital code; and carrying out inter-board capacitor voltage switching according to the digital code to obtain a quantization result. According to the embodiment of the invention, the power consumption of the SAR ADC structure can be reduced, and the quantization precision of the SAR ADC structure can be improved. The circuit can be widely applied to the technical field of integrated circuits.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

The invention discloses a discrete time increment type analog-to-digital converter and a control method thereof, the analog-to-digital converter comprises a modulator and a digital filter, and the modulator comprises an integrator module, a single-bit quantizer, an FIR feedback digital-to-analog converter, a first compensation path and a second compensation path. The control method comprises the following steps: carrying out noise shaping processing on an input signal and an output signal of a single-bit quantizer to obtain a preliminary output signal; and the digital filter is used for filtering the preliminary output signal to obtain an output signal of the analog-to-digital converter. According to the analog-to-digital converter, hardware consumption and digital power consumption can be reduced, the conversion precision of the analog-to-digital converter is improved, and the signal distortion degree of the analog-to-digital converter is reduced. The circuit can be widely applied to the technical field of mixed signal circuits.

The invention provides a continuous time pipeline analog-to-digital converter based on a multipath interleaving time domain. The continuous time pipeline analog-to-digital converter comprises a continuous time level ADC, a time domain ADC and a digital reconfigurable filter, the continuous time-stage ADC performs high-order quantization on an input signal and then outputs the input signal to the digital reconfigurable filter, and performs filtering processing on a residual signal in the input signal and then outputs the residual signal to the time-domain ADC; the time domain ADC is used for quantizing the residual signals passing through the continuous time level ADC and then outputting the quantized residual signals to the digital reconfigurable filter; and the digital reconfigurable filter is used for carrying out digital filtering on the quantization result of the continuous time level ADC and carrying out data reconstruction on the quantization code value output by the time domain ADC. The architecture not only retains the characteristics of ultrahigh energy efficiency and digitization of a time domain ADC, but also benefits from the continuous time ADC architecture, and the resistive input impedance and the inherent anti-aliasing filtering effect of the continuous time ADC architecture are beneficial to the realization of a high-speed ADC in a completely integrated wireless receiver.

The current disclosure is related to digital-to-analog converters (DACs) with localized frequency multiplication circuits. For example, an electronic device may include a local oscillator (LO) providing clock signals, a digital front-end providing digital signals, a DAC, (e.g., a radio frequency DAC (RFDAC)), and one or more antennas. The DAC may include a number of cells (e.g., unit power amplifiers). Moreover, each cell may provide a unit power analog signal upon activation with a higher frequency than the received digital signals and clock signals. The DAC may provide an output signal (e.g., an analog signal) based on combining (e.g., aggregating) the unit power analog signals of the activated cells for transmission by the one or more antennas.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

A noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) including a noise-shaping (NS) filter, a comparator, a differential input path between the NS filter and the comparator, and a cross-coupled set of capacitive elements coupled to the differential input path.

A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.

The invention discloses a signal receiving method and device, which can reduce the peak power of a signal input to an analog-to-digital converter (ADC), thereby reducing quantization noise and improving signal receiving performance. The method comprises the following steps: receiving a first signal by a receiving device, performing down-conversion on the first signal to obtain a second signal, determining a third signal according to the second signal, sampling the third signal, and determining a target signal. Wherein the first signal comprises a target signal, and the target signal adopts comb mapping, that is, the target signal occupies one subcarrier in every M continuous subcarriers. The third signal comprises superposition of K delay signals of the second signal, the delay time associated with the kth delay signal in the K delay signals is # imgabs0 #, T is the time length of the first signal, k = 1, 2,..., K, delta is greater than or equal to 0, M is a positive integer greater than 1, and K is a positive integer greater than or equal to M.

An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

The invention discloses a high-precision analog domain gain error shaping analog-to-digital converter and an implementation method thereof, and relates to the field of integrated circuit design. The high-precision analog domain gain error shaping analog-to-digital converter adopts a fully differential structure; comprising a first-stage sub analog-to-digital converter, a residual error amplifier and a second-stage sub analog-to-digital converter which are connected in sequence. A first-stage sub analog-to-digital converter is designed into a coarse-fine quantization architecture of an NS SAR ADC and a DAC, an input signal is sampled and quantized through the coarsely quantized NS SAR ADC to generate a first-stage digital code, and then the first-stage digital code is read to the finely quantized DAC. And the finely quantized DAC performs DAC array switching according to the first-stage digital code, and directly obtains the shaped first-stage quantization noise to realize gain error shaping. The method does not need to predict the first-stage quantization noise any more, solves the problem that the truncation error is not matched with the gain, and achieves a better gain error shaping effect.

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CTΣΔ achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS / s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.

Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

The invention discloses a digital-to-analog converter chip which comprises an analog power supply for supplying power to an analog power supply domain, a digital power supply for supplying power to a digital power supply domain and a clock power supply for supplying power to a clock power supply domain, the digital power supply domain comprises a first linear voltage regulator, and the clock power supply domain comprises a second linear voltage regulator. Power supply output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected with a power supply detection circuit; the power supply detection circuit is used for outputting a power supply establishment signal; the digital power domain comprises a second AND gate unit, and the clock power domain comprises a third AND gate unit; wherein the second AND gate unit is used for enabling the first linear voltage regulator to start; and the third AND gate unit is used for enabling the second linear voltage regulator to start. The problem that in the prior art, the LDO of the digital power domain and the LDO of the clock power domain are likely to be different in voltage building time in the power-on starting process, and consequently overvoltage of a low-voltage device is caused is solved, and the reliability of a digital-to-analog converter chip is improved.

The invention provides an analog-to-digital conversion circuit and electronic equipment, and relates to the field of integrated circuits. The coarse quantization unit and the fine quantization unit simultaneously sample an input differential signal and store the input differential signal on a capacitor array of the fine quantization unit. The coarse quantization unit firstly uses the resistor string unit to carry out coarse quantization on the voltage quantity to obtain 2M-1-bit thermometer codes, the 2M-1-bit thermometer codes are transmitted to the thermometer code capacitance control logic of the fine quantization unit, and meanwhile transcoding is carried out to obtain M-bit binary codes. And the fine quantization unit is combined with the redundant bit capacitor and resistor string unit to jointly carry out calibration and fine quantization on the residual voltage quantity to obtain an N + 2 bit binary code. And the digital error correction unit performs digital error correction on the M-bit binary code and the N + 2-bit binary code to obtain an M + N-bit binary code and outputs the M + N-bit binary code. According to the method, the problem that coarse quantization and fine quantization of the whole ADC are not matched due to the fact that the coarse quantization precision is limited is successfully solved. Therefore, the analog-to-digital conversion circuit provided by the invention reaches the precision of a traditional high-precision SAR-ADC. And the overall power consumption overhead is saved.

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

Some embodiments of the present disclosure include a digital-to-analog conversion system configured to reduce inter-symbol interference (ISI) in high-speed continuous-time DACs. The system can include a main DAC with multiple sub-DACs, each configured to process a portion of a digital input sequence and generate part of an output waveform. To address ISI errors introduced by the sub-DACs, the system can include an ISI mitigation feedback loop. The ISI mitigation feedback loop can include an analog-to-digital converter (ADC) that generates a digital sequence from the output waveform and an analog correction signal generated by a correction DAC. A fractional decimation filter can be used to adjust a sampling rate and attenuate high-frequency components. A digital error estimator can generate an error cancellation sequence by correlating encoder information with the input sequence. The correction DAC can use the error cancellation sequence to generate the analog correction signal.