56results about "Synchronisation error detection" patented technology

The application discloses a frame synchronization-based laser communication and ranging integrated system, and belongs to the technical field of satellite laser communication.The system solves the problem that ranging precision is limited under the condition of low communication rate.The system comprises a sending end and a receiving end, wherein the sending end comprises a synchronization header sequence generating module, a data sequence generating module and a framing module, the receiving end comprises a synchronization sliding correlation / rough ranging calculation module, a fine ranging calculation module and a data sequence extracting module; the synchronization header sequence generating module generates a synchronization header sequence, the data sequence generating module generates a data sequence, and the framing module completes splicing of the synchronization header sequence and the data sequence; the synchronization sliding correlation / rough ranging calculation module performs frame synchronization and calculates an integer symbol period of transmission delay, the fine ranging calculation module calculates a fractional symbol period of transmission delay, and the data sequence extracting module performs frame disassembly according to a starting position of the synchronization header sequence, extracts the data sequence and completes communication reception.

This application provides a frequency offset correction method and a communication apparatus, and relates to the field of wireless communication technologies. The method includes: A second device performs down-conversion by using a first local oscillator signal, to receive a first reference signal from a first device, and adjusts the first local oscillator signal based on a receiving result of the first reference signal, to obtain a second local oscillator signal, where a frequency offset of the second local oscillator signal is less than a frequency offset of the first local oscillator signal. The second device performs down-conversion by using the second local oscillator signal, to receive a first data signal from the first device, where a guard band of the first reference signal is greater than a guard band of the first data signal.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

The invention relates to the technical field of signal processing, and discloses a time slot control method and system for an inter-satellite link time division communication system, and the method comprises the steps: carrying out the clock domain crossing synchronization and jitter elimination processing of a pulse per second signal inputted externally, and detecting the validity of the processed pulse per second signal; extracting a time error between a local clock and an external clock based on the second pulse signal after validity detection; performing continuous health detection on the time error to generate a health state indication; performing second-order filtering processing on error information by referring to the health state indication and the time error, taking a processing result as an adjustment amount of a frequency control word of an NCO counter, and driving the NCO counter to generate a time reference; and detecting whether an external pulse per second signal is subjected to slip adjustment or not, and distributing a time slot control signal by using the time reference. Accurate distribution of time information is achieved, misreading of externally input time information is avoided, and the adaptive capacity of the system under different working conditions is improved.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

The present invention provides a synchronization circuit device and a method for generating a synchronization signal. The synchronization circuit device includes: a carrier frequency offset blind estimation circuit, which is configured to receive a multi-bit frequency domain data stream and a synchronization signal fed back from an address synchronization circuit, and output a first carrier frequency offset estimation value; a carrier frequency offset compensation circuit, which is configured to perform carrier frequency offset compensation on the received multi-bit frequency domain data stream according to the first carrier frequency offset estimation value, and output a frequency domain data stream without carrier frequency offset as a single bit; and an address synchronization circuit, which is configured to receive the frequency domain data stream without carrier frequency offset as a single bit, and output a synchronization signal.

The embodiment of the invention relates to a baud rate detection method and device, equipment and a storage medium. The method comprises the following steps: receiving interval section signals, recording interval transmission duration, and obtaining a preliminary baud rate according to the interval transmission duration; under the condition that the preliminary baud rate has the adjacent baud rate, setting a sampling baud rate matched with the preliminary baud rate; receiving a synchronous section signal, and sampling the synchronous section signal according to the sampling baud rate to obtain synchronous sampling data; and determining a target baud rate in the preliminary baud rate and the adjacent baud rate according to the synchronous sampling data. According to the technical scheme provided by the embodiment of the invention, high-precision Baud rate detection is realized without a high-frequency timer, the number of Baud rates which can be compatible with a self-adaptive Baud rate communication system is increased, and the operation resources and hardware cost of the system are saved.

The application discloses a data alignment method and system, an electronic device and a storage medium, and relates to the field of data processing. The method is applied to a transmission link with multiple data channels, and comprises the following steps: for each data channel, at different delay times, detecting whether the sampling edge of a clock signal is in a stable region of a transmission signal based on a preset training code; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the detection result as a first flag; otherwise, recording the detection result as a second flag; sorting the first flags of the data channels according to the order of the delay times to obtain a first continuous interval formed by continuous first flags; obtaining a common delay time interval as a first common interval; and delaying the clock signal based on the delay time at the center of the first common interval to correct the phase deviation of any data channel in the transmission link.

Data equalization system, featuring: a data clock input configured to receive a clock signal; an input node which is to be operated in such a way that it receives a data signal of transmission symbols which change their state synchronously with the clock signal; a first branch which is connected to the input node; and a second branch configured to receive a modification of the data signal, wherein at least one of a weighting of the first branch and a weighting of the second branch is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

At least some aspects of the present disclosure provide for a method (500). In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal (510) and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result (520). The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages (525). The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts (535) and applying second equalization to the received data signal based on the determined relationship among the plurality of counts (540).

The invention discloses a signal receiving method, a signal receiving device and a communication system. The signal receiving method comprises the steps that a command feedback signal is received, and the command feedback signal comprises a start bit and an information bit behind the start bit; generating a detection signal based on the command feedback signal, the detection signal comprising a plurality of detection windows opened after an end position of the start bit, the plurality of detection windows being in one-to-one correspondence with a plurality of jump edges of the information bit, the position of the (n + 1) th detection window is determined according to the jump edge detected in the nth detection window, and n is a positive integer. According to the technical scheme, the position of the (n + 1) th detection window is determined through the jump edge detected in the nth detection window, so that the offset of the detection window and the jump edge can be reduced, the offset of the detection window cannot be accumulated, and the data receiving success rate is greatly improved.

The invention discloses a very simple clock error detection method and device under a flexible oversampling factor, equipment, a storage medium and a product, and relates to the technical field of clock error detection, and the method comprises the steps: carrying out the complex number symbol processing of a received signal, and obtaining a symbol result; and querying a preset clock error mapping table based on the symbol result to obtain a clock error. According to the method, the received signal is subjected to complex number symbol processing to obtain the symbol result, and the preset clock error mapping table is queried based on the symbol result to obtain the clock error. Compared with an existing digital timing error detector with too high calculation complexity, the digital timing error detector has the advantages that multiplication in existing clock error detection can be eliminated, and power consumption and calculation resources are reduced.

The present invention relates to an interface circuit, a memory controller, and a method for calibrating multiple signal processing devices within an interface circuit of a memory controller. The method includes: negotiating an operating mode of the interface circuit in a calibration process with a host device during a link process; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device during the calibration process, wherein the first signal processing device is configured on a receive signal processing path to process a receive signal, and the second signal processing device is configured on a transmit signal processing path to process a transmit signal, and the interface circuit operates according to the operating mode during the calibration process.

Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

The invention provides a synchronization method and device, equipment, a storage medium and a program product, and relates to the technical field of wireless, the method is applied to an accelerator card, the accelerator card is inserted into a server through a golden finger of a communication interface, and the method comprises the following steps: processing a first PP1S signal of a GNSS by using a two-stage clock circuit to obtain a first pulse signal; according to the first pulse signal, synchronization information is generated, and the synchronization information comprises a frame header, a frame number, a time slot header and a time slot number; sending the frame header and the frame number to an active antenna unit (AAU), and sending the frame number, the time slot header and the time slot number to the server through the communication interface; the frame header and the frame number are used for the AAU to perform clock synchronization, and the frame number, the time slot header and the time slot number are used for the server to perform clock synchronization. Therefore, the acceleration card can obtain the stable pulse signal so as to provide stable synchronization information for the server and the AAU, and synchronization of the server, the AAU and the acceleration card is realized.

The application discloses a differential link alignment method and system, and relates to the field of data processing. The method comprises the following steps: judging whether the sampling edge of a clock signal is in a stable region of a differential link based on a training code at different delay times; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the judgment result as a first flag; otherwise, recording the judgment result as a second flag; arranging the first flag and the second flag according to the order of the delay times to obtain a flag set; screening out a middle flag of any first interval or second interval in the flag set; and delaying the clock signal or the differential link based on the delay amount corresponding to the middle flag, so as to realize data alignment of the differential link. Based on the above processing, the sampling edge of the clock signal after data alignment can be prevented from being in a jump region.

Technologies for periodic and synchronous phase error detection and compensation are described. An integrated circuit includes a clock source to generate a clock signal having a first frequency, and an analog-to-digital converter (ADC) to sample an incoming signal to obtain data samples using a sampling clock. The data samples include a periodic and synchronous phase error caused by the clock signal. The periodic and synchronous phase error has a harmonic of the first frequency. The integrated circuit also includes a signal processing circuit coupled to the ADC and the clock source. The signal processing circuit includes a harmonic phase correction block to detect and compensate for the periodic and synchronous phase error in the data samples to obtain corrected data samples.

A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

The present invention provides a synchronization circuit apparatus and a synchronization signal generation method. The synchronization circuit apparatus comprises: a carrier frequency offset blind estimation circuit, which is configured to receive a multi-bit frequency-domain data stream and a synchronization signal that is fed back from an address synchronization circuit, and output a first carrier frequency offset estimation value; a carrier frequency offset compensation circuit, which is configured to perform carrier frequency offset compensation on the received multi-bit frequency-domain data stream on the basis of the first carrier frequency offset estimation value, and output a single-bit frequency-domain data stream without a carrier frequency offset; and the address synchronization circuit, which is configured to receive the single-bit frequency-domain data stream without a carrier frequency offset, and output a synchronization signal.

Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

The invention provides a clock recovery method. The clock recovery method comprises the following steps: determining a sampling phase deviation based on any subcarrier in demultiplexed subcarriers; and obtaining a subcarrier signal after clock recovery based on the sampling phase deviation and the center frequency of the subcarrier after demultiplexing. The invention further provides electronic equipment, a readable medium and a program product.

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

This invention discloses a signal processing method, apparatus, receiver, and electronic device for GFSK demodulation. The method includes: obtaining a local angle sequence of a theoretical GFSK modulated signal based on a preset synchronization word; obtaining a reference angle difference sequence based on the local angle sequence; obtaining a signal angle sequence based on the received baseband signal; obtaining a window angle difference sequence corresponding to each window state from the signal angle sequence based on a sliding window, wherein the size of the sliding window is determined by the length of the local angle sequence; and determining the synchronization position in the received baseband signal for GFSK demodulation based on the window state with the highest similarity to the reference angle difference sequence; or including: determining the interference caused by the previous symbol sequence and the next symbol sequence according to the preset synchronization word; and performing synchronization word decision by eliminating interference based on the synchronization position. Therefore, this invention can reduce computational complexity, thereby reducing system computational cost and improving system demodulation performance.

The embodiment of the invention provides a synchronization method based on a dynamic sparse attention mechanism, electronic equipment and a storage medium, and relates to the technical field of wireless communication, and the method comprises the following steps: setting a plurality of parallel frequency domain channels to carry out frequency compensation on an input signal, the number of the plurality of parallel frequency domain channels is the same as the number of frequencies used by the synchronization section; carrying out sliding correlation operation on the signals of each channel after frequency compensation, and then carrying out double-threshold peak detection and time consistency detection; extracting the following characteristics from the detected threshold peak values: related peak amplitude, peak-to-average ratio, frequency consistency, kurtosis coefficient and peak value number; and on the basis of the extracted features, a feature importance probability is calculated by adopting an attention network based on dynamic sparseness, and the arrival time for synchronization processing is determined according to the feature importance probability. The method can effectively resist interferences such as synchronous forwarding and frequency hopping following, and improves the anti-interference capability of a communication or data link system.

Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.

The invention discloses a data alignment method and system, electronic equipment and a storage medium, and relates to the field of data processing. The method is applied to a transmission link with a plurality of data channels, and comprises the following steps: for each data channel, detecting whether a sampling edge of a clock signal is in a stable region of a transmission signal based on a preset training code at different delay times; if yes, and a latch value obtained based on the sampling edge under the current delay time belongs to a first set, recording the detection result as a first mark; otherwise, recording the detection result as a second mark; sorting the first marks of the data channels according to the sequence of the delay time to obtain a first continuous interval formed by the continuous first marks; acquiring a common delay time interval as a first common interval; and delaying the clock signal based on the delay time at the center of the first common interval so as to correct the phase deviation of any data channel in the transmission link.

The invention discloses a differential link alignment method and system, and relates to the field of data processing. The method comprises the following steps: under different delay times, judging whether a sampling edge of a clock signal is in a stable region of a differential link based on a training code; if yes, when a latch value obtained based on the sampling edge under the current delay time belongs to a first set, recording the judgment result as a first mark; otherwise, recording the judgment result as a second mark; arranging the first mark and the second mark according to the sequence of the delay time to obtain a mark set; in the mark set, screening out a middle mark of any first interval or second interval; and delaying the clock signal or the differential link based on the delay amount corresponding to the intermediate mark so as to realize data alignment of the differential link. Based on the processing, the sampling edge of the clock signal after data alignment can be prevented from being in the hopping region.

The present disclosure describes systems and methods that enable a user terminal to eliminate or reduce the number of false bursts (or bursts without data) that it transmits. These systems and methods use two burst detectors - a first burst detector that analyzes the physical structure of a signal and a second burst detector that analyzes the information structure of a signal. The output from the first burst detector can be used to control the operation of a signal decoder that decodes a received signal. The second burst detector analyzes the output from the signal decoder to determine a second burst indicator. In other words, the first burst detector can be implemented prior to decoding the received signal to provide a first estimate as to the presence or absence of a burst. The first estimate can then be used to limit the amount of processing performed by the signal decoder.

A lock-detection circuit detects whether a first clock signal is frequency locked to a second clock signal. A lock-detection scheme that continuously evaluates the lock condition between the clock signals and as programmable frequency-offset tolerances for reporting lock acquisition and loss. A quadrature clock generator produces two periodic signals from the first clock signal. The periodic signals are in quadrature, which is to say they are misaligned with one another by ninety degrees. These quadrature signals are sampled on edges of the second clock signal to produce a sequence of states that exhibit a Gray-code progression if first and second clock signals are locked. Errors in the Gray-code progression indicate whether edges of the first clock signal are early or late with respect to the second clock signal. The lock-detection circuit is adjustable to indicate loss of lock under in dependence upon the temporal spacing of errors.

The application discloses a kind of underwater acoustic physical layer network coding symbol synchronization methods, belong to underwater acoustic communication and networking field.Three-node underwater acoustic PNC symbol synchronization mechanism is designed: preset relay node R is expected to the fixed transmission delay T of two terminal nodes A and B S , two terminal nodes A and B reach this expected time as target, utilize clock information in data transmission process to estimate downlink propagation delay, obtain the waiting delay τ A (k) and τ B (k) required before multiple access of terminal nodes A and B in each round PNC transmission process, realize the symbol synchronization of each round PNC transmission;Establish asymmetric link Kalman filter clock synchronization algorithm, for providing accurate clock information for PNC symbol synchronization mechanism, improve the synchronization accuracy of PNC symbol synchronization mechanism.Reduce the time slot overhead of underwater acoustic network, improve the performance of entire underwater acoustic network.