26results about "Synchronisation error detection" patented technology

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

The application discloses a data alignment method and system, an electronic device and a storage medium, and relates to the field of data processing. The method is applied to a transmission link with multiple data channels, and comprises the following steps: for each data channel, at different delay times, detecting whether the sampling edge of a clock signal is in a stable region of a transmission signal based on a preset training code; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the detection result as a first flag; otherwise, recording the detection result as a second flag; sorting the first flags of the data channels according to the order of the delay times to obtain a first continuous interval formed by continuous first flags; obtaining a common delay time interval as a first common interval; and delaying the clock signal based on the delay time at the center of the first common interval to correct the phase deviation of any data channel in the transmission link.

Data equalization system, featuring: a data clock input configured to receive a clock signal; an input node which is to be operated in such a way that it receives a data signal of transmission symbols which change their state synchronously with the clock signal; a first branch which is connected to the input node; and a second branch configured to receive a modification of the data signal, wherein at least one of a weighting of the first branch and a weighting of the second branch is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

The invention discloses a very simple clock error detection method and device under a flexible oversampling factor, equipment, a storage medium and a product, and relates to the technical field of clock error detection, and the method comprises the steps: carrying out the complex number symbol processing of a received signal, and obtaining a symbol result; and querying a preset clock error mapping table based on the symbol result to obtain a clock error. According to the method, the received signal is subjected to complex number symbol processing to obtain the symbol result, and the preset clock error mapping table is queried based on the symbol result to obtain the clock error. Compared with an existing digital timing error detector with too high calculation complexity, the digital timing error detector has the advantages that multiplication in existing clock error detection can be eliminated, and power consumption and calculation resources are reduced.

The application discloses a differential link alignment method and system, and relates to the field of data processing. The method comprises the following steps: judging whether the sampling edge of a clock signal is in a stable region of a differential link based on a training code at different delay times; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the judgment result as a first flag; otherwise, recording the judgment result as a second flag; arranging the first flag and the second flag according to the order of the delay times to obtain a flag set; screening out a middle flag of any first interval or second interval in the flag set; and delaying the clock signal or the differential link based on the delay amount corresponding to the middle flag, so as to realize data alignment of the differential link. Based on the above processing, the sampling edge of the clock signal after data alignment can be prevented from being in a jump region.

Technologies for periodic and synchronous phase error detection and compensation are described. An integrated circuit includes a clock source to generate a clock signal having a first frequency, and an analog-to-digital converter (ADC) to sample an incoming signal to obtain data samples using a sampling clock. The data samples include a periodic and synchronous phase error caused by the clock signal. The periodic and synchronous phase error has a harmonic of the first frequency. The integrated circuit also includes a signal processing circuit coupled to the ADC and the clock source. The signal processing circuit includes a harmonic phase correction block to detect and compensate for the periodic and synchronous phase error in the data samples to obtain corrected data samples.

A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

The embodiment of the invention provides a synchronization method based on a dynamic sparse attention mechanism, electronic equipment and a storage medium, and relates to the technical field of wireless communication, and the method comprises the following steps: setting a plurality of parallel frequency domain channels to carry out frequency compensation on an input signal, the number of the plurality of parallel frequency domain channels is the same as the number of frequencies used by the synchronization section; carrying out sliding correlation operation on the signals of each channel after frequency compensation, and then carrying out double-threshold peak detection and time consistency detection; extracting the following characteristics from the detected threshold peak values: related peak amplitude, peak-to-average ratio, frequency consistency, kurtosis coefficient and peak value number; and on the basis of the extracted features, a feature importance probability is calculated by adopting an attention network based on dynamic sparseness, and the arrival time for synchronization processing is determined according to the feature importance probability. The method can effectively resist interferences such as synchronous forwarding and frequency hopping following, and improves the anti-interference capability of a communication or data link system.

Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.

The invention discloses a data alignment method and system, electronic equipment and a storage medium, and relates to the field of data processing. The method is applied to a transmission link with a plurality of data channels, and comprises the following steps: for each data channel, detecting whether a sampling edge of a clock signal is in a stable region of a transmission signal based on a preset training code at different delay times; if yes, and a latch value obtained based on the sampling edge under the current delay time belongs to a first set, recording the detection result as a first mark; otherwise, recording the detection result as a second mark; sorting the first marks of the data channels according to the sequence of the delay time to obtain a first continuous interval formed by the continuous first marks; acquiring a common delay time interval as a first common interval; and delaying the clock signal based on the delay time at the center of the first common interval so as to correct the phase deviation of any data channel in the transmission link.

The invention discloses a differential link alignment method and system, and relates to the field of data processing. The method comprises the following steps: under different delay times, judging whether a sampling edge of a clock signal is in a stable region of a differential link based on a training code; if yes, when a latch value obtained based on the sampling edge under the current delay time belongs to a first set, recording the judgment result as a first mark; otherwise, recording the judgment result as a second mark; arranging the first mark and the second mark according to the sequence of the delay time to obtain a mark set; in the mark set, screening out a middle mark of any first interval or second interval; and delaying the clock signal or the differential link based on the delay amount corresponding to the intermediate mark so as to realize data alignment of the differential link. Based on the processing, the sampling edge of the clock signal after data alignment can be prevented from being in the hopping region.

A lock-detection circuit detects whether a first clock signal is frequency locked to a second clock signal. A lock-detection scheme that continuously evaluates the lock condition between the clock signals and as programmable frequency-offset tolerances for reporting lock acquisition and loss. A quadrature clock generator produces two periodic signals from the first clock signal. The periodic signals are in quadrature, which is to say they are misaligned with one another by ninety degrees. These quadrature signals are sampled on edges of the second clock signal to produce a sequence of states that exhibit a Gray-code progression if first and second clock signals are locked. Errors in the Gray-code progression indicate whether edges of the first clock signal are early or late with respect to the second clock signal. The lock-detection circuit is adjustable to indicate loss of lock under in dependence upon the temporal spacing of errors.

The invention relates to an interface circuit, a memory controller and a method for correcting a plurality of signal processing devices in an interface circuit of a memory controller. The method comprises the following steps: negotiating an operation mode of the interface circuit in a correction program with a host device in a link program; and correcting a characteristic value of the first signal processing device and a characteristic value of the second signal processing device in the correction program, in which the first signal processing device is arranged on a received signal processing path for processing a received signal, and the second signal processing device is arranged on a transmitted signal processing path for processing a transmitted signal, and the interface circuit operates in the correction program according to the operation mode.

The invention provides a method for detecting a channel-associated clock and routing equipment, and the method comprises the steps that a service board receives a channel-associated clock signal sent by a main control board, generates a periodic trigger signal according to the channel-associated clock signal, and sends the periodic trigger signal to a local reference clock domain, enabling the local reference clock domain to take the received adjacent periodic trigger signals as statistical cycles, obtaining local reference clock counts of a plurality of statistical cycles, and judging whether the corresponding associated clock signals are abnormal or not according to the obtained local reference clock counts of the plurality of statistical cycles. Through the method, anomaly detection can be carried out on the channel associated clock signal without additionally arranging a hardware circuit.

A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable / disable vector Q[1:N] that can turn on / off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.

A method and an apparatus are provided in which at least one data slicer of a receiver samples a signal based on a clock sampling position to obtain a first data sample and a second data sample. An integrator of the receiver integrates the signal from the first data sample to the second data sample to generate an integrated voltage. A first data slicer of the receiver samples the integrated voltage at a time of the second data sample to obtain an integrated sample. A phase detector of the receiver determines whether the clock sampling position requires adjustment based on a sign of the integrated sample.

This application discloses a simplified clock error detection method, apparatus, device, storage medium, and product under a flexible oversampling factor, relating to the field of clock error detection technology. The method includes: performing complex sign-deduction processing on the received signal to obtain a sign result; and querying a preset clock error mapping table based on the sign result to obtain the clock error. Since this application performs complex sign-deduction processing on the received signal to obtain a sign result, and then queries a preset clock error mapping table based on the sign result to obtain the clock error, compared to existing digital timing error detectors with excessively high computational complexity, the above method of this application can eliminate multiplication operations in existing clock error detection, reducing power consumption and computational resources.

This application provides a link adjustment circuit. The link adjustment circuit comprises a link status circuit and a phase locked loop control circuit, wherein the link status circuit is configured to obtain a signal transmitted in a data channel circuit; the link status circuit is further configured to obtain link status information based on the obtained signal; the link status circuit is further configured to determine, based on the link status information, that a rate of a link needs to be changed; the phase locked loop control circuit is configured to: when the link status circuit determines that the rate of the link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate, wherein the target phase locked loop is an unused phase locked loop in at least two phase locked loops; the link status circuit is further configured to detect that the link enters a rate-changing state; and the phase locked loop control circuit is further configured to switch a currently used phase locked loop to the target phase locked loop when the link status circuit detects that the link enters the rate-changing state.

Embodiments of this application disclose a phase detection method, a phase detection circuit, and a clock recovery apparatus. The method includes: receiving a first signal, and deciding a (2M-1) level of the first signal to obtain a decision result, where the first signal is a (2M-1)-level signal, and M is a positive integer; obtaining a response amplitude parameter of a transmission channel; extracting clock phase information in the first signal based on the first signal, the decision result, and the response amplitude parameter; and determining output clock phase information based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods. According to the foregoing method, a stable phase detection gain can be achieved when a clock phase is tuned to a pulse response edge.

An inference unit (1033) predicts as a prediction parameter value, a future parameter value of a time synchronization parameter used for time synchronization calculation which is calculation for synchronizing times of two devices. When a measured parameter value which is a measured value corresponding to the prediction parameter value is generated with elapse of time, a cumulative distribution table generation unit (1034) calculates as a prediction error, a difference between the measured parameter value and the prediction value. A cumulative probability calculation unit (1036) calculates an abnormality degree indicating possibility that an abnormality is included in the measured parameter value, using the prediction error.

This application provides a frequency offset correction method and a communication apparatus, and relates to the field of wireless communication technologies. In this application, a signal energy loss can be reduced, interference can be reduced, and demodulation performance can be improved. The method includes: A second device performs down-conversion by using a first local oscillator signal, to receive a first reference signal from a first device, and adjusts the first local oscillator signal based on a receiving result of the first reference signal, to obtain a second local oscillator signal, where a frequency offset of the second local oscillator signal is less than a frequency offset of the first local oscillator signal. The second device performs down-conversion by using the second local oscillator signal, to receive a first data signal from the first device, where a guard band of the first reference signal is greater than a guard band of the first data signal.

This invention discloses a signal receiving method, a signal receiving device, and a communication system. The signal receiving method includes: receiving a command feedback signal, the command feedback signal including a start bit and information bits following the start bit; generating a detection signal based on the command feedback signal, the detection signal including multiple detection windows opened after the end position of the start bit, the multiple detection windows corresponding one-to-one with multiple transition edges of the information bits, and the position of the (n+1)th detection window being determined based on the transition edge detected within the nth detection window, where n is a positive integer. This invention determines the position of the (n+1)th detection window by using the transition edge detected within the nth detection window, thereby reducing the offset between the detection window and the transition edge, and preventing the offset of the detection window from accumulating, thus significantly improving the data reception success rate.

This application relates to data correction and phase optimization in high-speed receivers. In some implementations, a system for performing data correction includes an analog-to-digital converter (ADC) configured to receive differential data from a continuous-time linear equalizer (CTLE) and generate a bitstream including a plurality of data bits and a corresponding plurality of data symbol bits, a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block, and data correction circuitry. In some implementations, the data correction circuitry is configured to receive the bitstream from the ADC, determine whether to correct a data symbol bit, flip the data symbol bit in response to determining that the data symbol bit is to be corrected, and provide the plurality of data symbol bits including the flipped data symbol bit to the DFE.