93results about "Synchronisation error detection" patented technology

Systems and methods are described that enable user terminals to eliminate or reduce the number of dummy bursts (or bursts with no data) they send. The systems and methods use two burst detectors, a first burst detector that analyzes the physical structure of the signal, and a second burst detector that analyzes the informational structure of the signal. Output from the first burst detector can be used to control operation of a signal decoder that decodes received signals. The second burst detector analyzes output from the signal decoder to determine the second burst indicator. In other words, the first burst detector can be implemented prior to decoding the received signal to provide a first estimate related to the presence or absence of a burst. This can then be used to limit the amount of processing performed by the signal decoder.

The application discloses a frame synchronization-based laser communication and ranging integrated system, and belongs to the technical field of satellite laser communication.The system solves the problem that ranging precision is limited under the condition of low communication rate.The system comprises a sending end and a receiving end, wherein the sending end comprises a synchronization header sequence generating module, a data sequence generating module and a framing module, the receiving end comprises a synchronization sliding correlation / rough ranging calculation module, a fine ranging calculation module and a data sequence extracting module; the synchronization header sequence generating module generates a synchronization header sequence, the data sequence generating module generates a data sequence, and the framing module completes splicing of the synchronization header sequence and the data sequence; the synchronization sliding correlation / rough ranging calculation module performs frame synchronization and calculates an integer symbol period of transmission delay, the fine ranging calculation module calculates a fractional symbol period of transmission delay, and the data sequence extracting module performs frame disassembly according to a starting position of the synchronization header sequence, extracts the data sequence and completes communication reception.

According to an aspect of an embodiment, a method may include assigning an activation window by an optical line terminal during a portion of an upstream transmitting window in a passive optical network (PON). The method may include performing a first modification to a first upstream transmission. The method may include performing a second modification to a second upstream transmission. The method may include receiving the first upstream transmission from a first optical network unit (ONU) during the activation window, the first ONU synchronized in the PON. The method may include receiving a second upstream transmission from a second ONU during the activation window, the second ONU requesting activation in the PON.

A method and a circuitry to perform clock and data recovery, CDR is provided. The method includes the steps of obtaining an analogue communication signal characterized by a symbol frequency Fsymbol; and performing an analogue-to-digital conversion of the analogue communication signal according to a sampling rate Fsample targeting Fsymbol*(M / L) thereby obtaining a digital signal. The method includes up-sampling the digital signal by L; filtering the up-sampled digital signal with filter coefficients of a finite impulse response, FIR, filter to perform a fractionally-spaced equalisation; and down-sampling the filtered digital signal by M resulting in a recovered digital signal. Intermediate filter coefficients are obtained for the FIR filter and a phase error is determined based on the recovered digital signal. The intermediate filter coefficients are interpolated based on the phase error to compensate for the phase error, resulting in interpolated filter coefficients; and the filter coefficients of the FIR filter are updated with the interpolated filter coefficients.

This application provides a frequency offset correction method and a communication apparatus, and relates to the field of wireless communication technologies. The method includes: A second device performs down-conversion by using a first local oscillator signal, to receive a first reference signal from a first device, and adjusts the first local oscillator signal based on a receiving result of the first reference signal, to obtain a second local oscillator signal, where a frequency offset of the second local oscillator signal is less than a frequency offset of the first local oscillator signal. The second device performs down-conversion by using the second local oscillator signal, to receive a first data signal from the first device, where a guard band of the first reference signal is greater than a guard band of the first data signal.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

The invention relates to the technical field of signal processing, and discloses a time slot control method and system for an inter-satellite link time division communication system, and the method comprises the steps: carrying out the clock domain crossing synchronization and jitter elimination processing of a pulse per second signal inputted externally, and detecting the validity of the processed pulse per second signal; extracting a time error between a local clock and an external clock based on the second pulse signal after validity detection; performing continuous health detection on the time error to generate a health state indication; performing second-order filtering processing on error information by referring to the health state indication and the time error, taking a processing result as an adjustment amount of a frequency control word of an NCO counter, and driving the NCO counter to generate a time reference; and detecting whether an external pulse per second signal is subjected to slip adjustment or not, and distributing a time slot control signal by using the time reference. Accurate distribution of time information is achieved, misreading of externally input time information is avoided, and the adaptive capacity of the system under different working conditions is improved.

The invention relates to the technical field of equipment synchronous calibration, and particularly discloses a synchronous calibration method based on multi-equipment control, which comprises the following steps: designing a calibration board card, and counting equipment which is connected with the calibration board card and needs to be subjected to synchronous calibration; any two devices are controlled to communicate, time delay generated in the process that a signal reaches a receiving device from a sending device in the communication process is obtained, and a matrix T is generated after all combinations are traversed; performing operation on the matrix T to obtain a matrix C; calculating the average number of each row of the matrix C, and obtaining the maximum value in the average number; and taking the difference value between the maximum value and the average corresponding to the equipment as the time delay required to be compensated by the equipment. According to the invention, synchronization of signal sending / receiving of the equipment can be realized based on the time point of signal sending / receiving of the equipment.

Example embodiments describe a method and a circuitry to perform clock and data recovery, CDR. The method comprises the steps of obtaining an analogue communication signal characterized by a symbol frequency Fsymbol; performing an analogue-to-digital conversion of the analogue communication signal according to a sampling rate Fsample targeting Fsymbol *(M / L) thereby obtaining a digital signal; up-sampling the digital signal by L; filtering the up-sampled digital signal with filter coefficients of a finite impulse response, FIR, filter to perform a fractionally-spaced equalisation; down-sampling the filtered digital signal by M resulting in a recovered digital signal; obtaining intermediate filter coefficients for the FIR filter; determining a phase error based on the recovered digital signal; interpolating the intermediate filter coefficients based on the phase error to compensate for the phase error, resulting in interpolated filter coefficients; and updating the filter coefficients of the FIR filter with the interpolated filter coefficients.

Methods and systems for performing data correction and phase optimization are disclosed herein. In some implementations, a system for performing data correction comprises: an analog to digital converter (ADC) configured to receive differential data from a continuous time linear equalizer (CTLE) and generate a bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits; a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block; and data correction circuitry. In some implementations, the data correction circuitry is configured to: receive the bitstream from the ADC; determine whether to correct a data sign bit; responsive to determining the data sign bit is to be corrected, flip the data sign bit; and provide the plurality of data sign bits, including the flipped data sign bits, to the DFE.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

A method and an apparatus are provided in which at least one data slicer of a receiver samples a signal based on a clock sampling position to obtain a first data sample and a second data sample. An integrator of the receiver integrates the signal from the first data sample to the second data sample to generate an integrated voltage. A first data slicer of the receiver samples the integrated voltage at a time of the second data sample to obtain an integrated sample. A phase detector of the receiver determines whether the clock sampling position requires adjustment based on a sign of the integrated sample.

The present invention provides a synchronization circuit device and a method for generating a synchronization signal. The synchronization circuit device includes: a carrier frequency offset blind estimation circuit, which is configured to receive a multi-bit frequency domain data stream and a synchronization signal fed back from an address synchronization circuit, and output a first carrier frequency offset estimation value; a carrier frequency offset compensation circuit, which is configured to perform carrier frequency offset compensation on the received multi-bit frequency domain data stream according to the first carrier frequency offset estimation value, and output a frequency domain data stream without carrier frequency offset as a single bit; and an address synchronization circuit, which is configured to receive the frequency domain data stream without carrier frequency offset as a single bit, and output a synchronization signal.

A method and system for the post-adjustment (i.e., offline) of event timestamps to implement virtual time synchronization amongst detection node clocks. In existing methodologies with the goal of clock synchronization, clocks (and timestamps generated therefrom) are disciplined or adjusted at the recordation time of the events on a detection node (e.g., a switch / router, an Internet-of-Things (IoT) device, a wireless sensor, etc.). However, there is no particular reason for these clocks or timestamps to be accurate during the recordation time, but rather, should be accurate at their use or interpretation time. Further, through these recordation time adjustments, clock drifts and timing errors may be gradually introduced, leading to runaway inaccuracies. The disclosed method and system intentionally avoids the disciplining of clocks at event recordation times on the detection node and, instead, adjusts timestamps during interpretation times, to overcome the aforementioned issues.

The invention provides a signal synchronization method and device based on phase shift keying and a spectrum analyzer, and relates to the technical field of signal synchronization. In the application, first, first frequency offset estimation can be performed on a to-be-synchronized signal to obtain a first frequency offset corresponding to the to-be-synchronized signal, and frequency offset compensation is performed on the to-be-synchronized signal based on the first frequency offset to obtain a first frequency offset compensation signal corresponding to the to-be-synchronized signal; secondly, performing second frequency offset estimation on the first frequency offset compensation signal to obtain a second frequency offset corresponding to the to-be-synchronized signal, and performing frequency offset compensation on the to-be-synchronized signal based on the second frequency offset to obtain a second frequency offset compensation signal corresponding to the to-be-synchronized signal; and then, outputting a synchronization signal based on the second frequency offset compensation signal to obtain a target synchronization signal corresponding to the to-be-synchronized signal. Based on the above content, the problem of poor signal synchronization effect in the prior art can be improved.

The embodiment of the invention relates to a baud rate detection method and device, equipment and a storage medium. The method comprises the following steps: receiving interval section signals, recording interval transmission duration, and obtaining a preliminary baud rate according to the interval transmission duration; under the condition that the preliminary baud rate has the adjacent baud rate, setting a sampling baud rate matched with the preliminary baud rate; receiving a synchronous section signal, and sampling the synchronous section signal according to the sampling baud rate to obtain synchronous sampling data; and determining a target baud rate in the preliminary baud rate and the adjacent baud rate according to the synchronous sampling data. According to the technical scheme provided by the embodiment of the invention, high-precision Baud rate detection is realized without a high-frequency timer, the number of Baud rates which can be compatible with a self-adaptive Baud rate communication system is increased, and the operation resources and hardware cost of the system are saved.

The present application discloses a time synchronization method, device, storage medium and slave, the method comprising: determining a first time signal corresponding to the time information according to the time information of the received host, and determining the first moment information corresponding to the start synchronization moment in the first time signal, obtaining a second time signal in the slave, and determining the second moment information corresponding to the start synchronization moment in the second time signal; determining the time error between the first moment information and the second moment information; determining the signal parameter of the second time signal, dividing the time error into a plurality of sub-time errors according to the signal parameter; adjusting the second time signal of the slave after the start synchronization moment according to the plurality of sub-time errors, so that the second time signal is synchronized with the first time signal. The present application can avoid the situation that the device cannot be recognized due to the sudden change of the signal in the slave, and can also improve the accuracy of time synchronization.

The application discloses a data alignment method and system, an electronic device and a storage medium, and relates to the field of data processing. The method is applied to a transmission link with multiple data channels, and comprises the following steps: for each data channel, at different delay times, detecting whether the sampling edge of a clock signal is in a stable region of a transmission signal based on a preset training code; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the detection result as a first flag; otherwise, recording the detection result as a second flag; sorting the first flags of the data channels according to the order of the delay times to obtain a first continuous interval formed by continuous first flags; obtaining a common delay time interval as a first common interval; and delaying the clock signal based on the delay time at the center of the first common interval to correct the phase deviation of any data channel in the transmission link.

Data equalization system, featuring: a data clock input configured to receive a clock signal; an input node which is to be operated in such a way that it receives a data signal of transmission symbols which change their state synchronously with the clock signal; a first branch which is connected to the input node; and a second branch configured to receive a modification of the data signal, wherein at least one of a weighting of the first branch and a weighting of the second branch is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

At least some aspects of the present disclosure provide for a method (500). In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal (510) and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result (520). The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages (525). The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts (535) and applying second equalization to the received data signal based on the determined relationship among the plurality of counts (540).

The invention discloses a data decoding device, method and system, and the method comprises the steps: a rising edge detection module receives a level signal which is transmitted by an LIN controller and corresponds to an original data flow, and transmits a first enabling signal to a falling edge detection module when detecting that the level signal is switched from a first level to a second level within a first set time period, the falling edge detection module is controlled to start to receive the level signal; and after the falling edge detection module receives the first enable signal, the timing module is controlled to start timing, and when the timing of the timing module does not reach a time threshold and the level signal is detected to be switched from the second level to the first level, a target data stream corresponding to the level signal is sent to the conversion device. According to the invention, the rising edge detection module, the falling edge detection module and the timing module are used for detecting the level signal corresponding to the original data stream of the LIN bus data link layer, the data stream corresponding to the synchronous interval segment with variable length is screened out, the decoding cost is reduced, and the decoding flexibility is improved.

The invention discloses a signal receiving method, a signal receiving device and a communication system. The signal receiving method comprises the steps that a command feedback signal is received, and the command feedback signal comprises a start bit and an information bit behind the start bit; generating a detection signal based on the command feedback signal, the detection signal comprising a plurality of detection windows opened after an end position of the start bit, the plurality of detection windows being in one-to-one correspondence with a plurality of jump edges of the information bit, the position of the (n + 1) th detection window is determined according to the jump edge detected in the nth detection window, and n is a positive integer. According to the technical scheme, the position of the (n + 1) th detection window is determined through the jump edge detected in the nth detection window, so that the offset of the detection window and the jump edge can be reduced, the offset of the detection window cannot be accumulated, and the data receiving success rate is greatly improved.

The invention discloses a very simple clock error detection method and device under a flexible oversampling factor, equipment, a storage medium and a product, and relates to the technical field of clock error detection, and the method comprises the steps: carrying out the complex number symbol processing of a received signal, and obtaining a symbol result; and querying a preset clock error mapping table based on the symbol result to obtain a clock error. According to the method, the received signal is subjected to complex number symbol processing to obtain the symbol result, and the preset clock error mapping table is queried based on the symbol result to obtain the clock error. Compared with an existing digital timing error detector with too high calculation complexity, the digital timing error detector has the advantages that multiplication in existing clock error detection can be eliminated, and power consumption and calculation resources are reduced.

The present invention relates to an interface circuit, a memory controller, and a method for calibrating multiple signal processing devices within an interface circuit of a memory controller. The method includes: negotiating an operating mode of the interface circuit in a calibration process with a host device during a link process; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device during the calibration process, wherein the first signal processing device is configured on a receive signal processing path to process a receive signal, and the second signal processing device is configured on a transmit signal processing path to process a transmit signal, and the interface circuit operates according to the operating mode during the calibration process.

The signal synchronization method, device and spectrum analyzer based on phase shift keying provided by this application relate to the technical field of signal synchronization. In this application, first, a first frequency offset estimation can be performed on the signal to be synchronized to obtain the first frequency offset corresponding to the signal to be synchronized, and frequency offset compensation can be performed on the signal to be synchronized based on the first frequency offset to obtain the first frequency offset compensation signal corresponding to the signal to be synchronized; secondly, a second frequency offset estimation can be performed on the first frequency offset compensation signal to obtain the second frequency offset corresponding to the signal to be synchronized, and frequency offset compensation can be performed on the signal to be synchronized based on the second frequency offset to obtain the second frequency offset compensation signal corresponding to the signal to be synchronized; then, the output of the synchronization signal can be performed based on the second frequency offset compensation signal to obtain the target synchronization signal corresponding to the signal to be synchronized. Based on the above content, the problem of poor signal synchronization effect existing in the prior art can be improved.

Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

The invention provides a synchronization method and device, equipment, a storage medium and a program product, and relates to the technical field of wireless, the method is applied to an accelerator card, the accelerator card is inserted into a server through a golden finger of a communication interface, and the method comprises the following steps: processing a first PP1S signal of a GNSS by using a two-stage clock circuit to obtain a first pulse signal; according to the first pulse signal, synchronization information is generated, and the synchronization information comprises a frame header, a frame number, a time slot header and a time slot number; sending the frame header and the frame number to an active antenna unit (AAU), and sending the frame number, the time slot header and the time slot number to the server through the communication interface; the frame header and the frame number are used for the AAU to perform clock synchronization, and the frame number, the time slot header and the time slot number are used for the server to perform clock synchronization. Therefore, the acceleration card can obtain the stable pulse signal so as to provide stable synchronization information for the server and the AAU, and synchronization of the server, the AAU and the acceleration card is realized.

The application discloses a differential link alignment method and system, and relates to the field of data processing. The method comprises the following steps: judging whether the sampling edge of a clock signal is in a stable region of a differential link based on a training code at different delay times; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the judgment result as a first flag; otherwise, recording the judgment result as a second flag; arranging the first flag and the second flag according to the order of the delay times to obtain a flag set; screening out a middle flag of any first interval or second interval in the flag set; and delaying the clock signal or the differential link based on the delay amount corresponding to the middle flag, so as to realize data alignment of the differential link. Based on the above processing, the sampling edge of the clock signal after data alignment can be prevented from being in a jump region.

Technologies for periodic and synchronous phase error detection and compensation are described. An integrated circuit includes a clock source to generate a clock signal having a first frequency, and an analog-to-digital converter (ADC) to sample an incoming signal to obtain data samples using a sampling clock. The data samples include a periodic and synchronous phase error caused by the clock signal. The periodic and synchronous phase error has a harmonic of the first frequency. The integrated circuit also includes a signal processing circuit coupled to the ADC and the clock source. The signal processing circuit includes a harmonic phase correction block to detect and compensate for the periodic and synchronous phase error in the data samples to obtain corrected data samples.

A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.