90 results about "Fixed-point arithmetic" patented technology

The invention discloses a data output method and device based on fixed-point number extraction and a storage medium, and relates to the technical field of computers, and the method comprises the steps: carrying out the calculation and normalization processing of a non-zero positive number of an input value through a precision formula, and generating a valid number corresponding to the non-zero positive number; querying in a compression lookup table according to a compression index corresponding to the effective number to obtain a reciprocal square root approximate value corresponding to the effective number; performing iterative optimization, index parity adjustment, remainder feedback correction and boundary specialization processing on the basis of a reciprocal square root approximate value corresponding to the effective number to generate an effective result; and carrying out reverse normalization processing on the effective result, generating a fixed point number corresponding to the effective result, and outputting the fixed point number. According to the invention, through conversion between the fixed-point number form and the effective number form, the technical problem of distributed environment amplification errors in a fixed-point number extraction algorithm in related technologies is solved, and the performance and accuracy of fixed-point number extraction are improved.

The invention relates to the technical field of artificial intelligence, in particular to an operation method and an arithmetic unit based on a Point data format.The method comprises the steps that sign bits, exponential expansion bits, mantissa bits and exponential bits of the Point data format are obtained, all the positions of the Point data format are preprocessed, a bit width distribution priority rule is defined, and a bit width distribution priority rule is obtained; multiplying the two mantissa bits obtained by decoding to obtain a mantissa product and a mask sequence; determining a prepositive zero number of the mantissa product according to the mask sequence, and performing unified logic shift on the mantissa product; the method comprises the following steps: carrying out shift on a mantissa part, carrying out rounding operation on the shifted mantissa part, converting a mantissa product into a fixed-point number format according to a sign bit, an exponential expansion bit and an exponential bit, carrying out additive operation based on the fixed-point number, and outputting an accumulation result. The circuit area and power consumption are reduced, complex time sequence control is not needed, and logic resource consumption is reduced.

The invention relates to the technical field of computers, and provides a texture coordinate processing method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving at least one first texture coordinate and a plurality of groups of precision parameters, wherein the first texture coordinate is a floating-point number; for each first texture coordinate, the plurality of groups of precision parameters are used to convert the first texture coordinate to obtain a plurality of second texture coordinates, and the second texture coordinates are fixed point numbers; and for a plurality of second texture coordinates obtained by converting each first texture coordinate, determining the precision difference between each second texture coordinate and a reference value corresponding to the second texture coordinate, and determining the second texture coordinate with the maximum precision difference with the reference value as the texture coordinate obtained by processing. The method can reduce the number of iterations, reduce the data processing cost, and improve the processing efficiency of texture coordinates.

The invention relates to a fractional order PID (Proportion Integration Differentiation) control method and system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of: 1, setting fractional order PID related parameters according to the requirements of a controlled object; 2, calculating a fractional order calculus weight coefficient according to the fractional order PID related parameters, and storing the fractional order calculus weight coefficient in the FPGA; 3, collecting a state feedback signal of the controlled object, and calculating an integral term operator and a differential term operator; step 4, calculating control output and performing amplitude limiting processing, and updating the state of the controlled object by using the control output after the amplitude limiting processing; and 5, repeating the steps 1-4 to realize fractional order PID closed-loop control. By optimizing a discrete convolution algorithm, adopting a parallel pipeline architecture and configurable parameter design and combining fixed-point number operation and security boundary constraint, the numerical stability and hardware security of the system under high-speed operation are ensured, the calculation speed is remarkably increased while the operation precision is ensured, and the method is suitable for large-scale popularization and application. And the method is suitable for control occasions with extremely high real-time requirements.

An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation corresponding to each of layers constituting a neural network and output an arithmetic operation result; an analysis unit configured to perform, for each of division units obtained by dividing the arithmetic operation result by one or more units, an analysis according to the arithmetic operation result belonging to the division unit, and output an analysis result for each division unit; a decimal point position determination unit configured to determine a decimal point position indicating a dynamic range for each division unit on the basis of the analysis result for each division unit output by the analysis unit; and a quantization unit configured to perform quantization on the arithmetic operation result to become fixed-point data having a decimal point position determined for the division unit to which the arithmetic operation result belongs.

The embodiment of the invention provides a data processing method, which comprises the following steps of: converting an e index calculation task into an index calculation task aiming at a target fixed point number, and splitting the index calculation task aiming at the target fixed point number into a shift task and index calculation aiming at a target decimal part, an index calculation task aiming at the target decimal part is approximate to linear function calculation (namely addition and multiplication based on calculation parameters), so that the calculation process can be greatly simplified, and simple multiplication and addition are executed by utilizing a digital signal processor based on the calculation parameters corresponding to the target decimal part; compared with the prior art, the method has the advantages that operation steps and required computing resources are reduced, all computing resources of one digital signal processor are fully utilized in the process, the whole task process can be performed in series, judgment branches and data rereading do not exist, the overall computing efficiency is improved, and hardware resource consumption is reduced.

The invention discloses a lightweight fault diagnosis model compression method based on channel pruning and quantization fusion, relates to the technical field of data processing, and comprises the following steps: training and preparing a fault diagnosis model; l1 regularization is introduced in the model training process, and the weight of a convolutional layer is constrained; after the training is finished, screening out a preset percentage convolution kernel with the lowest contribution degree according to the L1 norm of the convolution kernel, and obtaining a pruned fault diagnosis model; a 8-bit fixed-point quantification method is adopted for the pruned fault diagnosis model, floating-point parameters in the fault diagnosis model are converted into 8-bit fixed-point numbers to be expressed, and the pruned and quantized fault diagnosis model is obtained; and carrying out fine tuning on the fault diagnosis model after pruning and quantification, and carrying out iterative training on the fault diagnosis model by using the training set. According to the method, the fault diagnosis model is pruned by introducing L1 regularization, a low-contribution convolution kernel can be removed, the model is simplified, and in addition, the accuracy of the model can be ensured in the re-simplification process.

One or more embodiments of the specification provide a data processing method and device applied to a database system. After triggering a data type conversion task, the data processing method obtains a to-be-converted floating point number of the data type conversion task, converts the to-be-converted floating point number into a first floating point number represented by an extended precision, and then calculates a second floating point number scaled to a preset numerical interval through multiple loop integer calculations to perform accurate rounding. According to whether the decimal part of the intermediate value of the last loop integer calculation and the distance between the upper interval and the lower interval of the last loop integer calculation are both greater than the error value of the last loop integer calculation, in the case of satisfying the error value of the last loop integer calculation, the second floating point number is converted into a fixed point number according to the integer part of the intermediate value of each loop integer calculation and the rounding result of the last loop integer calculation, to serve as the execution result of the data type conversion task.

The invention provides a floating point index operation method, a tensor processor, equipment and a storage medium. The floating point index operation method comprises the following steps: converting a first equation into a second equation taking 2 as a bottom and taking a target floating point number multiplied by a reciprocal of ln2 as an index, and obtaining an integer term of an index of the second equation; obtaining a first decimal item of an index of the second equation, splitting the first decimal item into a fixed-point number item and a first floating-point number item, and obtaining a first index operation result corresponding to the fixed-point number item from a preset table; calculating a second exponential operation result of the integer term and multiplying the first exponential operation result by the second exponential operation result to obtain an initial natural exponential operation result of the target floating-point number; and performing Taylor expansion calculation on the first floating-point number item to obtain a third exponential operation result, and multiplying the initial natural exponential operation result of the target floating-point number by the third exponential operation result. According to the embodiment of the invention, the floating point index operation efficiency can be improved on the premise of ensuring the floating point index operation precision.

This application relates to a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point number division. The method includes: obtaining a fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; mapping the first value and the second value to a preset fixed-point format respectively to obtain a third value and a fourth value represented by the preset fixed-point format, wherein the data convergence efficiency of the preset fixed-point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated; extracting a value of a preset bit width starting from the least significant bit of the fourth value, and determining the extracted value as a fifth value; performing iterative calculation on the third value and the fifth value until the current value meets a first preset condition, and stopping the iterative calculation; and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation. This can improve the efficiency of fixed-point number division calculation.

The application relates to the field of artificial intelligence, and discloses a neural network model running method, readable medium and electronic equipment. The method comprises the following steps: detecting a first operation in the process of running a neural network model, the first operation comprising a first operation part, and the first operation part comprising at least one nonlinear operation factor; obtaining first input data of the first operation from a first data matrix; generating first lookup table parameters of the first input data; determining a first index value corresponding to the first lookup table parameters in an index table, obtaining a first lookup table result corresponding to the first index value in the index table, wherein the first lookup table parameters, the first index value and the first lookup table result are fixed-point numbers; and determining an operation result of the first operation part based on the first lookup table result. Thus, the electronic equipment can obtain the fixed-point number operation result of the first operation through linear operation and lookup table when running the first operation, and the speed of running the neural network model of the electronic equipment is improved.

The present application relates to trailing or leading digit predictors. A method and a leading zero predictor for estimating the number of leading zeros in the result of a fixed-point arithmetic operation, accurate to within one bit of any signed fixed-point number. The leading zero predictor comprises an input encoding circuit that generates an encoded input string from the fixed-point number; a window-based proxy string generation circuit that generates a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string.

The invention discloses an SDFT high-precision fast signal processing method and system based on linear convolution. The method comprises the following five steps: (1) obtaining the total sample number of a discrete signal x (n) to be transformed, and recording the total sample number as N; (2) a data type conversion step, namely converting the discrete signal x (n) from a double-precision floating point type into a fixed point number with a longer data bit; (3) constructing a complex number convolution kernel 1, a complex number convolution kernel 2 and a phase compensation factor by adopting a fixed point number according to the total sample number N; (4) a linear convolution step, namely linear convolution of the convolution kernel 1 and the convolution kernel 2, and taking effective linear convolution as an output frequency spectrum; and (5) a phase compensation step: performing phase compensation on the frequency spectrum obtained in the step (4) by using a phase compensation factor to obtain SDFT of the input signal x (n). Compared with an existing SDFT fast transformation processing method, the calculation precision of the method is improved by three orders of magnitude.

The invention relates to a scaling-free CORDIC optimization structure based on fractional time division constant multiplication, and belongs to the technical field of hardware implementation. Comprising a fractional time division multi-constant multiplication optimization framework; unifying a discrete angle iteration architecture; the multi-constant multiplication shares a calculation structure; a rapid angle selection and compensation mechanism; the fixed-point data format is matched with the platform. According to the method, high-precision multiplication-free calculation is realized, hardware resource occupation is reduced, and the delay lifting speed is shortened.

The application provides an image target recognition method, comprising: inputting images in an image set into a trained floating-point deep neural network model, and obtaining a value range of floating-point numbers output by each hidden layer of the floating-point deep neural network model; determining parameters in an asymmetric quantization relationship between the floating-point numbers output by each hidden layer of the floating-point deep neural network model and fixed-point numbers according to the value range of the floating-point numbers output by each hidden layer of the floating-point deep neural network model and in combination with a target bit width value of the fixed-point numbers after quantization; determining the asymmetric quantization relationship between the floating-point numbers output by each hidden layer and the fixed-point numbers as: after each hidden layer of the floating-point deep neural network model, an output floating-point number corresponding to each hidden layer is replaced by an asymmetric quantization relationship between the output floating-point number and the fixed-point number to obtain a fixed-point neural network model; inputting a to-be-detected image into the fixed-point neural network model, converting the floating-point numbers output by each hidden layer in the fixed-point neural network model into fixed-point numbers, and completing image target recognition.

The invention provides an RANS entropy coding method, system and equipment, and the method achieves the high parallelism and rapid calculation while solving the state dependence through an interleaving pipeline and a fixed-point number shift multiplication lossless replacement division method, enables the time needed by coding to be remarkably reduced, greatly improves the throughput, achieves the full utilization of hardware resources, and improves the coding efficiency. Meanwhile, when high-resolution images are coded, the compression rate loss of the method can be basically ignored, and the method is suitable for a depth image compression neural network.

The invention provides a WiFi network digital down-conversion system which comprises a multi-phase mixer and a resampling filter. The multi-phase mixer is used for converting a high-speed digital band-pass signal into a low-speed mode so as to realize digital down-conversion (DDC) on an FPGA (Field Programmable Gate Array) platform; and the resampling filter is used for reducing the sampling rate and removing unwanted frequency spectrum components to generate a complex baseband frequency spectrum. The multi-phase mixer PM of the present invention employs a parallel coordinate rotation digital computer (CORDIC) processor and a low pass filter array to reduce high speed data rates while minimizing resource utilization. The resampling filter comprises a cascade integral combination (CIC) filter and a multi-channel pulse finite impulse response (FIR) filter, optimal hardware cost is achieved, a floating point data type is converted into a fixed point data type, and resources are remarkably saved.

Technologies for compilers that implement non-power of two Fast Fourier Transform (FFT) algorithms are described. The non-power of two FFT algorithm uses a recursive function to generate a hardware design of a set of compute blocks of a fixed-point digital signal processor (DSP) and routing data between the compute blocks. The compiler receives input specifying a sequence of indexes and a bit width of the fixed-point DSP and performs a process. The process splits the sequence using a recursive loop, determines a number of multiplications in the hardware design, and generates a trace graph of the non-power of two FFT algorithm. The process is entered via the recursive function and exists when the recursive loop decrements to a specified value corresponding to a Radix-3 or Radix-2. The compiler outputs data, including the hardware design, the number of multiplications in the hardware design, and the trace graph.

A design method for a fixed-point and floating-point adder includes: S1, performing fixed-point and floating-point identification by a shared mantissa addition module; S2, for fixed-point numbers, performing low-bit calculation in the shared mantissa addition module; configuring a fixed-point number processing module, saving a carry of a highest bit in low-bit calculation results, and transmitting the saved carry to the fixed-point number processing module to obtain a fixed-point number addition result; S3, for floating-point numbers, performing calculation, in the shared mantissa addition module, on mantissas of the floating-point numbers, configuring a floating-point number processing module, and performing exponent matching and normalization on exponents of the floating-point numbers to obtain a normalized result; obtaining a floating-point number addition result according to sign bits of the floating-point numbers, the exponents subjected to the exponent matching and the normalized result; and S4, transmitting the result to an output module, and outputting the result.

The embodiment of the invention discloses a multi-data-type multiplier and a method for realizing multiplication of multiple types of data, relates to the technical field of digital integrated circuits, and is convenient for realizing the multiplier supporting data operation of multiple data types at lower cost, so that the area of the integrated circuit and power consumption resources are saved. The method comprises the following steps: basic multiplication units of at least two data types, wherein the basic multiplication units are used for realizing mantissa part or fixed-point number multiplication of floating-point numbers of predetermined data types through combinational operation; the control unit is used for selecting basic multiplication unit combinations of different data types according to the data types of the input matrix; the input matrix is decomposed into a plurality of parts, and the parts are respectively transmitted to corresponding basic multiplication units for operation; and performing shift and accumulation operation on the operation result of each part. The method is suitable for an integrated circuit design scene.

The invention discloses a method for realizing a general exponential lookup table supporting floating point type data, which belongs to the field of integrated circuit digitalities and comprises the following steps of: firstly, solving a lookup value of the exponential lookup table; log2 is taken from the table lookup numerical value to calculate a data storage address of the lookup table; performing table lookup on an exponential lookup table by using the calculated address and the next address; solving an interpolation coefficient; converting the interpolation coefficient represented by the fixed-point number into a floating-point number format; and performing linear interpolation calculation to obtain a final output result. When the address and the interpolation coefficient are calculated, an integer simulation floating point operation is adopted, so that floating point calculation units are greatly reduced, and the consumption of hardware resources is reduced. The method based on the lookup table is adopted, so that the universality is enhanced, and the calculation speed is increased.

The invention relates to a multi-input floating-point number additive operation framework and method, and the framework comprises at least two input data caching modules which are used for carrying out the grouping caching of input floating-point numbers according to the size range of the index values of the input floating-point numbers, and then carrying out the parallel output of the input floating-point numbers; the floating point pair order adder tree is used for converting the floating point number into a fixed point number and carrying out parallel summation calculation based on a fixed point pair order adder; the data path selector is used for selecting a group of floating-point numbers and transmitting the floating-point numbers to the floating-point pair-order adder tree; the at least two result accumulation cache modules are associated with the at least two input data cache modules in a one-to-one correspondence manner and are used for performing grouped fixed-point number accumulation and cache on the fixed-point number calculation results; the dislocation addition calculation module is used for carrying out dislocation addition on the cache output data of all the result accumulation cache modules to obtain a fixed point number summation result; and the fixed-point-to-floating-point module is used for converting a fixed-point number summation result into a floating-point number. The floating point calculation precision is high, the circuit structure is simple, and the operation speed is high.

The invention discloses an integral simulation method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining an integral input value of the simulation, the integral input value of the simulation being a difference value between a current speed and a target speed of a vehicle; on the basis of the integral input value of the simulation and a preset simulation step size, determining an integral increment of the simulation, the preset simulation step size being represented by a decimal fixed-point number; and determining the integral output value of the simulation based on the integral increment of the simulation and the integral output value of the previous simulation. In this way, the simulation precision requirement of the model can be met, the integral operation precision is improved, and therefore the precision of the whole PID algorithm and the simulation control precision of the vehicle speed are improved.

Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and / or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.

The present disclosure relates to the technical field of computers, and provides a texture coordinate processing method and device, electronic equipment and storage medium. The method comprises: receiving at least one first texture coordinate and a plurality of sets of precision parameters, the first texture coordinate being a floating-point number; for each first texture coordinate, converting the first texture coordinate using the plurality of sets of precision parameters to obtain a plurality of second texture coordinates, the second texture coordinates being fixed-point numbers; for the plurality of second texture coordinates obtained by converting each first texture coordinate, determining the precision gap between each second texture coordinate and a reference value corresponding to the second texture coordinate, and determining the second texture coordinate with the largest precision gap with the reference value as the processed texture coordinate. The method can reduce the number of iterations, reduce data processing costs, and improve the processing efficiency of texture coordinates.

The invention belongs to the field of computer part manufacturing, and particularly discloses an NAND type content addressable memory circuit and an operation method. The circuit comprises an NAND type analog content addressable memory array, a pre-charging circuit and a comparator circuit. The input fixed-point number is compared with the stored fixed-point number bit by bit, a discharge path is formed according to a comparison result, and a word line load capacitor discharges through the path to obtain a corresponding word line voltage; and the voltage is input into the comparator circuit, and finally a data comparison result is output. According to the method, the size comparison of fixed-point numbers can be efficiently realized in parallel, the calculation complexity is greatly reduced, and the calculation rate is improved. In a big data or artificial intelligence application scene needing large-scale data comparison, a large amount of calculation overhead can be saved, and the calculation speed is improved.

The present application relates to a data compression method, device, electronic device, and storage medium, and relates to the field of wireless communication technology. The method includes: obtaining data to be compressed, and obtaining a compression bit width C, wherein the data to be compressed is data retransmitted each time under a hybrid automatic repeat request mechanism, and the data to be compressed is a floating-point number after a noise whitening operation is performed, and the compression bit width C is determined based on the current hardware itself, and the compression bit width C is smaller than the effective bit width of the current hardware; converting the data to be compressed from a floating-point number to a fixed-point number to obtain a fixed-point number corresponding to the data to be compressed; and compressing the fixed-point number corresponding to the data to be compressed based on the compression bit width C to obtain compressed data. In this way, the fixed-point number corresponding to the data to be compressed can be compressed based on the compression bit width C, thereby reducing the storage space occupied by the data retransmitted each time under the hybrid automatic repeat request mechanism, thereby achieving the purpose of reducing hardware costs.

An embodiment of the present application provides an embedded AI-based power grid waveform dynamic bit width adaptive preprocessing method, system, and medium, the method comprising: acquiring real-time sampling data of voltage and current, analyzing the sampling accuracy of the real-time sampling data; setting a sampling accuracy threshold, and determining whether the sampling accuracy is greater than the sampling accuracy threshold; if greater than the sampling accuracy threshold, performing Q-format fixed-point conversion on the real-time sampling data, and normalizing the real-time sampling data after the Q-format fixed-point conversion; if less than or equal to, converting the real-time sampling data into normalized data using a LUT lookup method; inputting the normalized sampling data into a quantization model, outputting the data bit width, generating a bit width adjustment strategy based on the set bit width threshold, and dynamically adjusting the data bit width. The data preprocessing efficiency is improved through Q-format fixed-point conversion and the LUT lookup method, memory usage is reduced, and adaptive preprocessing can be performed according to acquisition signals of different bit widths.

The invention provides a partial product decoupling-based dynamic precision approximate multiplication implementation method and a multiplier, and the multiplier comprises a significance evaluation unit which splits a first operand and a second operand into high digits and low digits, and correspondingly generates a first amplitude and a second amplitude; different precision instructions are generated based on the amplitudes and the threshold values; the dynamic precision unit performs zero setting processing on the second low digit based on the precision instruction to form an approximate number, and calculates a partial product of the first high digit and the approximate number; the accurate calculation unit accurately calculates products of the other three parts; and the final addition unit sums the products of the four parts according to the weight. The calculation unit can be used for constructing or optimizing a multiplication calculation array in a neural network hardware accelerator, is particularly suitable for scenes with dense fixed-point number operation such as convolution, and performs efficient approximate operation on the input fixed-point number through a data driving mechanism by utilizing the common sparsity and amplitude difference characteristics of neural network data, so that the calculation efficiency is improved. And self-adaptive management of power consumption is realized.

The invention provides a memristor-based fixed-point matrix FFT (Fast Fourier Transform) calculation method, which belongs to the technical field of signal processing and image processing, and comprises the following steps of: firstly, constructing a non-linear voltage controlled memristor model, simulating a state conversion behavior in logic operation through a dynamic regulation mechanism, and realizing the function of a basic logic gate; according to the method, an FFT algorithm based on matrix block optimization is designed, FFT calculation is decomposed into small-scale matrix operation units, calculation efficiency is optimized in combination with a Kronecker product and an arrangement matrix, FFT operation with higher point number is expanded in a recursion mode, meanwhile, a full adder and a multiplier are designed based on a memristor, efficient fixed-point number operation is achieved, and finally, the FFT calculation efficiency is improved. The method is applied to image FFT processing, and a processing result is obtained. The scheme of the invention has higher calculation efficiency and lower energy consumption while ensuring the calculation precision, can be widely applied to the fields of image processing, signal analysis, scientific calculation and the like, and has important practical value and application prospect.