141 results about "Fixed-point arithmetic" patented technology

The invention discloses a data output method and device based on fixed-point number extraction and a storage medium, and relates to the technical field of computers, and the method comprises the steps: carrying out the calculation and normalization processing of a non-zero positive number of an input value through a precision formula, and generating a valid number corresponding to the non-zero positive number; querying in a compression lookup table according to a compression index corresponding to the effective number to obtain a reciprocal square root approximate value corresponding to the effective number; performing iterative optimization, index parity adjustment, remainder feedback correction and boundary specialization processing on the basis of a reciprocal square root approximate value corresponding to the effective number to generate an effective result; and carrying out reverse normalization processing on the effective result, generating a fixed point number corresponding to the effective result, and outputting the fixed point number. According to the invention, through conversion between the fixed-point number form and the effective number form, the technical problem of distributed environment amplification errors in a fixed-point number extraction algorithm in related technologies is solved, and the performance and accuracy of fixed-point number extraction are improved.

The invention provides a nonlinear activation function rapid calculation device and method based on a coefficient lookup table, and the device comprises an input selection unit which is used for selecting an input floating-point number; the coefficient lookup table unit is used for dividing the whole region of the activation function into a plurality of intervals and dividing a non-infinite interval into a plurality of sections; carrying out approximation on each section by using a quadratic function so as to establish a coefficient lookup table; the preprocessing unit is used for performing feature extraction on the floating-point number to obtain a sign bit, an order code and a mantissa; the operation unit is used for calculating an index value and a second mantissa subsegment; obtaining a corresponding quadratic function coefficient in a coefficient lookup table according to the index value; obtaining a value of a quadratic polynomial based on the second mantissa sub-segment, a corresponding quadratic function coefficient and fixed-point number multiplication and addition operation; and the post-processing output unit is used for normalizing the value of the quadratic polynomial and outputting a value in a floating-point number format in combination with the sign bit and the order code of the floating-point number, so that the problem that the calculation speed of the activation function is relatively low is solved.

The embodiment of the invention provides an embedded AI power grid waveform dynamic bit width adaptive preprocessing method and system and a medium, and the method comprises the steps: obtaining the real-time sampling data of voltage and current, and analyzing the sampling precision of the real-time sampling data; setting a sampling precision threshold, and judging whether the sampling precision is greater than the sampling precision threshold; if the sampling precision is greater than the sampling precision threshold value, performing Q-format fixed-point number conversion on the real-time sampling data, and performing normalization processing on the real-time sampling data after the Q-format fixed-point number conversion; if the real-time sampling data is smaller than or equal to the real-time sampling data, converting the real-time sampling data into normalization by adopting an LUT table look-up method; normalized sampling data is input into a quantitative model, data bit width is output, a bit width adjustment strategy is generated based on a set bit width threshold value, the data bit width is dynamically adjusted, the data preprocessing efficiency is improved through Q format fixed-point and LUT lookup methods, memory occupation is reduced, and self-adaptive preprocessing can be conducted according to collected signals of different bit widths.

The invention relates to the technical field of artificial intelligence, in particular to an operation method and an arithmetic unit based on a Point data format.The method comprises the steps that sign bits, exponential expansion bits, mantissa bits and exponential bits of the Point data format are obtained, all the positions of the Point data format are preprocessed, a bit width distribution priority rule is defined, and a bit width distribution priority rule is obtained; multiplying the two mantissa bits obtained by decoding to obtain a mantissa product and a mask sequence; determining a prepositive zero number of the mantissa product according to the mask sequence, and performing unified logic shift on the mantissa product; the method comprises the following steps: carrying out shift on a mantissa part, carrying out rounding operation on the shifted mantissa part, converting a mantissa product into a fixed-point number format according to a sign bit, an exponential expansion bit and an exponential bit, carrying out additive operation based on the fixed-point number, and outputting an accumulation result. The circuit area and power consumption are reduced, complex time sequence control is not needed, and logic resource consumption is reduced.

The invention relates to the technical field of computers, and provides a texture coordinate processing method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving at least one first texture coordinate and a plurality of groups of precision parameters, wherein the first texture coordinate is a floating-point number; for each first texture coordinate, the plurality of groups of precision parameters are used to convert the first texture coordinate to obtain a plurality of second texture coordinates, and the second texture coordinates are fixed point numbers; and for a plurality of second texture coordinates obtained by converting each first texture coordinate, determining the precision difference between each second texture coordinate and a reference value corresponding to the second texture coordinate, and determining the second texture coordinate with the maximum precision difference with the reference value as the texture coordinate obtained by processing. The method can reduce the number of iterations, reduce the data processing cost, and improve the processing efficiency of texture coordinates.

The invention relates to a fractional order PID (Proportion Integration Differentiation) control method and system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of: 1, setting fractional order PID related parameters according to the requirements of a controlled object; 2, calculating a fractional order calculus weight coefficient according to the fractional order PID related parameters, and storing the fractional order calculus weight coefficient in the FPGA; 3, collecting a state feedback signal of the controlled object, and calculating an integral term operator and a differential term operator; step 4, calculating control output and performing amplitude limiting processing, and updating the state of the controlled object by using the control output after the amplitude limiting processing; and 5, repeating the steps 1-4 to realize fractional order PID closed-loop control. By optimizing a discrete convolution algorithm, adopting a parallel pipeline architecture and configurable parameter design and combining fixed-point number operation and security boundary constraint, the numerical stability and hardware security of the system under high-speed operation are ensured, the calculation speed is remarkably increased while the operation precision is ensured, and the method is suitable for large-scale popularization and application. And the method is suitable for control occasions with extremely high real-time requirements.

The invention discloses an FPGA-based target detection model acceleration design method, and relates to the technical field of computer vision. The acceleration design method comprises the steps that a block RAM is adopted as a feature map cache unit, DDR4 data provided by peripheral equipment are converted into stream data at the input end of the feature map cache unit, and the stream data are stored in a line scanning mode; before the feature map is input into convolution processing, the feature map is processed through a quantization operation unit, and floating-point number data is converted into fixed-point data; and inputting the quantized feature map and the model weight into a convolution operation unit to execute convolution operation, caching the feature map into a row buffer area in rows in each convolution in the convolution operation unit, and multiplying the feature map with a weight matrix position by position and adding the feature map. According to the method, ZYNQ is adopted as a hardware platform, the target detection algorithm is accelerated and optimized through a software and hardware collaborative design method, the operation speed of the target detection algorithm is improved, and the accuracy of target detection is ensured.

The embodiment of the invention provides a calculation method and device of an embedded system, equipment and a storage medium, and the method comprises the steps: responding to a time sequence prediction demand through the embedded system, and obtaining the time sequence data of home equipment; if the floating-point number exists in the time sequence data, converting the floating-point number in the time sequence data into a fixed-point number to obtain to-be-processed time sequence data; obtaining a bias result obtained by performing bias processing on the to-be-processed time sequence data by the upper computer; and obtaining an activation function result contrast relationship from the upper computer, and obtaining time sequence prediction data corresponding to the offset result based on the activation function result contrast relationship. By optimizing the calculation method of the LSTM network, the speed of outputting the result is effectively improved, and then the prediction speed of the home equipment on time sequence prediction and the processing speed of the home equipment on natural language are improved.

An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation corresponding to each of layers constituting a neural network and output an arithmetic operation result; an analysis unit configured to perform, for each of division units obtained by dividing the arithmetic operation result by one or more units, an analysis according to the arithmetic operation result belonging to the division unit, and output an analysis result for each division unit; a decimal point position determination unit configured to determine a decimal point position indicating a dynamic range for each division unit on the basis of the analysis result for each division unit output by the analysis unit; and a quantization unit configured to perform quantization on the arithmetic operation result to become fixed-point data having a decimal point position determined for the division unit to which the arithmetic operation result belongs.

The embodiment of the invention provides a data processing method, which comprises the following steps of: converting an e index calculation task into an index calculation task aiming at a target fixed point number, and splitting the index calculation task aiming at the target fixed point number into a shift task and index calculation aiming at a target decimal part, an index calculation task aiming at the target decimal part is approximate to linear function calculation (namely addition and multiplication based on calculation parameters), so that the calculation process can be greatly simplified, and simple multiplication and addition are executed by utilizing a digital signal processor based on the calculation parameters corresponding to the target decimal part; compared with the prior art, the method has the advantages that operation steps and required computing resources are reduced, all computing resources of one digital signal processor are fully utilized in the process, the whole task process can be performed in series, judgment branches and data rereading do not exist, the overall computing efficiency is improved, and hardware resource consumption is reduced.

The invention discloses a lightweight fault diagnosis model compression method based on channel pruning and quantization fusion, relates to the technical field of data processing, and comprises the following steps: training and preparing a fault diagnosis model; l1 regularization is introduced in the model training process, and the weight of a convolutional layer is constrained; after the training is finished, screening out a preset percentage convolution kernel with the lowest contribution degree according to the L1 norm of the convolution kernel, and obtaining a pruned fault diagnosis model; a 8-bit fixed-point quantification method is adopted for the pruned fault diagnosis model, floating-point parameters in the fault diagnosis model are converted into 8-bit fixed-point numbers to be expressed, and the pruned and quantized fault diagnosis model is obtained; and carrying out fine tuning on the fault diagnosis model after pruning and quantification, and carrying out iterative training on the fault diagnosis model by using the training set. According to the method, the fault diagnosis model is pruned by introducing L1 regularization, a low-contribution convolution kernel can be removed, the model is simplified, and in addition, the accuracy of the model can be ensured in the re-simplification process.

The invention relates to a real-time laser radar point cloud 3d mapping method implemented on an FPGA (Field Programmable Gate Array), which is compatible with accuracy, efficiency and power consumption, and constructs a laser radar point cloud coordinate conversion algorithm based on the parallel capability of the FPGA to realize the acceleration processing of laser radar data coordinate conversion by the FPGA; violent nearest neighbor search with a nearest neighbor threshold value introduced is used as a nearest neighbor calculation method; the FPGA configures a processing element array for parallel calculation of the distance between point pairs according to a violent nearest neighbor search optimization data cache architecture with a nearest neighbor threshold introduced, and the violent nearest neighbor search is accelerated by hardware; the FPGA executes a P2P-ICP algorithm, point cloud alignment is carried out through violent nearest neighbor search, attitude parameters are generated, then the generated attitude parameters are used as attitude priori estimation, and Gaussian-Newton algorithm iteration is carried out through an improved ICP stage to obtain a final attitude; and the FPGA adopts a laser radar data processing mode of fixed-point number operation.

The invention discloses a post-training quantization method of a variable granularity ViTs model based on an abnormal value, electronic equipment and a storage medium, which can reduce quantization loss and improve model performance. The method comprises the following steps: 1, converting a floating-point number into a low-order fixed-point number in a quantization process; 2, a # imgabs 0 # Transformer block serves as a reconstruction unit, calculation of a quantization error is defined as # imgabs 1 #, # imgabs 2 # and # imgabs 3 # represent input activation and quantization of the # imgabs 4 # Transformer block respectively, # imgabs 5 # and # imgabs 6 # represent weights and quantization of the # imgabs 7 # Transformer block respectively, # imgabs 8 # represents expectation, # imgabs 9 # represents a Frobenius norm, and # imgabs 10 # represents a quantization function of the # imgabs 11 # Transformer block; and 3, calculating gradient estimation of rounding operation by adopting a straight-through estimator during back propagation.

One or more embodiments of the specification provide a data processing method and device applied to a database system. After triggering a data type conversion task, the data processing method obtains a to-be-converted floating point number of the data type conversion task, converts the to-be-converted floating point number into a first floating point number represented by an extended precision, and then calculates a second floating point number scaled to a preset numerical interval through multiple loop integer calculations to perform accurate rounding. According to whether the decimal part of the intermediate value of the last loop integer calculation and the distance between the upper interval and the lower interval of the last loop integer calculation are both greater than the error value of the last loop integer calculation, in the case of satisfying the error value of the last loop integer calculation, the second floating point number is converted into a fixed point number according to the integer part of the intermediate value of each loop integer calculation and the rounding result of the last loop integer calculation, to serve as the execution result of the data type conversion task.

The invention provides a floating point index operation method, a tensor processor, equipment and a storage medium. The floating point index operation method comprises the following steps: converting a first equation into a second equation taking 2 as a bottom and taking a target floating point number multiplied by a reciprocal of ln2 as an index, and obtaining an integer term of an index of the second equation; obtaining a first decimal item of an index of the second equation, splitting the first decimal item into a fixed-point number item and a first floating-point number item, and obtaining a first index operation result corresponding to the fixed-point number item from a preset table; calculating a second exponential operation result of the integer term and multiplying the first exponential operation result by the second exponential operation result to obtain an initial natural exponential operation result of the target floating-point number; and performing Taylor expansion calculation on the first floating-point number item to obtain a third exponential operation result, and multiplying the initial natural exponential operation result of the target floating-point number by the third exponential operation result. According to the embodiment of the invention, the floating point index operation efficiency can be improved on the premise of ensuring the floating point index operation precision.

This application relates to a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point number division. The method includes: obtaining a fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; mapping the first value and the second value to a preset fixed-point format respectively to obtain a third value and a fourth value represented by the preset fixed-point format, wherein the data convergence efficiency of the preset fixed-point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated; extracting a value of a preset bit width starting from the least significant bit of the fourth value, and determining the extracted value as a fifth value; performing iterative calculation on the third value and the fifth value until the current value meets a first preset condition, and stopping the iterative calculation; and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation. This can improve the efficiency of fixed-point number division calculation.

The application relates to the field of artificial intelligence, and discloses a neural network model running method, readable medium and electronic equipment. The method comprises the following steps: detecting a first operation in the process of running a neural network model, the first operation comprising a first operation part, and the first operation part comprising at least one nonlinear operation factor; obtaining first input data of the first operation from a first data matrix; generating first lookup table parameters of the first input data; determining a first index value corresponding to the first lookup table parameters in an index table, obtaining a first lookup table result corresponding to the first index value in the index table, wherein the first lookup table parameters, the first index value and the first lookup table result are fixed-point numbers; and determining an operation result of the first operation part based on the first lookup table result. Thus, the electronic equipment can obtain the fixed-point number operation result of the first operation through linear operation and lookup table when running the first operation, and the speed of running the neural network model of the electronic equipment is improved.

The embodiment of the invention discloses a privacy-protecting method and device for performing index operation by combining two parties. The method is executed by any one party, and comprises the following steps: firstly, based on a first local-party fragment corresponding to a target index held by the local party, obtaining a second local-party fragment corresponding to a target operation result between the target index and a base number 2 through local calculation and interaction with the other party; wherein the first local fragment and the second local fragment belong to a first fixed-point number ring and a second fixed-point number ring respectively, and the modulus q of the later fixed-point number ring is smaller than the modulus 2L of the former fixed-point number ring. Then, the second local fragment is converted back to a first fixed point number ring, specifically, based on a result obtained by negation operation on the first bit of the second local fragment and a result obtained by peer-to-peer operation of the other party, safe multiplication calculation is carried out, and a third local fragment is obtained; performing negation operation on the fragment to obtain a bit fragment for the carry bit; and updating the second local fragment based on the bit fragment, the modulus q and the digit L.

The present application relates to trailing or leading digit predictors. A method and a leading zero predictor for estimating the number of leading zeros in the result of a fixed-point arithmetic operation, accurate to within one bit of any signed fixed-point number. The leading zero predictor comprises an input encoding circuit that generates an encoded input string from the fixed-point number; a window-based proxy string generation circuit that generates a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string.

The invention discloses an SDFT high-precision fast signal processing method and system based on linear convolution. The method comprises the following five steps: (1) obtaining the total sample number of a discrete signal x (n) to be transformed, and recording the total sample number as N; (2) a data type conversion step, namely converting the discrete signal x (n) from a double-precision floating point type into a fixed point number with a longer data bit; (3) constructing a complex number convolution kernel 1, a complex number convolution kernel 2 and a phase compensation factor by adopting a fixed point number according to the total sample number N; (4) a linear convolution step, namely linear convolution of the convolution kernel 1 and the convolution kernel 2, and taking effective linear convolution as an output frequency spectrum; and (5) a phase compensation step: performing phase compensation on the frequency spectrum obtained in the step (4) by using a phase compensation factor to obtain SDFT of the input signal x (n). Compared with an existing SDFT fast transformation processing method, the calculation precision of the method is improved by three orders of magnitude.

The invention relates to a scaling-free CORDIC optimization structure based on fractional time division constant multiplication, and belongs to the technical field of hardware implementation. Comprising a fractional time division multi-constant multiplication optimization framework; unifying a discrete angle iteration architecture; the multi-constant multiplication shares a calculation structure; a rapid angle selection and compensation mechanism; the fixed-point data format is matched with the platform. According to the method, high-precision multiplication-free calculation is realized, hardware resource occupation is reduced, and the delay lifting speed is shortened.

The application provides an image target recognition method, comprising: inputting images in an image set into a trained floating-point deep neural network model, and obtaining a value range of floating-point numbers output by each hidden layer of the floating-point deep neural network model; determining parameters in an asymmetric quantization relationship between the floating-point numbers output by each hidden layer of the floating-point deep neural network model and fixed-point numbers according to the value range of the floating-point numbers output by each hidden layer of the floating-point deep neural network model and in combination with a target bit width value of the fixed-point numbers after quantization; determining the asymmetric quantization relationship between the floating-point numbers output by each hidden layer and the fixed-point numbers as: after each hidden layer of the floating-point deep neural network model, an output floating-point number corresponding to each hidden layer is replaced by an asymmetric quantization relationship between the output floating-point number and the fixed-point number to obtain a fixed-point neural network model; inputting a to-be-detected image into the fixed-point neural network model, converting the floating-point numbers output by each hidden layer in the fixed-point neural network model into fixed-point numbers, and completing image target recognition.

The invention provides an RANS entropy coding method, system and equipment, and the method achieves the high parallelism and rapid calculation while solving the state dependence through an interleaving pipeline and a fixed-point number shift multiplication lossless replacement division method, enables the time needed by coding to be remarkably reduced, greatly improves the throughput, achieves the full utilization of hardware resources, and improves the coding efficiency. Meanwhile, when high-resolution images are coded, the compression rate loss of the method can be basically ignored, and the method is suitable for a depth image compression neural network.

In general, techniques are described for optimizations to resolver-to-digital signal converters. Processing circuitry comprising a delta-sigma analog-to-digital converter and a fixed-point signal processor may perform the techniques. The delta-sigma analog-to-digital converter may be communicatively coupled to a fixed-point digital signal processor and electrically coupled to a resolver sensor attached to a rotating element controlled by the processing circuitry, where the delta-sigma analog-to-digital converter is configured to obtain, based on electrical interactions with the resolver sensor, a digital cosine value for an indirectly sensed angle of the rotating element and a digital sine value for the indirectly sensed angle of the rotating element. The fixed-point digital signal processor may be configured to implement a fixed-point Luenberger Observer resolver-to-digital converter configured to obtain, based on the digital sine value and the digital cosine value, via fixed-point mathematical operations, an approximate angle of the rotating element.

The invention provides a WiFi network digital down-conversion system which comprises a multi-phase mixer and a resampling filter. The multi-phase mixer is used for converting a high-speed digital band-pass signal into a low-speed mode so as to realize digital down-conversion (DDC) on an FPGA (Field Programmable Gate Array) platform; and the resampling filter is used for reducing the sampling rate and removing unwanted frequency spectrum components to generate a complex baseband frequency spectrum. The multi-phase mixer PM of the present invention employs a parallel coordinate rotation digital computer (CORDIC) processor and a low pass filter array to reduce high speed data rates while minimizing resource utilization. The resampling filter comprises a cascade integral combination (CIC) filter and a multi-channel pulse finite impulse response (FIR) filter, optimal hardware cost is achieved, a floating point data type is converted into a fixed point data type, and resources are remarkably saved.

Technologies for compilers that implement non-power of two Fast Fourier Transform (FFT) algorithms are described. The non-power of two FFT algorithm uses a recursive function to generate a hardware design of a set of compute blocks of a fixed-point digital signal processor (DSP) and routing data between the compute blocks. The compiler receives input specifying a sequence of indexes and a bit width of the fixed-point DSP and performs a process. The process splits the sequence using a recursive loop, determines a number of multiplications in the hardware design, and generates a trace graph of the non-power of two FFT algorithm. The process is entered via the recursive function and exists when the recursive loop decrements to a specified value corresponding to a Radix-3 or Radix-2. The compiler outputs data, including the hardware design, the number of multiplications in the hardware design, and the trace graph.

A design method for a fixed-point and floating-point adder includes: S1, performing fixed-point and floating-point identification by a shared mantissa addition module; S2, for fixed-point numbers, performing low-bit calculation in the shared mantissa addition module; configuring a fixed-point number processing module, saving a carry of a highest bit in low-bit calculation results, and transmitting the saved carry to the fixed-point number processing module to obtain a fixed-point number addition result; S3, for floating-point numbers, performing calculation, in the shared mantissa addition module, on mantissas of the floating-point numbers, configuring a floating-point number processing module, and performing exponent matching and normalization on exponents of the floating-point numbers to obtain a normalized result; obtaining a floating-point number addition result according to sign bits of the floating-point numbers, the exponents subjected to the exponent matching and the normalized result; and S4, transmitting the result to an output module, and outputting the result.

The embodiment of the invention discloses a multi-data-type multiplier and a method for realizing multiplication of multiple types of data, relates to the technical field of digital integrated circuits, and is convenient for realizing the multiplier supporting data operation of multiple data types at lower cost, so that the area of the integrated circuit and power consumption resources are saved. The method comprises the following steps: basic multiplication units of at least two data types, wherein the basic multiplication units are used for realizing mantissa part or fixed-point number multiplication of floating-point numbers of predetermined data types through combinational operation; the control unit is used for selecting basic multiplication unit combinations of different data types according to the data types of the input matrix; the input matrix is decomposed into a plurality of parts, and the parts are respectively transmitted to corresponding basic multiplication units for operation; and performing shift and accumulation operation on the operation result of each part. The method is suitable for an integrated circuit design scene.

The invention discloses a method for realizing a general exponential lookup table supporting floating point type data, which belongs to the field of integrated circuit digitalities and comprises the following steps of: firstly, solving a lookup value of the exponential lookup table; log2 is taken from the table lookup numerical value to calculate a data storage address of the lookup table; performing table lookup on an exponential lookup table by using the calculated address and the next address; solving an interpolation coefficient; converting the interpolation coefficient represented by the fixed-point number into a floating-point number format; and performing linear interpolation calculation to obtain a final output result. When the address and the interpolation coefficient are calculated, an integer simulation floating point operation is adopted, so that floating point calculation units are greatly reduced, and the consumption of hardware resources is reduced. The method based on the lookup table is adopted, so that the universality is enhanced, and the calculation speed is increased.