376 results about "Word length" patented technology

An oversampling pulse oximeter includes an analog to digital converter with a sampling rate sufficient to take multiple samples per source cycle. In one embodiment, a pulse oximeter (100) includes two more more light sources (102) driven by light source drives (104) in response to drive signals from a digital signal processing unit (116). The source drives (104) may drive the sources (102) to produce a frequency division multiplex signal. The optical signals transmitted by the light sources (102) are transmitted through a patient's appendage (103) and impinge on a detector (106). The detector (106) provides an analog current signal representative of the received optical signals. An amplifier circuit (110) converts the analog current signal to an analog voltage signal in addition to performing a number of other functions. The amplifier circuit (110) outputs an analog voltage signal which is representative of the optical signals from the sources (102). This analog voltage signal is received by a fast A/D converter (112) which samples the analog voltage signal to generate a digital voltage signal which can be processed by the digital signal processing unit (116). The fast A/D converter (112) operates at a rate sufficient to take multiple samples per source cycle and may have a sampling frequency, for example, of over 41 kHz. The digital signal processing unit (116) implements software for averaging the samples over a source cycle for improved measurement consistency, improved signal to noise ratio and reduced A/D converter word length.

A method and apparatus for power management that controls the overflow of a digital combiner used in the transmit path for a broadband transceiver station (BTS) is disclosed. Power is managed by a digital word banking agent which is a part of the BTS system software. If a new channel request is received, the digital word banking agent determines if the request can be satisfied at the requested power level. Otherwise, the digital word banking agent determines if the channel request can be satisfied at a lower power request. The digital word banking agent also manages active channels by reclaiming power from channels requiring less power and/or by allocating more power to the channels requesting more power. If the digital word banking agent cannot satisfy a request, the digital word banking agent will queue the request for submission at a later time in the event that additional power becomes available.

A data optimization engine for deoptimizing selected frames of a first stream of data, comprising a receive interface circuit coupled to an optimization processor. The receive interface circuit is configured for receiving the first stream of data. The receive interface circuit includes a traffic controller circuit for separating frames in the first stream of data into a first deoptimizable frame and a first non-deoptimizable frame, and a deoptimization front-end circuit coupled to the traffic controller circuit to receive at least a first portion of the first deoptimizable frame. The deoptimization front-end circuit includes a protocol conversion circuit configured to convert data in the first portion of the first deoptimizable frame from a first protocol to a second protocol suitable for processing by the optimization processor, the first protocol specifies a first word length, the second protocol specifies a second word length different from the first word length, wherein the optimization processor is configured to deoptimize the first portion of the first deoptimizable frame by performing at least one of decompression and decryption on the first portion of the first deoptimizable frame.

Two versions of a variable word length encryption method are discussed. The methods are adapted for providing the means for long-term confidential transmission of printed characters, pictures, and voice dialogues over telephone lines or the Internet.

In a method of demodulating and decoding an encoded interleaved signal, a received encoded interleaved signal is demodulated, thereby producing soft-decision demodulated output words. Thereafter, the soft-decision demodulated output words are de-interleaved and scaled, thereby producing de-interleaved and scaled words. The scaling is performed for a plurality of successively demodulated output words at a time, thereby applying a scale factor that is substantially constant over the entire span of an interleaving frame. The de-interleaved and scaled words are word-length-reduced words. Finally, the de-interleaved and scaled words are decoded.

A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability.

A digital signal processing system for multiplexing/demultiplexing a large number of closely spaced FDM channels in which sub-band definition filtering divides the FDM spectral band comprised of "N" channels into "K" sub-bands in order to reduce the dimension of the polyphase filter fast Fourier transform structure required to complete the multiplexing/demultiplexing. This reduces the order of the required prototype filter by a factor proportional to K. The number of sub-bands K is chosen so that it is large enough to ensure the polyphase filter, fast Fourier transform structure for each sub-band is realizable within a finite word length, fixed point arithmetic implementation compatible with a low power consumption. To facilitate efficient sub-band definition filtering, the real basebanded composite signal is inputted at a spectral offset from DC equal to one quarter the FDM channel bandwidth for the N channels and the signal is sampled at a frequency 50% greater than the applicable Nyquist rate. The quarter band spectral offset and oversampling by 50% above the theoretical Nyquist rate facilitate the use of computationally efficient bandshift and symmetric half-band Finite Impulse Response (FIR) filtering.

Ranking search results, comprises receiving a query string; retrieving a plurality of search results that include a corresponding plurality of target strings that relate to the query string; segmenting the query string and each of the plurality of target strings; pairing segments in the query string with respective segments in the target strings to form a plurality of combinations; retrieving a plurality of weights that correspond to the plurality of combinations based on a mapping of word combinations and their respective weights, wherein a weight measures semantic correlation between words in a word combination; and determining a weighted word length based on the weights corresponding to each of the plurality of target strings; and ranking the plurality of target strings based on their respective weighted word lengths. Alternatively, ranking search results includes determining a minimum weight of each inserted word with respect to segmented words in the query string; determining a minimum weight of each deleted word with respect to segmented words in the target strings; determining a total edit distance based at least in part on the minimum weight of each inserted word and the minimum weight of each deleted word; and ranking the target strings based on the total edit distances.

The invention discloses a method for intelligently extracting labels from text. This method uses the Chinese word segmentation algorithm for text strings in memory to split keywords, and then calculates the weight of words based on word frequency, word length, part of speech, etc., sorts them in reverse order according to the weight of words, and takes a specified number of words as the result. output. The characteristic of this method is that all algorithms are processed in memory, the algorithm design is concise and efficient, and the analysis speed is effectively guaranteed. For a piece of text, after a series of processes such as word segmentation, weighting, word formation, filtering, and sorting, it has achieved a certain effect on the accuracy of the label. The invention can carry out independent packaging of algorithms and package of components, has certain universality, can be applied to all products that require text label extraction, and has certain universality in use.

The invention discloses a word segmentation method and a word segmentation device, and belongs to the field of information processing. The method comprises the following steps of performing word segmentation on a text to be subjected to the word segmentation to obtain a first text by using an nth-order Markov model; when the first text comprises a target word string, adding the target word string to a dictionary to obtain an updated dictionary, wherein the target word string is not stored in the dictionary, and the dictionary is used for storing all word strings and corresponding estimated probabilities; performing word segmentation on the first text to obtain a second text and a third text according to the updated dictionary and a preset algorithm by utilizing a forward maximum matching word segmentation method and a backward maximum matching word segmentation method respectively; selecting the text of which the word length expectation and the word length variance are consistent with preset rules from the second and third texts as a word segmentation result. According to the method, a conventional dictionary is updated only by adding new words into the conventional dictionary, so that the new words can be flexibly added on the premise of not increasing the word segmentation ambiguities.

A recognition ambiguity resolution method of a Chinese named entity belongs to the field of named entity extraction; the method comprises the following steps: (1) the invention adopts a feature induction to reduce a feature number, i.e., a classifier provided by the invention automatically selects a meaningful feature through training and learning; (2) after selecting the feature, an N-BEST best marking sequence is selected from the CRF (Conditional Random Field) model learning through a Viterbi algorithm, i.e., N marking sequences with maximum probability of an observation sequence are selected; (3) in consideration of an occurrence frequency and a word length of the Chinese named entity, the method disclosed by the invention adopts a modified greedy algorithm to implement the ambiguity resolution, thus the entity marking sequence is obtained.

Image compression methods for near-eye display systems that reduce the input bandwidth and the system processing resource are disclosed. High order basis modulation, dynamic gamut, light field depth sampling and image data word-length truncation and quantization aiming at matching the human visual system angular, color and depth acuity coupled with use of compressed input display enable a high fidelity visual experience in near-eye display systems suited for mobile applications at a substantially reduced input interface bandwidths and processing resources.

In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.

A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.

The present invention contemplates a method or cryptographic system for communicating securely over an insecure communication channel of the type which communicates a message from a transmitter to a receiver. The method includes the step of providing a finite filed serial-serial multiplication/reduction structure wherein an initial delay and clock-cycle are inherently independent of word length and wherein input operands are serially entered one digit at a time and the output result is computed serially one digit at a time, wherein the digit size can be one bit or more. As disclosed, the multiplication structure is scalable and a serial transfer reduces the bus width needed to transfer data back and forth between memory and a multiplication/reduction step. A finite field multiplication structure in which an operand multiplication and a finite field reduction are formulated as a serial-serial computation is also disclosed. Further, a digit serial-serial finite field multiplication/reduction method and structure as an integral operation in a cryptographic system is disclosed. In such methods and structures, the inherent word length independence of the initial delay is achieved by defining both operand multiplication and field reduction as serial-serial computation. In such computations, all of the numbers needed for the computation are fed serially one digit at a time. Therefore, the inter-connection between the memory module and the multiplier module need only to support the transfer of data one digit at a time.

A memory cell reconfiguration process is performed in accordance with the operational characteristic settings determined based upon the results of analysis and/or testing of memory cell operations. The memory circuit can include a plurality of memory cells and memory cell configuration controller. The memory cells store information associated with a variety of operations. The memory cell configuration controller coordinates selective enablement and disablement of each of the plurality of memory cells, which can be done on a subset or group basis (e.g., enables and/or disables memory cells on a word length or row by row basis). The address mapping can be adjusted so that the memory space appears continuous to external components. The memory cell configuration controller can also forward configuration information to upstream and/or downstream components that can adjust operations to compensate for the memory cell configuration (e.g., to prevent overflow).

A compressed data table is formed from an uncompressed data table by defining a code description bit structure having a code type and a run length of data items. The code type may be configured to identify byte-length data items, word-length data items and/or one or more user-specified data items. Each run of one or more byte-length, word-length or user-specified data items in the uncompressed data table is represented in the compressed data table with a code description bit structure having an appropriately configured code type and having its run length equal to the number of byte-length, word-length or user-specified data items in the run of one or more byte-length or word-length data items, and in the case of byte-length and word-length data items each code description bit structure is followed in the compressed data table by the one or more byte-length or word-length data items.

An RF transmitter filter for use in a wireless communication system is disclosed. The filter includes a waveform detector to detect a power level of a transmitted data stream on a symbol-by-symbol basis. The filter also includes a processor to select a combination of filter parameter values according to the power level. The RF transmitter filter selects and adjusts filter parameters (i.e., number of taps or filter length, word length, coefficient quantization, sampling rate, tap delay, sampling bits, etc.) based on signal waveform characteristics. The adjustments limit the transmitted bandwidth and allow transmitted signals to meet an emission mask, while still enabling a receiver to recover the correct sample values of transmitted symbols. The filter further includes a reconfigurable digital filter to filter the transmitted data stream according to the combination of filter parameters.