206 results about "Serial digital interface" patented technology

Serial Data Interface. A method of serial communication is provided with an integrated circuit. The operation of the integrated circuit is first interrupted on at least one input/output associated with the operation of the integrated circuit. Serial data is then transmitted over the at least one input/output, the operation of which was interrupted, and during the interruption thereof.

A system for controlling multiple strings of LEDs includes a group of LED driver ICs, each of which includes a current sense feedback (CSFB) sample latch for storing a digital representation of the forward-voltage drop across a controlled LED string. Each CSFB latch is coupled to a register within a serial lighting interface (SLI) bus that both originates and terminates at an interface IC. As the data on the SLI bus is shifted into the interface IC, the interface IC selects the CSFB word that represents the highest forward-voltage drop of any of the controlled LED strings, which is then used by the interface IC to generate a CSFB signal for setting the appropriate supply voltage for the controlled LED strings.

The invention discloses an interactive three dimensional graphic video visualization system. The system comprises a three dimensional scene creation module, a real-time video and information module, a real-time three dimensional rendering engine module and an interactive control module. The three dimensional scene creation module is used for creating various effect plug-ins of three dimensional models and light, textures and the like to generate scene template files; the real-time video and information module obtains multichannel contents of real-time videos, various words and data information needed during broadcasting, and transmits the contents to the real-time three dimensional rendering engine module through networks; the real-time three dimensional rendering engine module receives scene template files and real-time videos, various words and data information to generate real-time replaceable multiple dynamic three dimensional visualization scenes, and synchronously outputs the scenes to the interactive control module through a high definition-serial digital interface (HD-SDI) and a high definition multimedia interface (HDMI); and the interactive control module performs interactive operations to various contents and perspectives of the dynamic three dimensional visualization scenes through a gesture recognition mode. According to the interactive three dimensional graphic video visualization system, combined display and interaction of various information graphics in a three dimensional environment can be achieved.

A video conversion device, containing electronic circuitry for conversion of a High Definition Multimedia Interface (HDMI) signal fed through input terminal to a Serial Digital Interface (SDI) signal which is outputted through output terminals, is connected to a conventional video camera battery pack. The body has four L-shaped slideway formations to receive slides on a battery plate to form a push-on physical connection with the camera. One side of the body is recessed, with four lugs or slide formations complementary to the slideway formations, at the edges of the recess, to be fitted into the slideways formed in the base of the battery pack to the slideway slots in the conversion device, and the battery pack can be quickly fitted to the conversion device via a push-on connection. The battery pack supplies power to the circuitry of the conversion device through terminals which is then supplied to the camera.

A system for controlling multiple strings of LEDs includes a group of LED driver IC's, each of which includes a current sense feedback (CSFB) sample latch for storing a digital representation of the forward-voltage drop across a controlled LED string. Each CSFB latch is coupled to a register within a serial lighting interface (SLI) bus that both originates and terminates at an interface IC. As the data on the SLI bus is shifted into the interface IC, the interface IC selects the CSFB word that represents the highest forward-voltage drop of any of the controlled LED strings, which is then used by the interface IC to generate a CSFB signal for setting the appropriate supply voltage for the controlled LED strings.

The invention discloses a communication control protocol and a method for simultaneously transmitting a plurality of paths of real-time multimedia data streams by utilizing an identical high speed digital channel. Conventional transmission channels such as signal wires for composite video broadcast signals (CVBS), S-Video, serial digital interfaces (SDI), video graphics arrays, digital visual interfaces and the like all adopt the method for transmitting images in a point-by-point scanning way under the control of horizontal synchronization and field synchronization. In the communication control protocol and the method, a transmitter acquires mode control parameters such as the information of point frequency, horizontal synchronization, field synchronization, voice sampling frequency and the like required by real-time image and real-time voice playback, packages the mode control parameters into a control information packet, packages image data and voice data into an image data packet and a voice data packet respectively, adds media stream identifiers to the three data packets, and transmits the data packets to a receiver by the same digital channel. The receiver can recover the plurality of paths of real-time media streams from the three data packets according to an original mode or a new given mode, thereby realizing the simultaneous transmission of a plurality of paths of real-time images or real-time voices in the same digital transmission channel.

The invention discloses a high-definition video multi-service optical transceiver. A time division multiplexing technology is adopted, and a plurality of paths of high-definition serial digital interface (HDSDI) high-definition videos and a plurality of services are transmitted through a single fiber. The optical transmitter comprises a transmitter and a receiver. Each of the transmitter and the receiver comprises circuits such as a video processor, a memory, a clock recovery stabilization circuit and a singlechip. At least two paths of HDSDI high-definition video signal interfaces are arranged in each video processor. The transmitter is connected with the receiver through a core fiber. The transmitter performs locking and clock recovery on a plurality of paths of high-definition video code streams, extracts related video data and related control signals, accesses effective videos through the memory to realize frame synchronization, multiplexes synchronized signals such as effective high-definition video signals, analogue video signals, audio signals, data signals, network signals and telephone signals, and transmits the synchronized signals in form of optical signal at high speed. The receiver receives and converts the optical signals into electrical signals, demultiplexes the electrical signals to obtain each signal, and combines the effective high-definition video signals according to a required high-definition format for output.

The present invention provides methods and apparatus for passing an on-screen display (OSD) from a source device, such as a television terminal, to a sink device, such as a high definition television (HDTV), over a serial interface, such as an IEEE-1394 interface. The source device includes a tuner adapted for receiving an active isochronous MPEG data stream and graphic data for an OSD. A serial interface at the source device enables communication with a sink device. A processor at the source device detects an action requiring an OSD at the sink device. The source device also includes an MPEG encoder adapted for encoding the graphic data as an isochronous MPEG data stream carrying the OSD. The isochronous MPEG data stream carrying the OSD may then be passed to the sink device via the serial interface.

The invention provides an intelligent video security and protection system and a signal processing method thereof. The system comprises a video analysis front end and a central video server, wherein the video analysis front end comprises a video input interface, a control module and a video output interface; the video input interface is used for deserializing a high-speed SDI (Serial Digital Interface) video signal into a digital video stream signal meeting BT.656 standard; the control module is used for performing preprocessing and video behavior analysis on the digital video stream signal and outputting an IP (Internet Protocol) video stream signal; the video output interface is used for transmitting the IP video stream signal to the central video server. Compared with the prior art, the system and the method have the advantages that multiple targets and multiple rules can be effectively realized aiming at real-time high-definition video and the video behavior analysis is simultaneously performed. In addition, great use of stream line operation for an algorithm is realized apart from the use of the parallel processing characteristic of an FPGA (Field Programmable Gate Array), and the data throughput of processing is improved by using a mode that the speed is increased by reducing the area.

A video apparatus and a method for recognizing a digital interface thereof are disclosed. The method for recognizing the digital interface of the video apparatus enables a multimedia source to re-execute a high definition multimedia interface (HDMI) recognition to deal with errors when the multimedia source connected using the HDMI fails to recognize that the video apparatus supports the HDMI due to a cable connection error, an EDID recognition error, or an HDCP authentication error. The video apparatus determines whether or not a format of an input video signal is HDMI or DVI, and displays a result on a screen so that a user can recognize the format. As a result, the video apparatus enables a user to recognize whether or not the HDCP authentication error is occurred, and notifies the user of a method for improving the cause of the HDCP authentication error.

The invention discloses an image signal comprehensive processing device according to target tracking control. The image signal comprehensive processing device comprises a CCD TV tracking controller, a serial digital interface, a tracking computer and a servo device which are sequentially connected with one another. The CCD TV tracking controller comprises a CCD camera, a digital interface circuit and a tracking processor which are connected with one another. The tracking processor comprises a main control computer and an image data acquisition card which are connected with each other. The invention further discloses an implementation method of the image signal comprehensive processing device according to target tracking control. By means of the image signal comprehensive processing device and the implementation method thereof according to target tracking control, the problem that an acquired image can be easily disturbed by the factors such as illumination and new targets in a real-time scene is solved; meanwhile, the problem of irregular movement of moving targets or mutual sheltering among the targets in the target tracking process is solved, and accordingly an accurate target detection and tracking method with robustness and real-time performance is achieved.

The serial interface operable, for example, to facilitate high speed differential data transfer between integrated circuits provides level shifting of an incoming data signal using a switched capacitor technique which level shifts the common mode voltage with minimal attenuation and minimal reduction of bandwidths. The serial interface also includes a DC offset correction loop of the input data receiver path. The level shifting circuit operates by sensing the incoming common mode voltage of a differential data signal with a resistor divider and sampling the difference between the measured input common mode voltage and desired input differential voltages generated by a differential DAC in the DC offset correction loop on two small capacitors. The small capacitors are switched across larger in-signal-path capacitors cyclically, so that over time a charge will build up to give the desired level shift to shift the common mode voltage of the incoming signal to the level tolerable by low voltage high speed transistors in the receiving integrated circuit.

A test set for a server hard disk backplane comprises a complex programmable logic devices (CPLD) chip, and a hard disk fault location index system (SGPIO) bus interface, an inter-integrated circuit (I2C) bus interface and a serial interface which are connected onto the CPLD chip, wherein the serial interface is used for being connected with a personal computer, the SGPIO bus interface and the I2C bus interface are used for being respectively connected with corresponding interfaces on a server hard disk backplane to be tested, the personal computer can send the test program to the CPLD chip through the serial interface, the CPLD chip is used for correspondingly converting the received test program into an SGPIO bus data format and an I2C bus data format, and sending the two formats to the server hard disk backplane, so the SGPIO bus and the I2C bus of the server hard disk backplane to be tested are tested. The personal computer can be applied to testing the server hard disk back plane through the test set.

The invention relates to a high-definition SDI (Serial Digital Interface) digital video signal optical fiber transparent transmission device. The high-definition SDI digital video signal optical fiber transmission device comprises an SDI optical fiber transmission sending end and an SDI optical fiber transmission receiving end, wherein the SDI optical transmission sending end is used for converting an SDI high-definition digital video signal input by a user into an optical signal through signal processing, and transmitting the optical signal through an optical fiber medium; the SDI optical fiber transmission receiving end is used for receiving a high-speed serial optical signal transmitted by n optical fiber, reducing the optical signal into the SDI high-definition digital video signal through the signal processing, and outputting the SDI high-definition digital video signal to a video receiving end. The high-definition SDI digital video signal optical fiber transparent transmission device is compatible with the transmission of various SDI digital video formats, and has the advantages of high transmission instantaneity, large transmission bandwidth and high electromagnetic interference resistance.