142results about "Individual digits conversion" patented technology

The present application discloses a data decoding method and apparatus, an electronic device, and a storage medium. The method comprises: acquiring the clock rate of a single-channel clock; on the basis of the clock rate of the single-channel clock, sampling, at rising edges and falling edges of the single-channel clock, a data stream formed using Manchester encoding, and obtaining a plurality of pieces of sampling data; and decoding each piece of sampling data, and obtaining decoded data of the data stream. According to the data decoding method provided by embodiments of the present application, clock resources required to be occupied when the Manchester-encoded data is decoded can be reduced while improving the decoding efficiency.

The invention discloses a DALI (Digital Addressable Lighting Interface) data frame decoding method for Manchester encoding, which solves the problems of poor universality and high bit error rate caused by a fixed clock in the traditional method. The method comprises the following steps: receiving a DALI frame containing a start bit, a data bit and a stop bit; identifying a start bit, measuring the low level length of the start bit for multiple times, taking extreme values Tmax and Tmin, and checking the ratio (1lt; tmax / Tminlt, Tmax / Tminlt; 1 + n) and then T = (Tmax + Tmin) / 2 is calculated; setting two judgment intervals [T-nT, T + nT) and [2T-nT, 2T + nT) (0lt; nlt; 0.5) judging that the duration of the adjacent jump edge is T or 2T; counting edge overturning times in a 2T window from the middle moment of a data bit, keeping a logic value unchanged in two times, and performing negation in one time; and a stop position is detected through 4T in a non-jump manner. Through dynamic time sequence calibration and adaptive decoding, the decoding reliability in a complex environment is improved, the bit error rate is reduced, and the stability and universality of data transmission of the intelligent lighting system are enhanced.

An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.

The invention discloses a Manchester encoding communication verification system, and relates to the field of encoding, the Manchester encoding communication verification system comprises a core ECU and a plurality of edge ECUs, each edge ECU is internally provided with an SPI controller and is connected with a voltage conversion circuit of an MOSI end and a current conversion circuit of an MISO end; the edge ECU translates Manchester data to be sent into an SPI byte number cache through the CPU core, performs matching verification on an external level signal, and determines a fault source according to a result; the SPI controller takes over SPI byte data according to the request, and sends and receives data according to a preset coding frequency; the DMA controller reads the cached SPI byte data during sending and sends the cached SPI byte data to the SPI controller, and the SPI controller inputs an external level signal during receiving and calls and caches the external level signal through the DMA controller. According to the scheme, the characteristic that the SPI and DMA technologies have no CPU intervention in data transmission is utilized, the processing efficiency of Manchester encoding is improved, and the flexibility and expandability of system encoding verification are enhanced.

The present application relates to the technical field of digital chip design, and discloses a Manchester decoding method for a microsecond channel protocol, including: synchronizing a data stream in a Manchester encoding format based on a microsecond channel protocol; starting counting through a sampling counter when a falling edge appears in the data stream to sample the synchronized data stream and storing multiple sampling values ​​in a shift register; in the case where there are identical sampling values ​​in multiple sampling values, taking the identical sampling values ​​as valid sampling values ​​to obtain a target data stream; sampling the target data stream through a generated high-frequency clock to obtain a sampling result; wherein the baud rate of the high-frequency clock is determined according to the baud rate of the data stream; and decoding the target data stream according to the count value in the sampling result. It can significantly reduce transmission errors caused by data loss frames, and ensure the stability of data transmission. The present application also discloses a Manchester decoding device and electronic device for a microsecond channel protocol.

The disclosure relates to a fifth generation (5G) or sixth generation (6G) communication system for supporting a higher data transmission rate. In accordance with another aspect of the disclosure, a user equipment (UE) in a wireless communication system is provided. The method includes receiving, by the UE, first information from a base station, performing, by the UE, digital baseband encoding of uplink information based on at least one of the first information or predefined digital baseband coding schemes, and transmitting, by the UE, the encoded uplink information.

Encoding devices, methods and programs that encode with high transmission efficiency by controlling a running disparity are disclosed. In one example, an encoding device includes a scrambling circuit that scrambles an input data string, a calculation circuit that calculates a first running disparity of the scrambled data string, a determination circuit that determines whether or not to invert the scrambled data string on the basis of a first running disparity calculated by the calculation circuit and a second running disparity calculated at a time point before the first running disparity, and an addition circuit that inverts or non-inverts the scrambled data string on the basis of a determination result by the determination circuit, adds a flag indicating the determination result, and outputs the data string. The technology can be applied to devices that perform SLVS-EC standard communication.

The invention relates to a Manchester coded signal decoding method and a Manchester coded signal decoding system, and belongs to the field of electronic information, communication and power system automation. A plurality of clocks with the same frequency and different phases are generated according to Manchester encoding signals, the clocks are used for sampling the signals, a phase-shifting clock sampling method is used, dependence on a high-frequency clock is reduced, most interference in communication signals is determined to be eliminated according to a majority voting strategy for sampling results, and the accuracy of the signals is improved. And the seriously distorted signals are corrected according to special value enumeration, so that the interference of signal duty ratio distortion and burrs is reduced, and the decoding reliability is further improved. And finally, determining an original data stream of the signal according to the two level states of each code element. The method is used for decoding high-speed and ultra-high-speed Manchester encoding signals under the conditions of no high-frequency clock, poor data signal quality or unstable clock, and simultaneously realizing self-adaptive communication of different encoding formats.

The invention discloses a PSI5 decoding method, and relates to the technical field of PSI5 decoding, a main chip sends a PWM signal to enable a PSI5 conversion module to generate a synchronization pulse, a sensor detects the synchronization pulse and then fills fluctuating current data, a current comparison module converts the fluctuating current data into a digital voltage signal, a voltage output module amplifies the digital voltage signal and then sends the digital voltage signal to a main chip universal port, and the PSI5 conversion module outputs the digital voltage signal to the main chip universal port. The main chip detects the level of a port through a timed task, and Manchester soft decoding is carried out to obtain data. The method has obvious advantages, the dependence on a special decoding chip is eliminated, the cost is reduced, data can be analyzed by using a general interface of a main chip, the requirement on the main chip is reduced, the system performance is improved by software decoding, and the control real-time performance and the control effect are improved in applications such as an electric control suspension and the like.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an ambient Internet-of-Things (IoT) device may receive configuration information indicating resources associated with an uplink trigger message that initiates a communication session between the ambient IoT device and a network device. The ambient IoT device may transmit the uplink trigger message to the network device using the resources associated with the uplink trigger message. Numerous other aspects are described.

A device may receive signaling that includes a preamble having a first subset of bits of the set of bits and a payload having a second subset of bits. In some examples, the second subset of bits may be encoded according to a Manchester encoding scheme. The second subset of bits may include fewer bits than the first subset of bits. In some examples, less than a threshold quantity of bits of the first subset of bits includes a same bit value, and each bit of the threshold quantity of bits is consecutive. The device may detect the preamble of the received signaling, and decode the payload of the received signaling including the second subset of bits (e.g., Manchester encoded subset of bits) in response to the detected preamble of the received signaling.

A device may receive signaling that includes a preamble having a first subset of bits of the set of bits and a payload having a second subset of bits. In some examples, the second subset of bits may be encoded according to a Manchester encoding scheme. The second subset of bits may include fewer bits than the first subset of bits. In some examples, less than a threshold quantity of bits of the first subset of bits includes a same bit value, and each bit of the threshold quantity of bits is consecutive. The device may detect the preamble of the received signaling, and decode the payload of the received signaling including the second subset of bits (e.g., Manchester encoded subset of bits) in response to the detected preamble of the received signaling.

A method for serializing communications in the computing field includes serializing input data into a serialized stream of symbols, based on one or more encodings, at a serializer, each symbol including a disparity code selected based on a running disparity (RD) of the serialized stream of symbols. The running disparity (RD) is tracked by setting the RD to an initial value, and then adding a disparity of each symbol to the RD to ensure the RD does not exceed a desired maximum, e.g., three. A positive disparity encoding or a negative disparity encoding of each symbol is selected for transmission based on the RD. The serialized data stream of symbols is transmitted along a data conduit, to a deserializer, in which the serialized data stream of symbols is deserialized to determine a corresponding bit value, for outputting decoded information in parallel form.

The present invention relates to a memristor positive and negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder. The 3-line-1-line encoder of the present invention is used to input three binary signals and output a three-value signal; each three-value three-input maximum value gate is used to output the logical maximum value of three input terminals, the three-value three-input minimum value gate is used to output the logical minimum value of three input terminals, the three-value two-input AND gate is used to complete the "AND" operation of two inputs, the three-value two-input OR gate is used to complete the "OR" operation of two inputs, the standard three-value NOT gate is used to complete the standard three-value logic "NOT" operation, and the positive three-value NOT gate is used to complete the positive three-value logic "NOT" operation; the present invention uses a three-value digital signal to communicate at the same frequency, which will have a higher transmission rate, and the corresponding logic function circuit interconnection will also be reduced, and the digital chip can also be smaller and the cost is lower. Combined with the characteristics of the memristor, the efficiency of information storage, processing, and transmission is further improved.

Ternary data corresponding to a movable barrier drive is provided (21) and converted (22) into corresponding binary information. In a preferred approach, this comprises converting each ternary bit into a corresponding binary pair. According to a preferred approach, binary bits corresponding to, for example, fixed and / or non-fixed information (32 and 33) are provided (31) and then converted (34) into the aforementioned ternary data.

Examples of the invention relate to first and second communication devices for the transmission and reception of binary sequences in a communication system. Therefore, the first communication device (100) transmits a communication signal (510) to a second communication device (300), and the communication signal (510) comprises a first binary sequence which is formed based on a second binary sequence. The second binary sequence is in turn formed based on: permute a seed sequence s 0 or a binary complement of the seed sequence s 0 with a first permutation function p; extend or truncate the permuted seed sequence s 0 or the permuted binary complement of the seed sequence s 0 to a length L'; and permute the extended or truncated seed sequence s 0 or the extended or truncated binary complement of the seed sequence s 0 with a second permutation function π. Furthermore, examples of the invention also relate to corresponding methods and a computer program.

A position-determining system and a method for ascertaining a car position of an elevator car use a code tape mounted next to the elevator car in parallel with a movement direction and that includes a code-mark pattern of individual code marks, a detection apparatus mounted on the elevator car that detects the code marks, and an evaluation unit that determines the car position on the basis of the detected code marks. Here, n successive code marks of the code-mark pattern form a position mark, the position marks are unambiguously arranged in an n-digit pseudorandom sequence of various position marks, the position marks form a single-track code-mark pattern, and a discrete car position is assigned to each position mark. A detection region of the detection apparatus has a detection length in the movement direction that is shorter than a position-mark length of a position mark in the movement direction.

In an aspect, a method of coding a data stream is provided. In an aspect, the method includes mapping, by a data stream encoder, bits into one or more delimiters for the data stream while limiting a maximum run-length of a same polarity of bits in the data stream to be no more than 5. Each of the one or more delimiters include a zero bit and a one bit appended to an 8b / 10b codeword of one or more 8b / 10b codewords in the data stream. In an aspect, the method further includes transmitting, by a transmitter, the one or more delimiters in the data stream.

A method of data transmission includes transmitting a magnetic signal that is modulated with the bit stream, the magnetic signal having a nominal frequency and being formed of a high frequency and a low frequency, the nominal frequency being the average frequency of the magnetic signal. The bit stream is modulated onto the magnetic signal by encoding the bit stream into the magnetic signal, where each bit in the bit stream is represented by a transition between adjoining data symbols formed of K repetitions of a first state or a second state. The first state of the pair of states includes M / 2 cycles of the nominal frequency with a signal at the high frequency and M / 2 cycles of the nominal frequency with a signal at the low frequency. The second state is complementary to the first state.

A signal processor comprises a signal receiving circuit, a preprocessing circuit, a cycle acquisition circuit and a decoding circuit. The signal receiving circuit is used to receive an input signal. The preprocessing circuit is coupled to the signal receiving circuit and is used to generate a square wave signal according to the input signal. The cycle acquisition circuit is coupled to the preprocessing circuit and is used to capture multiple signal cycles of the square wave signal, wherein the multiple signal cycles include multiple signal cycle groups, and the multiple signal cycle groups respectively include at least two adjacent signal cycles in the multiple signal cycles. The decoding circuit is coupled to the cycle acquisition circuit and is used to perform decoding according to the time length of the multiple signal cycle groups and the number of voltage value changes to obtain a decoding result.

The present invention discloses a method and apparatus for generating frequency-encoded pulse data for use in a spiking neural network. The method comprises converting the time-encoded pulse data of the spiking neural network through one or more conversion functions to obtain frequency values, and generating the frequency-encoded pulse data of the spiking neural network based on the frequency values. The present invention advantageously supports more than one pulse coding format, provides the ability to integrate multiple coding formats, and provides compatibility with multiple coding processes.

The invention discloses a PSI5 interface circuit current threshold control method, device and equipment and a storage medium, and relates to the field of sensing detection, gradient current thresholds are set for N current comparators, each current comparator generates a Manchester signal based on a sampling current value and a corresponding current threshold, and a corresponding decoding success rate is recorded through a register group; determining a target current comparator based on the decoding success rate recorded by the N paths of current comparators after power-on; obtaining a target current comparator and a current threshold, outputting a Manchester coded signal, and calculating a duty ratio value; and updating the current threshold value of the target current comparator according to the duty ratio value gradient, and updating the N-path decoding success rate. According to the scheme, Manchester encoding signals are not directly and continuously monitored, different current threshold values are set in a gradient mode, the current comparators are screened according to the decoding success rate, then the duty ratio is adjusted, chip computing resources can be optimized to the maximum extent, and the encoding and decoding accuracy can be improved to the maximum extent.

A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

The invention discloses a Manchester code receiving and storing method and system, and the method comprises the steps: firstly converting a serial data signal of a Manchester code into a parallel signal, and carrying out the decoding of the serial signal, enabling the decoding operation to be isolated from a clock signal, weakening the dependence on the clock synchronization in a decoding process, and improving the decoding efficiency. The method is suitable for a scene that a serial signal does not have accurate synchronous clock input, a high-order address of a storage address is defined by judging packet header data, a low-order address of the storage address is determined by packet length, different packet header data are stored in corresponding addresses, classification and address division storage of received data frames according to packet header information is realized, and the storage efficiency is improved. The method can be applied to various bus transmission data protocols, is suitable for various FPGA development, and has good universality and application prospects.

A method of data transmission includes transmitting a magnetic signal that is modulated with the bit stream, the magnetic signal having a nominal frequency and being formed of a high frequency and a low frequency, the nominal frequency being the average frequency of the magnetic signal. The bit stream is modulated onto the magnetic signal by encoding the bit stream into the magnetic signal, where each bit in the bit stream is represented by a transition between adjoining data symbols formed of K repetitions of of a first state or a second state. The first state of the pair of states includes M / 2 cycles of the nominal frequency with a signal at the high frequency and M / 2 cycles of the nominal frequency with a signal at the low frequency. The second state is complementary to the first state.

The invention discloses a data decoding method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a clock rate of a single-channel clock; sampling a data stream formed by adopting Manchester coding at a rising edge and a falling edge of the single-path clock according to the clock rate of the single-path clock to obtain a plurality of pieces of sampling data; and decoding each piece of sampling data to obtain decoded data of the data stream. According to the data decoding method provided by the embodiment of the invention, the decoding efficiency can be improved, and meanwhile, clock resources which need to be occupied when the data which adopts Manchester encoding are decoded are reduced.

The invention discloses an industrial Internet of Things communication method based on time division. The method comprises the following steps: connecting a main node and a sub-node in an industrial Internet of Things by adopting a single cable; the main node allocates time slots of data transmission and power transmission of each child node at intervals based on a time division technology; each child node performs data transmission and power transmission with the main node in a specified time window according to the time slot; when data transmission is carried out between each child node and the main node, an encoding mode is Manchester encoding, and an adopted communication protocol is a Modbus protocol. According to the invention, data transmission and power transmission in the industrial Internet of Things are integrated in a single cable based on a time division technology, and Manchester encoding and a Modbus protocol are combined, so that the wiring is simplified, the cost is reduced, the line utilization rate is improved, and the communication reliability and high efficiency are ensured.

The application belongs to the field of chip interconnection communication, and particularly discloses a chip interconnection communication method and system based on Manchester coding, which comprises the following steps: a master control device generates and sends a communication frame, the physical layer of which adopts Manchester coding, logic 1 is high-to-low transition, and logic 0 is low-to-high transition, and the frame start / end is defined by a specific high-low level sequence; the data link layer of the communication frame comprises a synchronization code, an address field, a control field, a data field and an end code, the control field comprises pin intervals and quantity identification, and a clock is sent simultaneously to synchronize the slave device; the slave device decodes the received signal, determines the target pin range according to the identification when the address is matched, and sets the pin level according to the data field. The application improves the communication rate and efficiency, simplifies the wiring, and adapts to the chip interconnection requirements in multiple scenes.