409results about How to "Save area" patented technology

A module operable to be mounted onto a surface of a board. The module includes a linear accelerometer to provide a first measurement output corresponding to a measurement of linear acceleration in at least one axis, and a first rotation sensor operable to provide a second measurement output corresponding to a measurement of rotation about at least one axis. The accelerometer and the first rotation sensor are formed on a first substrate. The module further includes an application specific integrated circuit (ASIC) to receive both the first measurement output from the linear accelerometer and the second measurement output from the first rotation sensor. The ASIC includes an analog-to-digital converter and is implemented on a second substrate. The first substrate is vertically bonded to the second substrate.

A low-power, area and pin efficient signaling alternative to serial differential links used for chip-to-chip, backplane, optical and other signaling applications. The multi-bit differential signaling (MBDS) generally comprises a driver and link termination network design coupled with a coding system based on n choose M (nCm) coding. MBDS has comparable electrical characteristics to conventional low-voltage differential signaling (LVDS) and is fully compatible with existing LVDS receivers in point-to-point and multi-point bus topologies. However, MBDS uses up to 40% less power, with up to 33% fewer I / O pads than equivalent LVDS links.

A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

A system and method are disclosed which provide a look-down digital imaging device capable of capturing relatively high resolution digital images (e.g., comparable to traditional flatbed scanners). A preferred embodiment provides a look-down digital imaging device comprising a linear sensor for imaging a raster line of an original image placed substantially below the look-down digital imaging device, and a lens for focusing reflected light from the original to such linear sensor. The linear sensor functions much as in traditional flatbed scanners in that it captures a single, congruent digital image of a scanned original. Most preferably, the linear sensor is a high resolution sensor that enables a digital image to be captured having resolution comparable to that of traditional flatbed scanners. For instance, the linear sensor preferably enables capture of a digital image having a resolution no less than approximately 300 dpi. As a result, such linear sensor most preferably captures a digital image having sufficient resolution to permit optical character recognition operations to be performed on such captured image. In a most preferred embodiment, the look-down digital imaging device further comprises a digital video camera for capturing video data of a target scan area. Such video data may be fed in substantially real-time to a display (either included within the look-down digital imaging device or included on a device to which the look-down digital imaging device is coupled), which may aid a user in properly aligning an original within the target scan area.

A multiprocessor computer system includes an exception domain having multiple thread contexts (TCs) each having a restart address register, and a timer that generates a periodic interrupt request to the exception domain. The exception domain selects an eligible TC to service the interrupt request, which is non-specific regarding which TC to select. A first interrupt handler executes on the selected TC to service the interrupt request to schedule a set of processes assigned by the SMP OS for execution on the selected TC, and write an address of a second interrupt handler to the restart address register of each TC other than the selected TC. The second interrupt handler schedules a plurality of sets of processes assigned by the SMP OS for execution on respective ones of the TCs other than the selected TC.

An audio encoder has a common preprocessing stage, an information sink based encoding branch such as spectral domain encoding branch, a information source based encoding branch such as an LPC-domain encoding branch and a switch for switching between these branches at inputs into these branches or outputs of these branches controlled by a decision stage. An audio decoder has a spectral domain decoding branch, an LPC-domain decoding branch, one or more switches for switching between the branches and a common post-processing stage for post-processing a time-domain audio signal for obtaining a post-processed audio signal.

The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3 / Ta2O5, Al2O3 / Ta2O5 / Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a multiprocessor operating system. However, the microprocessor hardware does not support the ability for one TC to direct an exception to another TC, i.e., to specify to which of the other TCs the exception is directed. A first thread running on a first TC of the operating system executes architected instructions to halt a second thread (either user or kernel thread) running on a second TC, save state of the second TC, write the second TC state to emulate an exception—including writing a restart register with the address of an exception handler, and unhalt the second TC to execute the exception hander.

A method for forming a prograde kinematic model allowing reproduction in 3D intermediate geometries of geologic objects of an underground zone such as a sedimentary basin, from an initial state to a current state. A representation of the current geometry of the geologic objects of the zone is formed by interpretation of acquired data obtained by seismic exploration, by in-situ measurements and by observations, then each geologic object is subdivided into layers separated by deformation interfaces. Each one of the layers is defined by means of a grid pattern into a series of hexahedral volume elements. Tectonic deformations are then applied separately and successively to each series of volume elements of a layer in relation to an underlying layer while conserving the thickness and the surface area of an intermediate neutral surface in each volume element. Then the tectonic deformations are iteratively modified until a geologic representation substantially in accordance with the known final state of the underground zone is obtained.

Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact / via fuse, contact / via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ / N+ implants on a polysilicon as a program selector. By applying a high voltage to an OTP element coupled to the P-terminal of a diode and switching the N-terminal of a diode to a low voltage for suitable duration of time, a current flows through the OTP element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the OTP element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area.

The present invention provides an information processing apparatus of space-saved type that can execute the processing corresponding to a security function module. A security function module storing a device key is integrally arranged in an MPU chip, the secret data including programs and data to be applied to the data processing to be executed in the security function module are encrypted with the device key or attached with a falsification verification value and the resultant programs and data are stored in an external storage section. This novel configuration can significantly reduce the amount of data to be stored in the security function module and therefore eliminate the necessity for a large-capacity flash memory. Consequently, the security function module can be integrally arranged in the MPU chip having the main CPU, thereby significantly reducing the packaging area and the production cost.

An integrated circuit including a reinforced bonding pad structure is disclosed. The reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. At least one metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame of the reinforced bonding pad structure.

There is provided a display driver control circuit which is just suitable for display drive including display with a small amount of change and display with a large amount of change and can realize saving of chip area and reduction of power consumption and cost. In this display driver control circuit, memory capacity of an internal display memory is set smaller than amount of data of one display picture of a display panel as the drive object, and the display data can be transferred with the system in which externally inputted display data is once stored in the display memory and is then sent of a drive circuit to output a drive signal and with the system in which the display data is sent in direct to the drive circuit by way of no display memory to output a drive signal. Moreover, both transfer methods can be executed on the time division basis.

A method of virtual processing includes running a virtual processor (1), which when the virtual processor (1) encounters a faulting instruction unmaps the virtual processor (1) from the physical processor (A), and generates a list of other of the physical processors that could execute the instruction. Then determines if one of the other of the physical processors in the list is currently idle, and when one of the other of the physical processors in the list is determined to be currently idle, maps the virtual processor (1) to a physical processor (B) which is the one of the other of the physical processors in the list that was determined to be currently idle.

The present invention facilitates scaling of memory devices and operation thereof by employing a set associative repair cache system to correct or repair identified faulty memory cells. A repair cache region router 602 compares a repair region portion of a memory address to repair cache regions to identify a matching repair cache region. Then, a local repair location router 603 compares a repair address portion of the memory address to a local repair location addresses particular to the matching repair cache region to identify a matching local repair address. If a matching local repair address is identified, a repair component 606 provides access to a repair data location according to the matching local repair address and the matching repair cache region. Otherwise, a main memory 604 provides access to a memory location according to the memory address. Other systems and methods are disclosed.

A micromechanical rotation rate sensor has at least one first and one second seismic mass coupled to at least one first drive device and are suspended such that the first and second seismic masses are driven such that they are deflected in antiphase in one drive mode, with the rotation rate sensor being designed such that it can detect rotation rates about at least two mutually essentially orthogonal sensitive axes, wherein at least the first and second seismic masses are designed and suspended such that they oscillate in antiphase in a first read mode when a first rotation rate about the first sensitive axis is detected, and the first and second seismic masses and / or additional seismic masses are designed and suspended such that they oscillate in antiphase in a second read mode when a second rotation rate about the second sensitive axis is detected.

The disclosure is directed at a method of digital imaging comprising sensing photons on at least one pixel within a pixel array of a radiation detector; counting the photons using photon counting to produce a digital signal representative of the sensed photons; monitoring a photon flux associated with the sensed photons; and using photon integration to produce a digital signal representative of the sensed photons when the photon flux is higher than a predetermined photon flux.

An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.

A radio frequency (RF) integrated circuit with electrostatic discharge (ESD) protection and an ESD protection apparatus thereof are provided. The ESD protection apparatus includes a substrate, an RF bonding pad, and an ESD protection unit. The RF bonding pad for transmitting RF signal is disposed upon the substrate. The ESD protection unit is disposed under the RF bonding pad. Wherein, The ESD protection unit includes an inductor electrically connected between the RF bonding pad and the power rail.

A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source / drain region of the transistor is connected to the first doped region of the first capacitor.

A drive circuit of an organic light emitting display and an offset voltage adjustment unit thereof are provided. The offset voltage adjustment unit can be used in an operational amplifier of the drive circuit having a differential input stage, a bias stage, and an output stage. The offset voltage adjustment unit coupled between the bias stage and a ground including a resistor string and a plurality of latch units. The resistor string has a first-end, a second-end, and a plurality of resistors series-connected between the first-end and the second-end forming a plurality of junctions. The latch units are coupled between the junctions and the ground, respectively. The latch units are sequentially conducted to adjust a bias current of the bias stage according to a control signal. The latch units enter a latch state upon receiving a latch signal to calibrate an output offset voltage of the operational amplifier.

A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a multiprocessor operating system. However, the microprocessor hardware does not support the ability for one TC to direct an exception to another TC, i.e., to specify to which of the other TCs the exception is directed. A first thread running on a first TC of the operating system executes architected instructions to halt a second thread (either user or kernel thread) running on a second TC, save state of the second TC, write the second TC state to emulate an exception—including writing a restart register with the address of an exception handler, and unhalt the second TC to execute the exception hander.

A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.