4289 results about "A d converter" patented technology

This invention pertains to an intelligent electronic device designed for sophisticated monitoring and analysis of electrical power distribution. The device integrates at least one sensor for detecting electrical parameters from a distribution system to a load, coupled with an analog-to-digital converter to transform sensed analog signals into digital data. A processing module, linked to the converter, employs customized moving average filters to calculate the frequency of electrical power distribution, enhancing measurement accuracy by adjusting for transient fluctuations. It retrieves frequency threshold settings from memory to define operational bounds, logging frequency data around identified deviation events when measurements surpass these thresholds. This system facilitates precise frequency analysis and robust event logging, providing a comprehensive solution for maintaining electrical power distribution within defined standards.

The invention discloses a power grid multi-range intelligent sensing method and system based on MEMS integration, and relates to the technical field of intelligent sensing, and the method comprises the steps: connecting an MEMS sensing unit to three parallel measurement channels, and connecting the MEMS sensing unit to a controllable signal routing module in parallel; after gating, the signals are sent to a successive approximation analog-to-digital converter for digitalization through nonlinear gain amplification and anti-aliasing filtering; determining a measuring range based on a sampling sequence and a sliding window ratio, and automatically switching channels through a threshold value and a hysteresis mechanism; performing baseline correction on the switching data and performing weighted fusion according to sensitivity and bandwidth; and after the laboratory performs segmented calibration and consistency verification on the three channels, calibration parameters are written and stored, and are transmitted to an upper system through an isolation power supply according to a preset protocol. Automatic range switching is achieved through a sliding window and a hysteresis mechanism, baseline drift correction and weighting fusion according to the proportion of sensitivity and bandwidth are adopted after channel switching, and measurement continuity and precision consistency are ensured.

The invention relates to the technical field of power equipment state detection, in particular to an ultrahigh-frequency partial discharge online detection system, method and device and a medium, and the system comprises the steps: collecting an initial discharge signal in real time through an ultrahigh-frequency sensor array, and carrying out the preprocessing of the initial discharge signal, so as to obtain an ultrahigh-frequency discharge signal; carrying out peak detection on the ultrahigh-frequency discharge signal, and triggering a high-speed analog-to-digital converter to collect an original waveform when the amplitude exceeds a preset threshold value; performing multi-dimensional feature extraction on the original waveform by using a digital signal processor to obtain multiple groups of dimensional features; identifying and classifying the multiple groups of dimension features based on a random forest algorithm, generating discharge type labels and confidence coefficients, and storing the discharge type labels and the confidence coefficients in a dynamic database; carrying out spatial position calculation on the ultrahigh-frequency discharge signal by adopting a time difference method, and determining a three-dimensional coordinate of a discharge source; the dynamic database and the three-dimensional coordinates of the discharge source are subjected to space-time correlation and multi-dimensional analysis, a defect analysis result is generated, and high-precision online detection of the partial discharge defect of the high-voltage equipment is achieved.

The invention relates to the technical field of voltage acquisition, in particular to a battery string voltage acquisition system with a calibration system and a voltage acquisition method. Which comprises a multi-path voltage input end, a voltage signal adjusting end, a voltage follower, an analog-to-digital converter, a main control center and a communication circuit, and is characterized in that the voltage signal adjusting end comprises a dynamic voltage division network, consists of a digital potentiometer and a high-voltage operational amplifier, and dynamically adjusts the voltage division ratio to suppress common-mode voltage; the main control center is integrated with a multi-channel synchronous sampling calibration module and generates a global synchronous signal through the main MCU to control the ADC to perform synchronous acquisition; a temperature compensation module is arranged between the voltage follower and the ADC, and a digital temperature sensor is adopted to correct the gain drift of the operational amplifier in real time; the voltage division ratio of the dynamic voltage division network is dynamically adjusted according to the real-time common-mode voltage and a preset safety threshold value. According to the scheme, dynamic partial pressure adjustment, multi-channel self-calibration, nonlinear temperature compensation and a rapid protection mechanism can be integrated.

The invention relates to a high-precision temperature sensor based on complementary dynamic element matching and a zoom analog-to-digital converter and a working method, and belongs to the technical field of sensor improvement, and the sensor comprises an analog front end, an analog-to-digital converter, a digital rear end and a control logic. An improved chopping technology is adopted, and one clock signal is adopted to control two sub operational amplifiers, so that the output stability and precision of the analog front end are improved. A complementary dynamic element matching technology is utilized, errors caused by voltage drop at the two ends of a switch are reduced, the influence of channel charge injection is counteracted, a scaling type analog-to-digital converter design is provided for an analog-to-digital conversion part, and balance among power consumption, speed and precision is achieved. According to the method, a 10-bit successive approximation register analog-to-digital converter is used for measuring a numerical value and a change trend, and the numerical value and the change trend are analyzed, so that the expression effects of a current mirror structure, a transistor, a filter and the like are evaluated, the aging of the transistor is found in advance, and a clear direction is provided for future design improvement.

The invention discloses a noise reduction method and system for a high-performance TWS Bluetooth audio chip, and relates to the technical field of acoustoelectric integration, and the method comprises the steps: collecting an environment noise signal, synchronously obtaining a Bluetooth radio frequency interference signal, converting the Bluetooth radio frequency interference signal into a digital signal through a 24-bit analog-to-digital converter, and outputting a multi-modal noise feature matrix; performing noise separation and reverse sound wave generation on the multi-modal noise characteristic matrix by using a pre-trained lightweight CycleGAN model, and outputting a reverse sound wave signal; monitoring auditory meatus tightness parameters in real time, dynamically adjusting phase offset and frequency response balance parameters of the mixed noise reduction signals, and outputting optimized noise reduction signals adaptive to the current wearing state; and performing parameter calibration on the optimized noise reduction signal through anechoic chamber scene simulation and laser interferometer phase detection to generate a noise reduction control instruction set. According to the invention, the noise interference problem of the TWS earphone in a complex environment is effectively solved.

The invention belongs to the field of circuits, and particularly relates to an analog front-end circuit for capacitance detection and a current calibration method, the analog front-end circuit comprises a driving circuit, a to-be-detected capacitor, a chip signal input and output interface circuit, a current amplification circuit or charge amplification circuit, an integrating circuit and an analog-to-digital converter which are connected in sequence; the leakage current measurement and calibration controller is used for receiving a signal of the analog-to-digital converter and outputting a control signal for calibrating the leakage current to the current calibration circuit; the output end of the current calibration circuit is connected with the input end of the integrating circuit, and the current calibration circuit is used for adjusting the output of the current calibration circuit to calibrate the magnitude of the current input into the integrating circuit when receiving the control signal for calibrating the leakage current. According to the application, the leakage current measurement and calibration controller is arranged at the output end of the integrating circuit, the leakage current of the analog front-end circuit is measured, and the control signal is output to adjust the output of the current calibration circuit, so that the magnitude of the current input into the integrating circuit is calibrated, and errors caused by imbalance of the leakage current and the current of the amplifying circuit can be compensated.

The invention relates to the technical field of integrated circuit temperature compensation and high-precision calibration, and discloses a high-density full-temperature trimming method and system based on a fuze chip. The high-density full-temperature trimming method is applied to chip trimming equipment and specifically comprises the following steps that S101, temperature information of a fuze chip is received, the working temperature range of the fuze chip is divided into a plurality of continuous temperature sub-intervals, calibration points are uniformly deployed in each sub-interval, and the temperature information of the fuze chip is acquired; the temperature coordinates of the calibration points are collected in real time through the high-precision temperature sensor and then quantized through the analog-to-digital converter. According to the method, the density of calibration points in subintervals is dynamically adjusted, nonlinear characteristics of a temperature sensitive area are effectively captured, and the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below in combination with a cubic Hermite interpolation and residual compensation algorithm. In addition, the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below through application of a redundancy check storage architecture and an interleaving addressing technology. And the single event upset resistance of the calibration parameters is improved.

The invention discloses a circuit for simultaneously switching transimpedances of multiple channels by adopting a shift register. The circuit is characterized in that an FPGA (Field Programmable Gate Array) is connected with a signal acquisition and conversion circuit module through an analog-to-digital converter and a clock generation and distribution module; the signal acquisition and conversion circuit module comprises a bias voltage setting module, a pi-type filter, a photoelectric sensor and a transimpedance amplification module which are connected in series; the input end of a transimpedance amplifier in the transimpedance amplification module is connected with a transimpedance gain access circuit, the transimpedance gain access circuit is connected with the output end of the transimpedance amplifier through an analog switch, and the control end of the analog switch is connected with the FPGA through a shifting register. According to the circuit and the method for simultaneously switching the transimpedances of the multiple channels by adopting the shift register, the transimpedance gain of the transimpedance amplifier is judged and switched according to the size of the signal, the range of the input signal is expanded, the resolution is improved, and the IO resources of the FPGA are saved and the cost is reduced by utilizing the storage function and the serial-parallel conversion function of the shift register.

The invention provides an online monitoring method and device for partial discharge of GIS equipment, and relates to the field of online monitoring of high-voltage electrical equipment, and the method comprises the steps: collecting a partial discharge signal in the GIS equipment, and synchronously obtaining the data of an environment noise sensor; processing the acquired ultrahigh frequency signal based on the data of the environmental noise sensor to obtain a preprocessed analog signal; converting the preprocessed analog signal into a digital signal through a high-precision analog-to-digital converter; key characteristic parameters of the partial discharge signals are extracted from the digital signals; dynamically adjusting a discharge detection threshold according to the extracted key characteristic parameters by applying a hybrid optimization algorithm; and based on the adjusted discharge detection threshold, setting an event trigger condition, and when the detected partial discharge signal amplitude and the trigger frequency reach the event trigger condition, sending out an alarm signal. According to the invention, the partial discharge phenomenon can be detected and alarmed in time, so that the operation reliability and safety of the GIS equipment are improved.

The invention discloses a multi-channel analog-to-digital converter for multi-channel frequency division multiplexing and a conversion circuit and method thereof, and the frequency division multiplexing multi-channel analog-to-digital conversion circuit comprises an analog frequency conversion module which is used for receiving N paths of modulation clock signals, and generating N paths of modulation clock signals according to the modulation clock signals, n paths of input signals are modulated to preset frequencies of the input signals respectively, and N paths of modulation signals are obtained; wherein N is greater than or equal to 2, and N is a positive integer; the frequency bands where the N paths of modulation signals are located are not overlapped; the analog adder is used for combining the N paths of modulation signals to obtain one path of analog signal; the input end of the analog-digital conversion module is connected with the analog-digital conversion module; the digital logic control module is used for receiving the N paths of modulation clock signals and separating the digital signals into N paths of digital signals which are output in parallel. Multi-channel analog-to-digital conversion can be realized by adopting one analog-to-digital converter, the hardware volume, cost and power consumption can be reduced, and the analog-to-digital conversion rate and precision can be improved.

The present disclosure involves a medical device. The medical device includes an elongate cable assembly having a distal connector, a proximal connector, and a cable body coupling the proximal and distal connectors. The distal connector is configured for coupling with a diagnostic medical device. The proximal connector is configured for coupling with a medical measurement system. An electronic component is located inside the distal connector or the associated cable housing. The electronic component includes an analog-to-digital converter (ADC) and a microprocessor. The ADC is configured to receive medical data gathered by the diagnostic medical device and convert the medical data into digital signals. The microprocessor is coupled to an output of the ADC and configured to process the digital signals into a format that is readable by the medical measurement system.

A method of operating a time-interleaved analog-to-digital converter (TIADC). The TIADC converts an input signal to generate a digital output signal and includes multiple asynchronous sub-ADCs. The asynchronous sub-ADCs each convert the input signal at a different time point to generate a digital output code, and each of the asynchronous sub-ADCs generates a completion signal upon completion of an analog-to-digital conversion operation. The method includes the following steps: generating an indication signal according to the completion signals, wherein the indication signal indicates multiple candidate sub-ADCs; selecting one of the candidate sub-ADCs as a target sub-ADC according to the indication signal; and correcting the digital output code of the target sub-ADC to generate the digital output signal.

A centimeter-resolution integrated photonic millimeter-wave (mmWave) radar chip operating in the mmWave V band based on a 4-inch wafer-scale thin-film lithium niobate (TFLN) technology is provided. The fabricated TFLN photonic mmWave integrated circuit has a first electro-optic modulator (EOM) capable of generating a broadband linear frequency modulated mmWave radar waveform through optical frequency multiplication of a low-frequency input signal, and a second EOM for frequency de-chirp of the reflected echo wave, thereby greatly relieving bandwidth requirements for the digital-to-analog converter in the transmitter and analog-to-digital converter in the receiver. In the absence of optical and electrical filters, the radar chip features continuous on-demand tunability of the center frequency and bandwidth, currently only limited by the bandwidths of electrical amplifiers. The radar chip provides a promising way to achieve high resolution sensing and detection for vehicle radar, airborne radar, and smart home in the 6G era.

The utility model relates to a power supply device and a testing machine, and the power supply device comprises a loop controller which receives an error value and outputs a driving signal; the digital-to-analog converter is connected with the loop controller, receives the driving signal and outputs a test signal; the output and sampling unit is connected with the digital-to-analog converter and the tested device, transmits the test signal to the tested device, samples a feedback signal output by the tested device and outputs a sampling signal; the analog-to-digital converter is connected with the output and sampling unit, receives the sampling signal and outputs a sampling value; and the clamping control unit is connected with the analog-to-digital converter and the loop controller, and outputs a pre-clamping instruction to the loop controller when determining that a pre-clamping condition is met according to the sampling value output by the analog-to-digital converter and a preset pre-clamping set value, so that the loop controller slows down output. The trigger of the clamping function can be predicted in advance to act in advance, the high overshoot voltage / overshoot current for triggering the clamping can be avoided, and the tested device can be prevented from being damaged when an abnormality occurs.

The invention relates to a blind beam broadband anti-interference system and method for a GNSS (Global Navigation Satellite System) receiver. The system comprises a multi-element antenna array, a radio frequency front end, an A / D analog-to-digital converter, a broadband anti-interference module, a received signal processing module and a positioning calculation module. According to the system, all-satellite list capturing and searching attempts can be performed on each generated wave beam, satellite signals captured by each wave beam are tracked, and if multiple wave beams exist, the same satellite can be successfully captured at the same time; if yes, the satellite signals in the beams are sent to the tracking channels of the tracking channel groups corresponding to the beams to be tracked respectively; and during positioning calculation, the observed quantity of the tracking channel with the maximum carrier-to-noise ratio of the satellite is selected for positioning calculation, and the tracking channels of other beams continue to keep the tracking state of the satellite so as to participate in observation quantity screening of a subsequent round. By adopting the system, the anti-interference capability and the navigation positioning performance of the receiver can be effectively improved.

The invention discloses a method for detecting and displaying the electric quantity of an earphone, which relates to the technical field of electronic equipment and comprises the following steps of: acquiring an analog signal of battery voltage through an ADC (analog-to-digital converter) channel, converting the analog signal into a digital signal, performing digital filtering processing on the acquired signal, matching a preset voltage-electric quantity mapping table according to an updated battery voltage value, and displaying the electric quantity of the earphone according to the preset voltage-electric quantity mapping table. According to the method for detecting and displaying the electric quantity of the earphone, the voltage of a lithium battery of 0-4.2 V is detected through an ADC differential input mode, the sampling frequency is 100-500 Hz, the precision is 10-12 bits, and signal stability is ensured through low-pass filtering. A sliding window mean filtering algorithm is adopted to process signals, fluctuation and noise are effectively eliminated, and voltage changes are dynamically tracked. A deviation comparison mechanism avoids misjudgment and ensures accurate electric quantity detection. The electric quantity mapping table is dynamically adjusted according to the voltage, the battery use duration and the environment temperature, the earphone electric quantity state is accurately reflected, the user experience is improved, and the electric quantity detection stability and accuracy are improved.

The embodiment of the utility model provides a resistor calibration circuit, a resistor calibration device and an electronic device. The resistor calibration circuit comprises a current source module used for outputting a reference current; the standard resistor module is connected with the current source module to receive the reference current and generate a reference voltage; in the working process of the resistor calibration circuit, a resistor to be calibrated is connected with the current source module to receive the reference current and generate a voltage to be measured, and the analog-to-digital converter is connected with the standard resistor module to perform analog-to-digital conversion on the voltage to be measured based on the reference voltage. According to the resistance calibration circuit, the analog-to-digital converter in the module to be measured is multiplexed for resistance calibration, an additional high-precision measurement calibration system is not needed, and the resistance can be calibrated only by providing the current source module and the standard resistance module, so that the resistance calibration cost is reduced.

The present application relates to the technical field of integrated circuits and relates to a matrix operation apparatus based on a flexible RRAM memory-computing array, and solves the problem in the prior art of the inability to reduce the area of the memory-computing array without affecting the precision. The apparatus comprises: the flexible RRAM memory-computing array for outputting cumulative currents of columns of memory-computing units to a multiplexer (MUX) on the basis of multiple rows of inputs; the MUX for selecting the cumulative current of one column of memory-computing units from among the columns of memory-computing units and sending said cumulative current to an analog-to-digital converter (ADC); the ADC for converting the received cumulative current into a digital signal and sending said digital signal to a subtractor; a popcount module for receiving the multiple rows of inputs, obtaining the number of 1 in the multiple rows of inputs, and outputting the number of 1 to a multiplier; the multiplier for multiplying the number of 1 by a fixed value β and sending a product result to the subtractor; and the subtractor for subtracting the product result from the digital signal to obtain a multiply-accumulate result of the matrix. The present application realizes high-precision memory-computing based on a small-area memory-computing array, further enhances energy efficiency, and can be applied to flexible computing chips to create electronic skin.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

A modulation signal processing apparatus and method is provided. The apparatus is applied to a microcontroller unit. The apparatus includes a first signal processing module and a second signal processing module. The first signal processing module is connected to an analog-to-digital converter of the microcontroller unit, and used for receiving a completion mark output by the converter, collecting a conversion value output by the converter, and generating corresponding bit data according to a total number of sampling times and a preset half-cycle value. The second signal processing module is connected to a PWM output timer of the microcontroller unit, and used for converting the bit data into a modulation data packet that complies with a Qi protocol, and respectively calculating a reload value of the PWM output timer and a corresponding frequency modulation parameter according to the modulation data packet and a preset modulation configuration parameter.

An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

The invention belongs to the technical field of audio equipment design, and relates to a microphone for AI voice cloning based on pseudo tone of acoustic shielding, and the microphone comprises an audio collection module which is used for collecting an environment audio signal in real time; the analog-to-digital converter is used for converting the environment audio signal into a digital signal; the feature extraction module is used for performing frequency domain conversion on the digital signals and extracting frequency spectrum features and tone features; the acoustic shielding calculation module is used for calculating a shielding threshold value of the environment audio signal and determining a frequency band which cannot be heard by human ears in the environment audio signal according to the shielding threshold value; the pseudo tone generation module is used for generating pseudo tones based on the extracted tone features; the synthesis module is used for replacing a corresponding frequency band of the environment audio signal with the generated pseudo tone to form a synthesized audio; and the audio output module is used for outputting the synthesized audio. According to the invention, the pseudo tone can be generated in real time in the audio recording process, and it is ensured that a user is always protected during audio recording.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

The invention discloses a multi-channel parallel sampling high-dynamic response analog-to-digital conversion method, system and equipment and a storage medium, and belongs to the technical field of power electronics and signal processing, and the method comprises the steps: configuring a high-speed analog-to-digital converter channel to form a parallel sampling module, carrying out the alternate sampling of an input power grid analog signal, and generating a discrete sampling sequence group; inputting to a control unit to extract feature data, and calculating to obtain a fluctuation feature value; constructing a channel clock control vector, sending the channel clock control vector to each high-speed analog-to-digital converter channel, adjusting a sampling trigger moment, and re-executing analog signal sampling to obtain a sampling sequence after phase compensation processing; performing waveform reconstruction processing to obtain continuous reconstruction waveform data; and performing electric energy integral operation, and outputting a dynamic metering result. According to the invention, the problems of slow response, sampling distortion and large metering error of the analog-to-digital conversion system under the conditions of frequency fluctuation, unsteady disturbance and bidirectional power in the prior art are solved.

The embodiment of the invention provides a broadband signal dynamic generation method and system based on multiple clock sources, and the method comprises the steps: monitoring a target frequency in real time through a field programmable gate array, and automatically switching to a corresponding target clock source based on a frequency band to which the target frequency belongs; correcting the phase difference corresponding to the new and old target clock sources through a phase compensation register when the target clock sources are switched, and loading a compensation value to a phase offset register of a direct digital frequency synthesis chip; a fundamental waveform of a broadband signal is generated based on a direct digital frequency synthesis chip, multiple harmonic components are superposed through a fractional accumulation method, and each harmonic amplitude is independently controlled through a look-up table method; an output signal of the power amplifier is collected through the analog-to-digital converter, error information of the actually measured waveform and the theoretical waveform is extracted, the phase offset register and the harmonic amplitude look-up table coefficient are dynamically corrected, and a target broadband signal is output. Unification of broadband coverage, high resolution and quick response is realized.

The invention discloses an intelligent monitoring system for full life cycle aging of equipment based on Internet of Things, and relates to the technical field of Internet of Things equipment monitoring. Original analog signals are collected through an intelligent sensor, and conditioned analog signals are output by using a built-in adaptive gain conditioning circuit; converting the conditioned analog signal into a digital sequence through an adaptive analog-to-digital converter, carrying out dynamic sliding window filtering on the digital sequence, calculating derivative features according to the filtered digital sequence, combining original features with the derivative features to obtain a real-time feature vector, dividing the whole life cycle of the equipment into a running-in period, a stable period and a decline period, and carrying out dynamic sliding window filtering on the digital sequence; and constructing a feature state matrix of each stage, obtaining an equipment aging level based on the feature state matrix and the real-time feature vector, carrying out anomaly detection from three dimensions of time, space and features in combination with the equipment aging level, and executing different early warning strategies according to an analysis result. According to the invention, the accuracy of equipment life cycle monitoring is effectively improved.

The invention discloses a high-precision temperature measuring equipment correction system, and relates to the technical field of temperature measuring equipment correction, and the high-precision temperature measuring equipment correction system mainly comprises a hardware layer, an algorithm layer and an embedded layer which are electrically connected with one another. The hardware layer is used for acquiring temperature data, humidity data and pressure data; the hardware layer comprises a temperature sensor array, a humidity sensor, a pressure sensor and an analog-to-digital converter; the algorithm layer is used for correcting the temperature data according to the temperature data, the humidity data and the pressure data, and the algorithm layer comprises a data preprocessing module, a hybrid correction module and a dynamic compensation module; and the embedded layer is used for task scheduling and temperature data output. By implementing the high-precision temperature measurement equipment correction system provided by the invention, the correction precision, efficiency and reliability of the temperature measurement equipment can be improved.

A digital pre-processing chip is disclosed. The digital pre-processing chip comprises an analog interface for transmitting and receiving analog signals to and from a plurality of analog Radio Frequency (RF) chips, and a digital interface for transmitting and receiving digital signals to and from a baseband chip. The digital pre-processing chip further comprises a plurality of Analog-to-Digital Converters (ADCs) for converting a plurality of analog signals received via the analog interface to a plurality of RX digital signals, and a plurality of Digital-to-Analog Converters (DACs) for converting a plurality of TX digital signals to a plurality of analog signals to be transmitted to the plurality of analog RF chips via the analog interface. The digital pre-processing chip further comprises pre-processing circuitry configured to pre-process the plurality of RX digital signals received from the plurality of ADCs to form a pre-processed digital signal to be transmitted to the baseband chip via the digital interface. The pre-processing circuitry is further configured to pre-process a digital signal received via the digital interface to form the plurality of TX digital signals to be transmitted to the plurality of DACs.