117results about How to "Improve storage density" patented technology

The invention relates to the technical field of logistics, in particular to an intelligent stereoscopic warehouse and an operation method thereof. The method comprises the following steps: carrying out logistics tracking data acquisition on goods to be warehoused to obtain a current logistics tracking data set; according to the current logistics tracking data set, goods to be warehoused are classified, a goods classification list is obtained, and the goods classification list comprises a plurality of site fragile goods lists and a plurality of site non-fragile goods lists; according to the goods classification list, carrying out storage interval distribution on the to-be-warehoused goods to obtain a goods storage interval distribution list; according to the cargo storage interval distribution list, carrying out storage location distribution on the to-be-warehoused cargo to obtain a cargo storage location mapping table; and performing logistics updating on the current logistics tracking data set according to the cargo storage position mapping table to obtain an updated logistics tracking data set. The space utilization rate and the storage efficiency of the intelligent stereoscopic warehouse are improved, and the space pressure of a logistics center is effectively relieved.

The invention relates to a four-way cargo carrying device which comprises a mother vehicle, a plurality of lifting belt mechanisms are arranged on a mother vehicle body and connected with a cargo carrying table, the cargo carrying table is provided with a cargo taking and placing mechanism, first walking mechanisms are arranged on the two sides of the mother vehicle body in the first direction, and jacking reversing mechanisms are fixedly installed on the two sides of the mother vehicle body in the second direction. The jacking reversing mechanism is connected with the second walking mechanism so as to drive the second walking mechanism to ascend and descend. According to the goods carrying device, the lane changing efficiency is high, submission of a warehousing system is reduced, and meanwhile the utilization rate of goods shelves is increased.

The invention provides a method for realizing a metasurface hologram, and the method comprises the steps: presetting three kinds of nanometer unit structures which are different in geometric dimension and geometric shape, and each kind of nanometer unit structure comprises nanometer bricks; according to a preset target near field pattern, performing array periodic arrangement on the three nano unit structures on a preset substrate; encoding the phase information of the processed target far-field hologram into the nano brick rotation angle of each nano unit structure after arrangement to complete the construction of the metasurface; polarized light with different wavelengths is arranged to be incident to the metasurface, and a color hologram is achieved in a far-field area of the metasurface. According to the method, near-field nano-imprinting and far-field color holography are simultaneously realized on the same metasurface in a simple coding mode, and complete decoupling is realized, so that two channels have no crosstalk.

The invention discloses an automatic replacement platform for probes. The automatic replacement platform comprises a platform body, a base, a probe storage mechanism, a probe transfer mechanism, a probe docking mechanism and a control part, a probe connector is arranged on the platform body, the base is fixedly installed in a working area of the platform body, and the base and the platform body are connected through a supporting body. The probe storage mechanism comprises a probe frame, a connecting plate and a rotating shaft. The probe frame is provided with a plurality of probe storage positions distributed along the circumference, and the adjacent included angle is smaller than 90 degrees. A horizontal moving assembly of the probe transfer mechanism drives a fixed plate to reciprocate in the horizontal direction, and a rotating assembly drives a probe frame to rotate around a vertical shaft; the probe butt joint mechanism drives a probe joint to move in the vertical direction through a lifting mechanism, and accurate butt joint and separation of probes are achieved. And the control part coordinates the actions of all the parts to realize automatic replacement of the probe. According to the invention, automatic operation of probe replacement is realized, the replacement efficiency and the measurement precision are improved, and the device is suitable for high-frequency measurement scenes and applications of various probe specifications.

A semiconductor device and a method for preparing the semiconductor device, the semiconductor device comprises a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bit line connection line and a second bit line connection line, the first semiconductor structure comprises a sensing amplifier circuit, the second semiconductor structure is connected to the first semiconductor structure by bonding and comprises a first storage unit, the third semiconductor structure is connected to the second semiconductor structure by bonding and comprises a second storage unit, the first bit line connection line is associated with the first storage unit, the second bit line connection line is associated with the second storage unit, the first bit line connection line and the second bit line connection line are comparatively coupled to each other by the sensing amplifier circuit, and the length difference between the first bit line connection line and the second bit line connection line is less than or equal to 2 microns. The coupling capacitance of adjacent bit lines can be reduced, the anti-crosstalk capability can be improved, and the difference in signal transmission time delay can be reduced, thereby improving the stability and reliability of the device.

The invention discloses a method for improving optical storage capacity based on ultraviolet femtosecond laser multi-cycle low-temperature direct writing, and belongs to the technical field of laser processing. Leveling the sample table; designing a random data structure and calculating parameters; preparing a random data structure; reading and characterizing a random data structure; according to the method, firstly, ultraviolet femtosecond laser with the wavelength of 343 nm is used for replacing infrared / visible band laser used in traditional five-dimensional optical storage, secondly, a multi-cycle scanning mode is used for replacing an existing scanning mode, and birefringence modification with the smaller size is induced in quartz glass at low temperature; the tiny birefringence modification is used for realizing data writing and reading of the optical memory with higher storage density; according to the multi-cycle scanning mode, heat accumulation in the machining process is affected by changing single-point one-way acting time, so that the dot spacing is shortened, and the storage capacity is increased.

A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer and a plurality of second element layers in which a temperature detection circuit, a voltage generation circuit, and a memory cell are provided in each layer. The plurality of second element layers are stacked on the first element layer. The memory cell includes a transistor in which a semiconductor layer having a channel formation region includes an oxide semiconductor. The transistor includes a back gate. A voltage generation circuit provided in each layer has a function of generating a back gate voltage supplied to a back gate of a transistor included in a memory cell provided in the same layer. The temperature detection circuit has a function of controlling the back gate voltage according to the detected temperature. In the second element layer, a back gate voltage supplied to a transistor included in the second element layer disposed in an upper layer is greater than a back gate voltage supplied to a transistor included in the second element layer disposed in a lower layer.

According to the multi-two-dimensional-code data array generation and identification method and system provided by the invention, a plurality of two-dimensional codes are arranged in an array form, and through a corresponding generation and identification algorithm, the original advantages of the two-dimensional codes are maintained, and the information storage density and the identification speed are remarkably improved; the spatial relevance between the two-dimensional codes is fully considered in the multi-two-dimensional code data array generation process, the data storage efficiency is improved, and the error code diffusion condition in the recognition process is avoided; by introducing an error correction extreme value with high robustness and an optimization recognition algorithm, stable recognition of the multi-two-dimensional code data array in a complex environment is ensured; the limitation of an existing two-dimensional code in the aspects of information transmission and processing is effectively solved, a large amount of complex information is transmitted at a time by generating a multi-two-dimensional-code data array, the information storage capacity is greatly improved, more complex scene requirements are met, the scanning frequency is reduced, the information obtaining efficiency is improved, the high recognition accuracy is guaranteed, and the misreading risk is reduced.

The invention relates to a hardware routing table look-up method based on segmented unified storage. The method comprises the following steps: firstly, acquiring an IPv4 / IPv6 routing prefix, dividing the IPv4 / IPv6 routing prefix into 1-4 address fields according to 32 bits, allocating a unique forward and backward segment identifier for each field, constructing table entries containing the segment identifiers, 32-bit segment data and a next hop, and uniformly storing the table entries into the same TCAM. During table lookup, segmenting an address to be looked up according to the same rule, querying the TCAM from a first segment by taking segment data as a key, and recording a backward segment identifier and a next hop after hit; and if the backward segment identifier is invalid, directly returning to the corresponding next hop, and if the backward segment identifier is valid, continuing query by taking the identifier and the next segment of data as a joint key. And when the table item is not hit or the identification verification fails, selecting the table item with the longest prefix and the valid next hop in the matched section, and returning to the next hop. According to the invention, IPv4 / IPv6 routing table entries can be uniformly stored, the TCAM space utilization rate is improved, and meanwhile, the hardware table look-up efficiency is guaranteed.

The invention provides a static random access memory array and a preparation method thereof, a memory and electronic equipment. Relates to the technical field of memories. The purpose is to improve the storage density. The SRAM memory array comprises a semiconductor substrate, a front-channel device layer formed in the semiconductor substrate and a rear-channel device layer stacked on the front-channel device layer, the SRAM storage array further comprises a plurality of storage units, each storage unit comprises at least one P-type field effect transistor and at least one N-type field effect transistor which are electrically connected, for example, the storage units can be 6T storage units or 8T storage units; at least one P-type field effect transistor is formed in the front channel device layer; at least one N-type field effect transistor is formed in the back-end device layer. According to the invention, the P-type field effect transistor and the N-type field effect transistor are stacked in a three-dimensional manner, so that the storage density is improved.

The invention discloses a data storage method and system fusing magneto-optic-electric multiple media, and relates to the technical field of data storage, and the method comprises the steps: collecting multi-dimensional data, carrying out the information coding through a plurality of degrees of freedom of light, and generating a corresponding optical signal; selecting a proper storage medium, and storing the coded optical signal; a data writing mechanism and a data reading mechanism are established to improve efficiency; an intelligent algorithm is adopted to construct a comprehensive evaluation function, storage space is allocated based on the comprehensive evaluation function, and storage resource management is achieved; setting performance indexes to construct a health assessment function, and continuously monitoring the running state of the storage system; according to the invention, information coding is carried out by using multiple degrees of freedom of light, so that the data storage density and the read-write speed are improved; a proper storage medium and an optimized data read-write mechanism are selected, so that data redundancy is reduced, and efficiency is improved; and an intelligent algorithm is adopted for storage space allocation, so that effective management of storage resources is realized.

The invention provides a double-transistor embedded flash memory array. The double-transistor embedded flash memory array comprises a plurality of memory units which are arranged on a substrate in rows and columns, each storage unit comprises a selection tube and a storage tube which are arranged in pairs along a first direction; the active area of the storage array comprises a plurality of strip-shaped first active areas extending along a first direction and a strip-shaped second active area along a second direction; the selection tubes and the storage tubes of the two adjacent storage units in the first direction are arranged in a mirroring mode relative to the second active area, each storage unit forms a second electrode on the second active area, and the second active area is connected with the second electrodes of all the storage units in the second direction. According to the storage array, the continuous active regions are added in the word line direction, and one side of the substrate can be connected with the source line, so that the space between two control grids of an existing structure is reduced, the size of a storage unit is greatly reduced, and the storage density of the storage array is improved.

The invention discloses a railway station container scheduling optimization method, system, equipment and medium, and belongs to the technical field of railway station container scheduling, and the method comprises the steps: building a railway container yard container space assignment optimization model based on a container space freedom degree yard information representation method and a container stacking optimization process, stacking the to-be-stacked boxes by using a box stacking algorithm from a box yard to a train to obtain the optimal stacking positions of the to-be-stacked boxes; extracting the to-be-fetched box by using a box lifting algorithm from a train to a box yard to obtain an optimal target box position of the to-be-fetched box; using a heuristic algorithm to solve the railway container yard container quantity balanced distribution model to obtain the optimal division of the container area container quantity; and solving the railway container yard container space assignment optimization model by using a heuristic algorithm in combination with optimal division of container area container quantity to obtain an optimal container space assignment mode.

Compared with a common structure of a magnetic tunnel junction, the low-power-consumption nonvolatile memory device, the memory array and the preparation method thereof are characterized in that a non-uniform magnetic moment induction layer is additionally sputtered on an upper interface or a lower interface of a free layer or is consistent with the common structure of the magnetic tunnel junction; the difference is that the thickness of the upper ferromagnetic layer or the lower ferromagnetic layer in the free layer is not uniform, the upper ferromagnetic layer or the lower ferromagnetic layer grows in a wedge shape from thin to thick, and the perpendicular magnetic anisotropy is reduced along with increase of the thickness. The invention provides two low-power-consumption nonvolatile memory device structure design schemes and storage array arrangement design, is suitable for a CMOS standard logic circuit, and can effectively improve the writing speed, reduce the MTJ overturning current density and the writing energy consumption, and improve the MRAM storage density.

The intelligent logistics sending and taking device comprises table legs, a main body structure is fixedly connected to the tops of the table legs, a box body is fixedly connected to the tops of the table legs, a management control screen is fixedly connected to the right side of the box body, a storage opening is fixedly connected to the right side of the box body, and the storage opening is formed in the right end of the management control screen; according to the intelligent logistics sending and taking device, through cooperation of the storage plate, the first lead screw and the first motor, the first motor drives the first lead screw to rotate so as to drive the storage plate to move up and down, through the design, a user is allowed to flexibly adjust the position of the storage plate according to the height and the number of stored objects, so that the vertical space is utilized to the maximum extent, and the storage efficiency is improved. The space utilization rate is increased, the storage plates can adapt to articles of different sizes and shapes, the storage cabinet can store more kinds of articles due to the flexibility, storage space does not need to be independently designed for each kind of articles, and the space utilization rate is increased.

The invention relates to the technical field of semiconductors, and provides a semiconductor common block structure, a semiconductor memory and a preparation method thereof, and the semiconductor common block structure comprises a semiconductor common unit structure, a source drain layer and a shielding cover structure. The semiconductor common unit structure comprises a first storage unit and a second storage unit which are distributed side by side in a mirroring manner along a first direction, the first storage unit and the second storage unit share the same source-drain unit layer, and the first direction is parallel to the surface of the substrate; each of the first memory unit and the second memory unit comprises a first transistor and a second transistor, and a fourth source-drain region of the second transistor in the first memory unit and a fourth source-drain region of the second transistor in the second memory unit are respectively connected to two opposite surfaces of the source-drain unit layer; and all the source-drain unit layers in the same plane are sequentially connected end to end to form a source-drain layer. The shielding case structure accommodates all the second transistors therein, and all the first transistors are located outside the shielding case structure.

The invention discloses a multiferroic tunnel junction based on a Janus ferroelectric material, a device and a method. The magnetic tunnel junction comprises a polarization layer; a first ferromagnetic conductive layer is superposed on the upper surface of the polarization layer; a second ferromagnetic conductive layer is arranged on the lower surface of the polarization layer; a first electrode layer is superposed on the upper surface of the first ferromagnetic conductive layer; a second electrode layer is arranged on the lower surface of the second ferromagnetic conductive layer; wherein the polarization layer is made of a Janus ferroelectric material. The method has the advantages of low energy consumption and high storage density.

The invention provides a super-resolution three-dimensional optical storage focusing servo device and a servo method thereof. The device integrates a light source shaping module, a beam combining module, a zooming layer selection module, a servo signal detection module and a driving control module. The solid excitation light and the hollow suppression light are combined to form coaxial recording light, the servo objective lens and the recording objective lens are controlled to move axially by using a signal generated by reflecting the solid servo light by the servo guide layer, and the centers of double light beams are always kept aligned in the read-write process, so that high-speed nano focusing servo is realized. An additional servo light source is not needed, double-beam focuses are adjusted in real time to keep three-dimensional alignment, the diffraction limit is exceeded, and the storage density is improved. The lens group is combined to compensate aberration, zoom and skip layers, so that hundred-layer ultra-high-density storage is realized. The device is simple in structure, convenient to operate and good in compatibility, is applied to the field of super-resolution three-dimensional optical storage, and has a wide application prospect.

The invention provides a memory device and a manufacturing method thereof, and a semiconductor device, and the memory device comprises a substrate which comprises an insulating surface; a memory cell array including a plurality of memory cells disposed on the insulating surface, the plurality of memory cells being repeatedly arranged in a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction; each memory cell comprises a transistor, the transistor comprises a gate insulating layer, a gate structure and an active layer parallel to the insulating surface, the gate structure comprises a gate main body part, the gate main body part comprises a first gate, the first gate extends along the side wall of the active layer, and the gate insulating layer is located between the first gate and the active layer; the bit line structure comprises a plurality of bit lines extending in the first horizontal direction, and the active layer comprises a source end connected to the common source electrode structure and a drain end connected to one bit line. The storage device is high in storage density and simple in preparation process.

The utility model discloses an integrated goods warehouse-in and warehouse-out system, which comprises a first inventory area, a pick-and-place device, a goods picking area, an external handover area and a transfer system, and the external handover area is provided with a plurality of temporary storage grid openings; the transfer system can transfer goods between the goods picking area and the external cross-over area; the first inventory area at least comprises an upper inventory area located above the external handover area; relative to the boundary position between the picking area and the upper stock area, the picking area is located above, below or on the side of the boundary position; or the order picking area is located between the upper stock area and the external handover area. According to the utility model, the functions of storing, sorting, processing goods according to orders and warehousing are integrated, the layout is reasonable and compact, the occupied area is small, multiple types of goods can be stored in the small occupied area, multiple orders can be processed at the same time, the intermediate links are few, and the operation efficiency is high.

The embodiment of the invention provides a memory and a manufacturing method thereof. According to the memory provided by the embodiment of the invention, the first active structure of the first transistor and the second active structure of the second transistor in the memory unit are electrically connected with the same bit line, so that the two transistors can share the same bit line, and the number of the bit lines in the memory can be greatly reduced; therefore, the design difficulty of the memory can be reduced, the manufacturing difficulty of the memory can be reduced, and the manufacturing cost of the memory can be reduced. Moreover, the storage unit comprises a first capacitor and a second capacitor, so that the storage unit can store two-digit data. Moreover, the first capacitor, the first transistor, the second transistor and the second capacitor of the memory unit are sequentially laminated on one side of the substrate, so that the area occupied by the memory unit can be reduced, and the memory density of the memory can be improved.

A storage array, a memory, a reading method thereof, and an electronic device are disclosed. The storage array includes multiple storage cell subarrays, a reference cell column, and a set of reference voltage generation circuits, reference cell switching circuits, and read word line control circuits. The storage cell subarrays and reference cell column in two storage arrays are electrically connected via read bit lines and symmetrically distributed around a read decision unit. The transistors of the reference cells and storage cells are isomorphic and have the same circuit structure. The memory includes at least one pair of open storage arrays, each pair comprising a first storage array, a second storage array, and a set of read decision units. Each storage array is electrically connected to one of the two input terminals of the read decision unit. During reading, the two storage arrays provide a read voltage and a reference voltage, respectively. The two input terminals of the read decision unit have similar RC parameters, and the drift generated by the voltages at the two input terminals is also matched. This application improves storage density and data reading reliability.

A structure of a three-dimensional (3D) memory device and a structure of a system including the three-dimensional (3D) memory device are disclosed. In one example, the 3D memory device includes a storage plane, where the storage plane includes a first edge and an array of blocks. The block array includes: a plurality of memory blocks configured to store data, where the plurality of memory blocks are separated by a continuous slot structure; and a first dummy region between the first edge and the plurality of memory blocks. The first dummy region includes alternating first and second slot structures, where the first and second slot structures are discontinuous slot structures.

The invention belongs to the technical field of DNA information storage, and provides an image compression method, a DNA coding method and a related device thereof for solving the technical problem that an existing DNA information storage coding and decoding algorithm is low in storage density, and the image compression method, the DNA coding method and the related device comprise the steps that firstly, a pixel matrix of each channel of an image to be compressed is segmented, and the minimum value of each segmented matrix is obtained to form a minimum matrix; respectively subtracting the minimum value of the corresponding segmentation matrix from all values in the segmentation matrix to obtain a replacement matrix, respectively converting the replacement matrix and the minimum matrix into digits with the same system and different digits, flattening and splicing to complete compression. According to the method, some information is properly abandoned by utilizing the characteristic that the image information has certain redundancy, so that the integrity of the image in visual perception is maintained while the amount of stored information is reduced. The required storage space can be effectively reduced, and the storage density is increased.

A novel storage device is provided. A plurality of memory cells including two vertical transistors are connected in series. One of the two transistors is used as a transistor for writing information, and the other is used as a transistor for reading information written in the memory cell. The information written in the memory cell is held at the gate of the read transistor. A transistor having a small off-state current is used as the write transistor.

The invention provides a three-dimensional memory preparation process which comprises the following steps: forming a first hard mask layer on a three-dimensional memory substrate, forming a first mesh mask layer on the first hard mask layer, the mesh width of the first mesh mask layer being a, and the mesh width of the first mesh mask layer being b; performing anisotropic etching on the first hard mask layer by taking the first mesh mask layer as a mask to form a circular through hole array, and etching the three-dimensional memory substrate by taking the first hard mask layer as a mask to form a circular through hole array; a fourth hard mask layer is formed on the three-dimensional memory substrate, an annular cylinder array is formed above the fourth hard mask layer, connection lines of cylinder opening circle centers of any four adjacent annular cylinders form a rhombus, and the height of the rhombus is e; a third filling layer is deposited, the top end of the annular cylinder array is exposed through the planarization technology, the annular cylinder array is selectively removed, the remaining third filling layer serves as a mask to etch the fourth hard mask layer, an annular groove array is formed, and the height e of the rhombus is equal to a + b. According to the invention, the memory with a smaller size is prepared.

The invention provides a side window glass storage and transfer device which comprises a device frame, a roll shaft assembly, a front blocking assembly and a partition rod assembly, the device frame is provided with an installation platform, the roll shaft assembly is rotationally installed on the installation platform, the roll shaft assembly is provided with a plurality of conveying units distributed in the first direction, and the conveying units are used for conveying side window glass; the front blocking assembly and the partition rod assembly are fixedly arranged at the top of the device frame, the front blocking assembly is provided with a plurality of front blocking units distributed in the first direction, and the partition rod assembly is provided with a plurality of partition units distributed in the first direction; in the second direction, the front blocking unit, the partition blocking unit and the conveying unit form a vertically-distributed glass channel, and the first direction is perpendicular to the second direction. The device can improve the convenience and safety of side window glass storage, transfer and hoisting of the side window glass are facilitated, and the transfer efficiency of the side window glass is improved.

Embodiments of the present application provide a three-dimensional memory. The three-dimensional memory includes a peripheral circuit chip and a memory array chip, the peripheral circuit chip includes: a first substrate; a first circuit element layer disposed on the first substrate and including a first device layer, the first device layer including a plurality of high-voltage transistors; a second substrate disposed on the first circuit element layer and in contact with the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer, the second device layer including a plurality of low-voltage transistors; the memory array chip is disposed on the second circuit element layer.

This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks, each memory block including multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; the peripheral circuitry is configured to: perform programming operations on the memory cells in the memory blocks; and perform erase operations on at least a portion of the lower select transistors in the lower select transistor set.

The utility model provides an intensive steel platform warehouse, which relates to the technical field of warehouse, and comprises a support frame, the upper part of the support frame is provided with a cross beam, the upper part of the cross beam is provided with a goods shelf, the inner side of the goods shelf is provided with a first bracket and a second bracket, and the first bracket and the second bracket are oppositely arranged; and the number of the first brackets is the same as that of the second brackets. The upper-storage and lower-picking scheme is suitable for storage of various commodity packaging specifications, high in applicability, capable of providing various storage and picking modes of trays, workbins and goods shelves, capable of coping with various business scenes in the same warehouse, especially suitable for industries such as 3PL and supermarket retail, capable of meeting the storage and picking requirements, capable of reducing the leasing area and cost and capable of being popularized and applied. The usable clear height space of the warehouse can be fully utilized, and the storage capacity storage density is fully improved. Compared with an existing tray for densely storing products in the market, the upper-storage and lower-picking scheme is higher in storage density under the same area.