34results about How to "Improve storage density" patented technology

The invention relates to a hardware routing table look-up method based on segmented unified storage. The method comprises the following steps: firstly, acquiring an IPv4 / IPv6 routing prefix, dividing the IPv4 / IPv6 routing prefix into 1-4 address fields according to 32 bits, allocating a unique forward and backward segment identifier for each field, constructing table entries containing the segment identifiers, 32-bit segment data and a next hop, and uniformly storing the table entries into the same TCAM. During table lookup, segmenting an address to be looked up according to the same rule, querying the TCAM from a first segment by taking segment data as a key, and recording a backward segment identifier and a next hop after hit; and if the backward segment identifier is invalid, directly returning to the corresponding next hop, and if the backward segment identifier is valid, continuing query by taking the identifier and the next segment of data as a joint key. And when the table item is not hit or the identification verification fails, selecting the table item with the longest prefix and the valid next hop in the matched section, and returning to the next hop. According to the invention, IPv4 / IPv6 routing table entries can be uniformly stored, the TCAM space utilization rate is improved, and meanwhile, the hardware table look-up efficiency is guaranteed.

A storage array, a memory, a reading method thereof, and an electronic device are disclosed. The storage array includes multiple storage cell subarrays, a reference cell column, and a set of reference voltage generation circuits, reference cell switching circuits, and read word line control circuits. The storage cell subarrays and reference cell column in two storage arrays are electrically connected via read bit lines and symmetrically distributed around a read decision unit. The transistors of the reference cells and storage cells are isomorphic and have the same circuit structure. The memory includes at least one pair of open storage arrays, each pair comprising a first storage array, a second storage array, and a set of read decision units. Each storage array is electrically connected to one of the two input terminals of the read decision unit. During reading, the two storage arrays provide a read voltage and a reference voltage, respectively. The two input terminals of the read decision unit have similar RC parameters, and the drift generated by the voltages at the two input terminals is also matched. This application improves storage density and data reading reliability.

The invention provides a side window glass storage and transfer device which comprises a device frame, a roll shaft assembly, a front blocking assembly and a partition rod assembly, the device frame is provided with an installation platform, the roll shaft assembly is rotationally installed on the installation platform, the roll shaft assembly is provided with a plurality of conveying units distributed in the first direction, and the conveying units are used for conveying side window glass; the front blocking assembly and the partition rod assembly are fixedly arranged at the top of the device frame, the front blocking assembly is provided with a plurality of front blocking units distributed in the first direction, and the partition rod assembly is provided with a plurality of partition units distributed in the first direction; in the second direction, the front blocking unit, the partition blocking unit and the conveying unit form a vertically-distributed glass channel, and the first direction is perpendicular to the second direction. The device can improve the convenience and safety of side window glass storage, transfer and hoisting of the side window glass are facilitated, and the transfer efficiency of the side window glass is improved.

Embodiments of the present application provide a three-dimensional memory. The three-dimensional memory includes a peripheral circuit chip and a memory array chip, the peripheral circuit chip includes: a first substrate; a first circuit element layer disposed on the first substrate and including a first device layer, the first device layer including a plurality of high-voltage transistors; a second substrate disposed on the first circuit element layer and in contact with the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer, the second device layer including a plurality of low-voltage transistors; the memory array chip is disposed on the second circuit element layer.

This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks, each memory block including multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; the peripheral circuitry is configured to: perform programming operations on the memory cells in the memory blocks; and perform erase operations on at least a portion of the lower select transistors in the lower select transistor set.

This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and a memory system. The semiconductor device includes a first gate layer, a second gate layer, a semiconductor body, a third gate layer, and a fourth gate layer; the first gate layer and the second gate layer are spaced apart along a first direction, and the semiconductor body is located between the first gate layer and the second gate layer; the semiconductor body includes a first semiconductor body and a second semiconductor body, which are spaced apart along the first direction; the third gate layer and the fourth gate layer are both located between the first semiconductor body and the second semiconductor body, and the third gate layer and the fourth gate layer are connected at the same end facing the same direction in the first direction, reducing the space required for the semiconductor device to be arranged in a plane perpendicular to the first direction, and improving integration and memory density.

The method comprises the following steps: providing a substrate; forming a plurality of first electrode structures and a plurality of bit lines in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and the bit lines are arranged at intervals along a second direction, and the plurality of first electrode structures are arranged in an array; forming an MTJ structure above the first electrode structures; forming an insulating layer above the substrate, wherein the insulating layer covers the substrate and the MTJ structure; forming a plurality of electrode trenches in the insulating layer, wherein the electrode trenches expose the top surface of the MTJ structure and the top surface of the bit lines; and forming a plurality of second electrode structures in the plurality of electrode trenches. The method can reduce the alignment accuracy requirement when preparing the electrode, reduce the process difficulty, and improve the bit line density.

The utility model is suitable for inductance coil processing technical field provides a kind of cutting device for inductance coil processing, including bottom plate, the top fixed mounting of bottom plate has support, the support is fixedly installed with box body;Fixedly installed on the inner wall of box body top for blocking inductance coil pin baffle;Electric slide rail fixedly installed on the top of bottom plate, the sliding block of electric slide rail is fixedly installed with placing plate, the collecting box for collecting inductance coil pin is provided on the placing groove of placing plate;Assembling on the box body for cutting inductance coil pin cutting mechanism;Installed on the box body for compressing inductance coil pin extrusion mechanism.The cutting device for inductance coil processing provided in the scheme solves the technical problem that the pin of existing inductance coil is after cutting, is fluffy and is accumulated in box body, thereby leading to the technical problem of low space utilization.

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises the components of a substrate which is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate, the first surface is provided with a groove, the substrate is also internally provided with a first via hole, and the first via hole penetrates through the first surface and the second surface and is located at the side of the groove; the first shielding layer covers the bottom wall and the side wall of the groove; the chip is arranged in the groove, the chip is provided with a pin, and the pin is electrically connected with the first via hole; and the second shielding layer covers at least part of the surface, deviating from the bottom wall of the groove, of the chip. The semiconductor packaging structure is used for achieving the effect of improving magnetic shielding comprehensiveness and storage density.

This invention provides a cross-seasonal natural ice-making winter cold storage energy storage mine cooling system, belonging to the field of mine heat hazard control technology. It includes a cold storage subsystem and an underground cooling subsystem, coupled via a four-way reversing valve. The cold storage subsystem includes an ice storage tank, a water supply assembly, and a spray enhancement module. The outlet of the ice storage tank is connected to the inlet of the water supply assembly, and the outlet of the water supply assembly is connected to the first interface of the four-way reversing valve. The spray enhancement module is connected to the second interface of the four-way reversing valve. The underground cooling subsystem includes an air cooler, a second fan, a chilled water pipe, and a return water pipe. One end of the chilled water pipe is connected to the third interface of the four-way reversing valve, and the other end is connected to the inlet of the air cooler. The outlet of the air cooler is connected to the return water pipe, and the end of the return water pipe furthest from the air cooler is connected to the fourth interface of the four-way reversing valve. This mine cooling system has a simple structure, low energy consumption, low cost, and high energy storage efficiency.

The utility model discloses a special alcoholization oak barrel for cigars, and belongs to the field of cigarette processing devices. The device comprises a curing barrel, side plates, an upper-layer plate, a lower-layer plate and a bottom box, a sealing barrel cover is inserted into the end of the curing barrel, the side plates are symmetrically arranged in the curing barrel, and the upper-layer plate and the lower-layer plate which can slide transversely are vertically inserted between the side plates. The transmission mechanism is composed of a toothed plate, a transmission gear, a transmission shaft and a rotating wheel, the rotating wheel is rotated to drive the upper-layer plate and the lower-layer plate to slide reversely, non-contact turning of cigars is achieved, and temperature and humidity fluctuation caused by uncovering operation is avoided. A circulating fan, a drying agent and a humidifying bag are arranged in the bottom box, a directional airflow circulating system is formed by combining a mesh plate, and precise environment regulation and control are achieved by cooperating with a top temperature and humidity monitor. Vent holes are uniformly formed in the side plates and the layer plates, so that the ventilation uniformity is guaranteed while the storage density is enhanced. The cigar mellowing device solves the problems that a traditional device is low in laminate fixing and turning efficiency, lags behind temperature and humidity control and the like, and the cigar mellowing uniformity and curing stability are remarkably improved.

A capacitor structure and a method for forming the same are disclosed. The structure includes: a plurality of intermediate electrode layers, each of the intermediate electrode layers includes: a first intermediate electrode end and a second intermediate electrode end; a plurality of first intermediate finger plates located between the first intermediate electrode end and the second intermediate electrode end, the first intermediate finger plates include: a plurality of first segments and a plurality of second segments; the first segments and the second segments of adjacent upper and lower layers have a facing area. Since the gap between the first segments and the second segments can be controlled in a small range by a photolithography process, the storage density between the first segments and the second segments, and between the first finger plugs and the second finger plugs can be ensured to be large, thereby improving the storage density of the capacitor structure.

The utility model provides an in-memory computing array, an in-memory computing macro circuit and in-memory computing equipment, and the in-memory computing array comprises a memory unit group which can store data for computing; a calculation unit for performing a calculation operation; a latch capable of storing data read from the memory cell group; the global bit line switch is connected between a global bit line and the memory unit group, the global bit line can realize data interaction between the in-memory computing array and the outside, and the global bit line switch is configured to be switched off in response to a computing operation instruction, and the global bit line switch is configured to be switched off in response to the computing operation instruction. And reading data from the memory unit group to the latch for executing calculation operation, and closing the latch after the latch finishes data latching, so that the memory unit group reads / writes data through the global bit line, and the calculation operation and the read-write operation are parallel.

The application provides a non-volatile semiconductor memory array and a method for in-memory logic operation. In the array, a row of memory cells shares a word line, a column of memory cells shares a bit line and a storage gate lead, the source terminals of every two columns of memory cells are interconnected and connected to the same source lead CSL, and the end of each CSL is provided with a sensitive amplifier SA controlled by an enabling signal. One of the memory cells in every two columns has a substrate split, or the cell is replaced by a DCC cell. The method includes pre-writing, pre-charging, charging and discharging estimation, and judgment and result writing. The input and output are the storage states of different memory cells. The charging and discharging of the parasitic capacitor on the source lead when the memory cell is opened are detected as the input, and the SA is used to make a logic judgment and complete the writing. In one operation, any two-input logic except XOR and XNOR can be realized, and the logic result can be directly used as a logic input to realize cascading. The logic operation has many types, few steps, low difficulty and high efficiency.

The invention relates to a multilayer vertically-stacked hundred million resistance memory and a manufacturing method thereof, belongs to the technical field of memories, and solves the problem of current crosstalk caused by density increase of an existing memory unit. The memory includes an underlying circuit over a semiconductor substrate and provided with layer and column addressing switches; the bottom insulating layer is positioned above the bottom layer circuit and is provided with a plurality of through holes; a plurality of alternate stacks over the underlying circuit, each of the alternate stacks comprising a planar conductive layer and an interlayer insulating layer over the planar conductive layer; the vertical columnar electrode passes through the plurality of alternate laminations to be electrically connected with the plurality of through holes; the resistive random access medium layer surrounds the periphery of the vertical columnar electrode, so that the planar conductive layer, the resistive random access medium layer and the vertical columnar electrode form a resistive random access memory; the region isolation trench includes a plurality of rows and columns of parallel isolation trenches passing through the plurality of alternating stacks, the bottom insulating layer, and the underlying circuitry to isolate the three-dimensional memory array into a plurality of memory cell regions. And inter-layer and inter-row current crosstalk is reduced through block division and insulation partition.

The invention relates to a storage and calculation integrated peripheral circuit device based on a 3D VRRAM and a matrix calculation method, belongs to the technical field of memories, and solves the problem that the structure of an existing two-dimensional resistive random access memory array is not suitable for a neural network with a high calculation power demand. The device comprises a matrix multiplier for multiplying an input data matrix by a weight matrix; the input ends of the analog-to-digital converters are connected to the output ends of the column control switches so as to convert the analog product result into a digital product result; the plurality of samplers are connected with the output end of the analog-to-digital converter so as to sample the digital product result; the output ends of the plurality of samplers are connected with the input end of the matrix adder through the matrix adder so as to realize digital product result shifting, then shifting data are accumulated, and an accumulation result is stored in a temporary register; and the updating register adds the accumulation result and the data in the updating register to obtain sum data, and updates the data in the updating register by using the sum data. And high-storage and high-computing-power-density operation is realized so as to be suitable for a neural network.

The application relates to a DNA self-assembly nano-floating gate type 3D NAND structure, which comprises a substrate, a periodic stack structure arranged on the substrate, the stack structure comprising a plurality of first insulating medium layers and nano-floating gate storage structures alternately stacked, a plurality of through holes penetrating through the stack structure, a center channel layer being arranged on the side wall of the through hole, and a center insulating medium layer being filled in the center channel layer; wherein the nano-floating gate storage structure comprises a tunneling medium layer contacting the center channel layer, a blocking medium layer wrapping the outside of the tunneling medium layer, and a gate word line metal located outside the blocking medium layer, and a carbon nanotube floating gate layer is arranged in the tunneling medium layer. The structure can significantly improve the storage density and size miniaturization ability, and greatly reduce the working voltage and driving power consumption.

The invention provides a three-dimensional storage and near storage computing architecture which can be applied to the technical field of circuit design. The three-dimensional storage and near-storage computing architecture comprises a control layer, which comprises a gating module and a driving module; the plurality of storage layers are stacked on the surface of the control layer, and each storage layer comprises a plurality of storage units; wherein the gating module is used for controlling a target storage layer in the plurality of storage layers to be in a working state under the control of a gating signal; and the driving module is used for controlling the target storage unit in the target storage layer to execute read-write operation.

The embodiment of the utility model provides a warehousing system and a transfer robot. The warehousing system comprises a plurality of carriers, and carrier stand columns of the adjacent carriers are oppositely arranged at intervals; the transfer robot comprises a vehicle body, a walking mechanism and a climbing mechanism, the walking mechanism is arranged on the vehicle body, and the walking mechanism is configured to drive the vehicle body to walk in the first direction; the climbing mechanism is arranged at a first part of the vehicle body and can stretch out and draw back relative to the vehicle body from the two sides of the vehicle body in the radial direction of the vehicle body; the climbing mechanism is configured to be matched with carrier stand columns of two adjacent carriers on the two sides of the vehicle body so as to drive the vehicle body to ascend and descend along the carrier stand columns. Wherein the first direction intersects with the extending direction of the carrier stand column. The number of meshing structures arranged on the goods shelf stand column can be reduced, and the requirement for the installation precision of the goods shelf stand column is lowered.

The application discloses a method for simultaneously realizing color nano printing and color holography and a metasurface, and the method comprises the following steps: constructing a nano brick array; obtaining a color nano printing image, determining the long axis and the short axis of the nano brick in the nano brick structure unit at each position according to the color presented by the nano brick structure unit with different size parameters; obtaining a color holographic image, and determining the turning angle of the nano brick in the nano brick structure unit at each position; arranging the nano brick structure unit with the corresponding size at each position according to the corresponding nano brick turning angle determined above, and obtaining the required metasurface; and incident white light on the metasurface, and the reflected light forms a color nano printing image on the metasurface; and incident circularly polarized light with wavelengths of λ R , λ G , λ B on the metasurface, and a color holographic image is displayed on the design distance plane. The application can realize the display multiplexing of the color nano printing image and the color holographic image simultaneously by using one metasurface, and the information storage density is high.

The application relates to an ultra-low-power nanometer floating gate 3D NAND structure, which comprises a substrate, a stack structure arranged on the substrate, the stack structure comprising a plurality of first insulating medium layers and nanometer floating gate storage structures which are alternately stacked, a plurality of through holes penetrating through the stack structure, a tunneling medium layer and a center channel layer being sequentially arranged on the sidewall of each through hole, and a center insulating medium layer being filled in the center channel layer; the nanometer floating gate storage structure is vertically arranged with the tunneling medium layer of the sidewall of the through hole, a second insulating medium layer and a blocking medium layer are sequentially arranged in the direction from the tunneling medium layer to the outside of the through hole, a gate word line metal is embedded on the outside of the blocking medium layer, and a nanometer floating gate layer is arranged below the second insulating medium layer and part of the blocking medium layer. The structure can effectively inhibit charge coupling interference and reduce working voltage and power consumption while further reducing the word line spacing to realize high-density size miniaturization.

The embodiment of the application provides an OHT storage device and system, comprising a mother vehicle and a child vehicle. The overhead track crane is arranged in the air, the mother vehicle is arranged on the overhead track in cooperation, and the child vehicle is suspended on the mother vehicle. The child vehicle comprises a cargo carrying platform, a supporting assembly and a telescopic conveying assembly. The cargo carrying platform is suspendedly connected with the mother vehicle, the mother vehicle drives the cargo carrying platform to move along the overhead track, and the cargo carrying platform is used for carrying goods. The supporting assembly is arranged on the cargo carrying platform and is used for selectively abutting against a fixed part, so as to stabilize the cargo carrying platform, avoid shaking of the cargo carrying platform in the process of taking and placing goods, and improve the stability of taking and placing goods. The telescopic conveying assembly is arranged on the cargo carrying platform and is used for selectively extending out of the cargo carrying platform to convey goods, so as to conveniently move the goods into or out of the cargo carrying platform.

A memory and an access method thereof, and an electronic device, the memory comprising: a vertically stacked multi-layer memory cell array; the memory cell array comprising: a plurality of array-distributed memory cells, a plurality of bit lines, a plurality of source lines, a plurality of write word lines, and a plurality of read word lines; the memory cell comprising a read control unit and a write control unit, the read control unit being connected to the source line, the bit line, and the read word line, the write control unit being connected to the read control unit, the write word line, and the bit line, the plurality of source lines being connected to the same common source line, the bit line and the source line connected to the same memory cell being connected through an isolation sub-circuit, the isolation sub-circuit further being connected to an isolation control line, and the isolation sub-circuit being configured to electrically connect or disconnect the bit line and the source line under the control of the isolation control line. The scheme provided by the embodiments of the present disclosure sets the isolation sub-circuit between the bit line and the source line, and the plurality of source lines are connected to the same common source line, so that it is not necessary to set a ladder structure for the source line, the memory cell array area is reduced, and the storage density is increased.

The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate and a plurality of memory structures stacked on the substrate; the memory structure comprising: a first dielectric layer and a channel layer located in the first dielectric layer and extending along a first direction, the first dielectric layer having a first recess separating the channel layer; a capacitor structure covering the sidewall and the bottom surface of the first recess.

The application discloses a preparation method of a semiconductor device and electronic equipment, and the method comprises the following steps: alternately stacking a plurality of insulating layers and metal layers on a substrate to form a laminated structure; forming a plurality of transistors arranged in a multilayer array in the laminated structure, wherein the transistors comprise a via, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite sidewalls of the via; the channel layer covers the sidewalls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, the semiconductor device comprises a plurality of switch units and a plurality of word lines; the plurality of switch units are distributed in an array at intervals along the row direction and the column direction parallel to the substrate; each switching cell includes: a first transistor including a first electrode, a second electrode, a first semiconductor layer, a first gate electrode, and a gate insulating layer; a second transistor including a third electrode, a fourth electrode, a second semiconductor layer, a second gate electrode, and a gate insulating layer; the first semiconductor layer and the second semiconductor layer extend along a direction vertical to the substrate; the conduction type of one of the first transistor and the second transistor is N type, and the conduction type of the other transistor is P type; the word lines are distributed at intervals and extend in the direction perpendicular to the substrate. And each word line is connected with one switch unit. The switch unit of the semiconductor device is small in area and good in performance.

This disclosure provides a semiconductor device, its operation method, packaging structure, and system. The semiconductor device includes a first semiconductor structure and a second semiconductor structure, with a first side of the first and second semiconductor structures bonded together. The first semiconductor structure includes an analog-to-digital converter (ADC). The second semiconductor structure includes a memory array, multiple bit lines, and multiple first connection structures. The memory array is located between the multiple bit lines and the first side of the second semiconductor structure, and the multiple first connection structures are located between the multiple bit lines and the first semiconductor structure. Each bit line is connected to the ADC through a first connection structure.

This invention relates to the field of in-memory computing, specifically a 2F-1T-1C cell circuit, an in-memory computing circuit, and a chip. The cell circuit includes N-type FeFET transistors F1 and F2, an NMOS transistor M0, and a capacitor C0. The source of M0 and the drains of F1 and F2 are connected to one end of C0 and serve as node X; the other end of C0 is grounded. The gate of M0 is connected to the precharge enable line SAE, and the drain of M0 is connected to the precharge voltage line AWL. The gates of F1 and F2 are connected to word lines WLA and WLB, respectively, and the sources of F1 and F2 are connected to input signal lines SL1 and SL2, respectively. It can support the storage and multiplication of signed numbers and supports XOR operations on unsigned numbers. When applied to an in-memory computing circuit, it can further realize multiply-accumulate operations between signed numbers and complex content addressing. This invention solves the problem of insufficient efficiency of existing FeFET-based NVMs in BNN tasks.

The embodiment of the present disclosure relates to a semiconductor structure and a preparation method thereof, the semiconductor structure comprising: a substrate, a first doped region and a second doped region in the substrate, a first selection transistor and a second selection transistor, a conductive layer between the first doped region and the second doped region, a resistive switching dielectric layer, the conductive layer, the first doped region and the resistive switching dielectric layer opposite to the first doped region form a first variable resistor, the conductive layer, the second doped region and the resistive switching dielectric layer opposite to the second doped region form a second variable resistor, and an isolation dielectric layer between the conductive layer and the substrate. The embodiment of the present disclosure is beneficial to improve the storage density of RRAM memory.

The utility model provides a rotatable servo tool magazine which comprises a machine frame, a servo motor and a cutter head, and the servo motor is installed in the machine frame through a bolt. The output end of the servo motor penetrates through the top of the rack and is connected with a cutter head; the device is characterized in that the outer side wall of the cutter head is connected with a cutter rest through a plurality of detachable mounting modules; a tray is mounted on the outer side wall of the rack through bolts, and a jacking convex block is connected to the top of the tray through bolts; when reaching the position of the jacking convex block, the appointed knife rest is lifted under the action of the jacking convex block; the servo tool magazine effectively solves the problem that adjacent tools collide with each other during tool changing in the compact design of a traditional servo tool magazine, improves the space utilization rate and the tool changing efficiency of the tool magazine, and meets the requirements of the modern manufacturing industry for efficient and high-precision machining.