11results about How to "Improve storage density" patented technology

A storage array, a memory, a reading method thereof, and an electronic device are disclosed. The storage array includes multiple storage cell subarrays, a reference cell column, and a set of reference voltage generation circuits, reference cell switching circuits, and read word line control circuits. The storage cell subarrays and reference cell column in two storage arrays are electrically connected via read bit lines and symmetrically distributed around a read decision unit. The transistors of the reference cells and storage cells are isomorphic and have the same circuit structure. The memory includes at least one pair of open storage arrays, each pair comprising a first storage array, a second storage array, and a set of read decision units. Each storage array is electrically connected to one of the two input terminals of the read decision unit. During reading, the two storage arrays provide a read voltage and a reference voltage, respectively. The two input terminals of the read decision unit have similar RC parameters, and the drift generated by the voltages at the two input terminals is also matched. This application improves storage density and data reading reliability.

This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks, each memory block including multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; the peripheral circuitry is configured to: perform programming operations on the memory cells in the memory blocks; and perform erase operations on at least a portion of the lower select transistors in the lower select transistor set.

The utility model is suitable for inductance coil processing technical field provides a kind of cutting device for inductance coil processing, including bottom plate, the top fixed mounting of bottom plate has support, the support is fixedly installed with box body;Fixedly installed on the inner wall of box body top for blocking inductance coil pin baffle;Electric slide rail fixedly installed on the top of bottom plate, the sliding block of electric slide rail is fixedly installed with placing plate, the collecting box for collecting inductance coil pin is provided on the placing groove of placing plate;Assembling on the box body for cutting inductance coil pin cutting mechanism;Installed on the box body for compressing inductance coil pin extrusion mechanism.The cutting device for inductance coil processing provided in the scheme solves the technical problem that the pin of existing inductance coil is after cutting, is fluffy and is accumulated in box body, thereby leading to the technical problem of low space utilization.

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises the components of a substrate which is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate, the first surface is provided with a groove, the substrate is also internally provided with a first via hole, and the first via hole penetrates through the first surface and the second surface and is located at the side of the groove; the first shielding layer covers the bottom wall and the side wall of the groove; the chip is arranged in the groove, the chip is provided with a pin, and the pin is electrically connected with the first via hole; and the second shielding layer covers at least part of the surface, deviating from the bottom wall of the groove, of the chip. The semiconductor packaging structure is used for achieving the effect of improving magnetic shielding comprehensiveness and storage density.

A capacitor structure and a method for forming the same are disclosed. The structure includes: a plurality of intermediate electrode layers, each of the intermediate electrode layers includes: a first intermediate electrode end and a second intermediate electrode end; a plurality of first intermediate finger plates located between the first intermediate electrode end and the second intermediate electrode end, the first intermediate finger plates include: a plurality of first segments and a plurality of second segments; the first segments and the second segments of adjacent upper and lower layers have a facing area. Since the gap between the first segments and the second segments can be controlled in a small range by a photolithography process, the storage density between the first segments and the second segments, and between the first finger plugs and the second finger plugs can be ensured to be large, thereby improving the storage density of the capacitor structure.

The application provides a non-volatile semiconductor memory array and a method for in-memory logic operation. In the array, a row of memory cells shares a word line, a column of memory cells shares a bit line and a storage gate lead, the source terminals of every two columns of memory cells are interconnected and connected to the same source lead CSL, and the end of each CSL is provided with a sensitive amplifier SA controlled by an enabling signal. One of the memory cells in every two columns has a substrate split, or the cell is replaced by a DCC cell. The method includes pre-writing, pre-charging, charging and discharging estimation, and judgment and result writing. The input and output are the storage states of different memory cells. The charging and discharging of the parasitic capacitor on the source lead when the memory cell is opened are detected as the input, and the SA is used to make a logic judgment and complete the writing. In one operation, any two-input logic except XOR and XNOR can be realized, and the logic result can be directly used as a logic input to realize cascading. The logic operation has many types, few steps, low difficulty and high efficiency.

The invention relates to a storage and calculation integrated peripheral circuit device based on a 3D VRRAM and a matrix calculation method, belongs to the technical field of memories, and solves the problem that the structure of an existing two-dimensional resistive random access memory array is not suitable for a neural network with a high calculation power demand. The device comprises a matrix multiplier for multiplying an input data matrix by a weight matrix; the input ends of the analog-to-digital converters are connected to the output ends of the column control switches so as to convert the analog product result into a digital product result; the plurality of samplers are connected with the output end of the analog-to-digital converter so as to sample the digital product result; the output ends of the plurality of samplers are connected with the input end of the matrix adder through the matrix adder so as to realize digital product result shifting, then shifting data are accumulated, and an accumulation result is stored in a temporary register; and the updating register adds the accumulation result and the data in the updating register to obtain sum data, and updates the data in the updating register by using the sum data. And high-storage and high-computing-power-density operation is realized so as to be suitable for a neural network.

The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate and a plurality of memory structures stacked on the substrate; the memory structure comprising: a first dielectric layer and a channel layer located in the first dielectric layer and extending along a first direction, the first dielectric layer having a first recess separating the channel layer; a capacitor structure covering the sidewall and the bottom surface of the first recess.

This invention relates to the field of in-memory computing, specifically a 2F-1T-1C cell circuit, an in-memory computing circuit, and a chip. The cell circuit includes N-type FeFET transistors F1 and F2, an NMOS transistor M0, and a capacitor C0. The source of M0 and the drains of F1 and F2 are connected to one end of C0 and serve as node X; the other end of C0 is grounded. The gate of M0 is connected to the precharge enable line SAE, and the drain of M0 is connected to the precharge voltage line AWL. The gates of F1 and F2 are connected to word lines WLA and WLB, respectively, and the sources of F1 and F2 are connected to input signal lines SL1 and SL2, respectively. It can support the storage and multiplication of signed numbers and supports XOR operations on unsigned numbers. When applied to an in-memory computing circuit, it can further realize multiply-accumulate operations between signed numbers and complex content addressing. This invention solves the problem of insufficient efficiency of existing FeFET-based NVMs in BNN tasks.

The embodiment of the present disclosure relates to a semiconductor structure and a preparation method thereof, the semiconductor structure comprising: a substrate, a first doped region and a second doped region in the substrate, a first selection transistor and a second selection transistor, a conductive layer between the first doped region and the second doped region, a resistive switching dielectric layer, the conductive layer, the first doped region and the resistive switching dielectric layer opposite to the first doped region form a first variable resistor, the conductive layer, the second doped region and the resistive switching dielectric layer opposite to the second doped region form a second variable resistor, and an isolation dielectric layer between the conductive layer and the substrate. The embodiment of the present disclosure is beneficial to improve the storage density of RRAM memory.

The utility model relates to MPP cable protection tube storage technical field, specifically disclose a kind of placing device of MPP cable protection tube, including multiple upper and lower distribution's support plate, the front and rear ends of multiple support plate are commonly provided with telescopic mechanism, the telescopic mechanism includes the X folding frame between the setting of adjacent two support plates, the upper end surface of the support plate located in upper is fixedly connected with vertical plate, the outer wall of vertical plate and multiple X folding frame is rotatably connected with support shaft, through the telescopic mechanism of X folding frame and electric push rod linkage, the automatic adjustment of support plate spacing is realized, can flexibly adapt to the MPP protection pipe stacking demand of different height, greatly improve the storage density of unit space, compared with traditional single-layer storage mode, improve storage capacity, rain cloth can be quickly unfolded, cooperate with rain baffle to form double-layer waterproof barrier, ensure that MPP protection pipe is not eroded by rain when storing outdoors, avoid the performance decline of pipe material due to damp.