2005 results about "Gate stack" patented technology

Provided are a memory device and a method of manufacturing the same. The memory device includes a peripheral stack including a plurality of circuits, a lower cell array stack including a gate stack including a plurality of gate lines, a gate line contact passing through at least a part of the gate stack and electrically connected to a gate line selected from among the plurality of gate lines, a plurality of through-vias passing through the gate stack and connected to corresponding ones of the plurality of circuits of the peripheral circuit stack, and a wiring structure connecting one of the plurality of through-vias to the gate line contact.

The invention provides a method for manufacturing a semiconductor device and a vertically stacked semiconductor device, which can be applied to the technical field of semiconductors. The manufacturing method includes: disposing a lower field effect transistor and an upper field effect transistor on a substrate, the lower field effect transistor and the upper field effect transistor being stacked in a vertical direction; the upper surface of the substrate is connected with the lower surface of the lowermost gate stack in the lower field effect transistor and the lower surface of the source / drain layer; forming a full silicide layer on the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer; patterning the full silicide layer to form an opening which exposes the lower surface of the lowermost gate stack in the lower field effect transistor, and forming silicide layer patterns which are arranged on the two sides of the opening in the first direction and are connected with the lower surface of a source / drain layer in the lower field effect transistor at the same time; filling a dielectric material in the opening so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; a contact hole is provided in contact with the silicification layer pattern.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

The invention discloses a semiconductor device, relates to the technical field of semiconductors, and aims to reduce stray capacitance between gate stack structures and improve alternating current characteristics of the semiconductor device. The semiconductor device comprises a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulating layer, a first dielectric isolation layer and a second dielectric isolation layer. The insulating layer is disposed between the source / drain region included in the first gate-all-around transistor and the source / drain region included in the second gate-all-around transistor. And the first dielectric isolation layer and the second dielectric isolation layer are alternately stacked between a channel region included in the first gate-all-around transistor and a channel region included in the second gate-all-around transistor. A gate stack structure included in the first gate-all-around transistor and / or a gate stack structure included in the second gate-all-around transistor are located on the periphery of the first dielectric isolation layers and the second dielectric isolation layers which are alternately stacked, and film layers, located on the bottom layer and the top layer, in the first dielectric isolation layers and the second dielectric isolation layers which are alternately stacked are the first dielectric isolation layers.

Integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.

Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.

One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source / drain (S / D) feature, a second S / D feature, a channel region interposed between the first and second S / D features, and a gate stack engaging the channel region. The semiconductor device includes a first S / D contact landing on a top surface of the first S / D feature, a second S / D contact landing on a top surface of the second S / D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S / D feature. The dielectric plug spans a width equal to or smaller than a width of the first S / D feature.

A method includes etching a gate stack to form a trench extending through the gate stack, the gate stack including a metal gate electrode and a gate dielectric, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion; extending the trench through an isolation region under the gate stack and into a semiconductor substrate under the isolation region; conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.

A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

The invention provides a method for forming a strained silicon layer and a semiconductor structure, which comprises the steps of covering a semiconductor layer and a gate stack structure to form an etching stop layer, and the semiconductor layer comprises a first device region and a second device region which are separated from each other; forming an auxiliary side wall surrounding the side wall of the gate stack structure on the etching stop layer; forming a patterned hard mask layer; taking the patterned hard mask layer as an etching mask, and performing selective etching on the second device region through a wet etching process to form a sigma trench; and growing a strained silicon layer in the sigma groove. According to the invention, on the premise of not sacrificing the consistency of the critical dimensions of the sigma trench, the etching load effect caused by dry etching in the forming process of the sigma trench is avoided.

A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

Embodiments relate to a transistor having a substrate and a gate formed in or on a surface of the substrate. The gate can include a piezoelectric material. The transistor has a drain and a source formed in or on a surface of the gate. The transistor has a channel formed adjacent to the gate and located between the drain and the source. The channel can include a semiconductor / semi-metallic material. The transistor can have a source contact formed at the source and configured to anchor the semiconductor / semi-metallic channel material to the piezoelectric material. The transistor can have a drain contact formed at the drain and configured to anchor the semiconductor / semi-metallic channel material to the piezoelectric material. The transistor operates on the principle of voltage induced strain transduction via a piezoelectric gate stack leading to a modification of the interface between the metal contact and the semiconducting / semi-metallic channel material.

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

A method includes forming a first source / drain region and a second source / drain region in a semiconductor fin; depositing a first dielectric layer over the first source / drain region and the second source / drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source / drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source / drain region, resulting in a source / drain trench; partially recessing the second layers exposed in the source / drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.

The invention provides a method for forming an embedded source-drain region. The method comprises the following steps of: covering a semiconductor layer and a gate stack structure to form a sacrificial layer; covering the side wall of the gate stack structure with a sacrificial layer to form an auxiliary side wall; and covering the first device region with a patterned mask layer, etching the second device region by taking the auxiliary side wall and the sacrificial layer as masks to form a sigma trench extending to enter the lower part of the gate stack structure, and simultaneously thinning the sacrificial layer covering the top surface of the gate stack structure of the second device region. According to the forming method, the etching loss of the gate stack structure of the corresponding device region can be reduced, the height difference of the isolation side walls between the PMOS region and the NMOS region is reduced or eliminated, the influence of different etching loads on the subsequent process is avoided, and the process stability is improved on the premise that the process cost and the process complexity are not improved.

A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.

A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

A method includes forming a first complementary Field-Effect Transistor (CFET) and a second CFET. The first CFET includes a first lower transistor, and a first upper transistor overlapping the first lower transistor. The second CFET includes a second lower transistor, and a second upper transistor overlapping the second lower transistor. The method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching a first gate stack between the first upper transistor and the second upper transistor, and etching a second gate stack between the first lower transistor and the second lower transistor. The first opening is filled with a dielectric material to form a dielectric region. The method further includes performing a second etching process to etch a middle portion of the dielectric region and to form a second opening, and filling the second opening with a conductive material to form a through-via.

Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

Integrated circuit structures having backside plug last approach are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and a nanostructure stack. The method includes forming a first gate stack and a second gate stack wrapped around the nanostructure stack. The method includes forming a first source / drain structure in the nanostructure stack and between the first gate stack and the second gate stack. The method includes removing the second gate stack, the nanostructure stack and the fin under the second gate stack to form a trench passing through the nanostructure stack and the fin. The method includes forming a dielectric isolation structure in the trench. The method includes removing the first gate stack and the first nanostructure. The method includes forming a third gate stack wrapped around the second nanostructure. The method includes forming a first contact structure over the first source / drain structure.

Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells stacked vertically above a semiconductor substrate. Each memory cell stores a weight. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells. In one example, each memory cell is formed using a transistor that includes a semiconductor layer to provide a horizontal channel. A gate layer (e.g., a gate stack layer) wraps around a circumference of the semiconductor layer. Wordlines apply gate voltages to the transistors. Each wordline has a respective portion that wraps around a circumference of the gate layer of each transistor.

A semiconductor fabrication method includes: providing a separating wall and a plurality of liners including a first liner and a second liner between a first fin and a second fin having an epitaxial stack and a sacrificial gate stack over channel regions of the second fin; recessing a sacrificial epitaxial layer of the epitaxial stack to form a cavity; recessing the first line thereby expanding the cavity; recessing the second liner thereby expanding the cavity; forming inner spacer material in the first and second cavities; forming source / drain features; and replacing the sacrificial epitaxial layer and the sacrificial gate stack with a metal gate layer; wherein the metal gate layer has a first critical dimension (CD) measured between the inner spacer material, and wherein the first liner after recessing has a second CD measured between the inner spacer material that is approximately equal to the first CD.

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a first region and a second region, where a Flash memory cell gate stack is formed in the first region, a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation.

Integrated circuit structures having backside contact reveal uniformity, and methods of fabricating integrated circuit structures having backside contact reveal uniformity, are described. In an example, an integrated circuit structure includes an integrated circuit structure including a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive source or drain contact is vertically beneath and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is in a cavity in the isolation layer. The isolation layer extends laterally beneath the gate stack.