1158 results about "Gate stack" patented technology

Provided are a memory device and a method of manufacturing the same. The memory device includes a peripheral stack including a plurality of circuits, a lower cell array stack including a gate stack including a plurality of gate lines, a gate line contact passing through at least a part of the gate stack and electrically connected to a gate line selected from among the plurality of gate lines, a plurality of through-vias passing through the gate stack and connected to corresponding ones of the plurality of circuits of the peripheral circuit stack, and a wiring structure connecting one of the plurality of through-vias to the gate line contact.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.

Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

An integrated circuit structure includes a device layer including a plurality of devices. The plurality of devices includes (i) a plurality of source and drain regions, (ii) a plurality of gate stacks, and (iii) a plurality of gate spacers, each gate spacer separating a corresponding source or drain region from a corresponding gate stack, the gate spacers comprising a first dielectric material. A first source or drain contact is coupled to a frontside of a first source or drain region of the plurality of source or drain regions. A second dielectric material is coupled to a backside of the first source or drain region. A second source or drain contact is coupled to a backside of a second source or drain region of the plurality of source or drain regions. In an example, the first dielectric material and the second dielectric material comprise the same elemental constituents.

Dipole engineering techniques are disclosed herein that may be implemented when fabricating gate stacks, such as a gate stack of a transistor. An exemplary method for forming a gate stack of a transistor includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives aluminum from the p-dipole dopant source layer into the high-k dielectric layer, and after removing the p-dipole dopant source layer, forming at least one electrically conductive gate layer over the high-k dielectric layer. The p-dipole dopant source layer includes an aluminum layer. The p-dipole dopant source layer may further include an aluminum oxide layer and / or an aluminum nitride layer.

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for increasing the thickness of at least partial region of a gate side wall along the thickness direction of a semiconductor substrate, so that the region with larger thickness in the gate side wall has a stronger protection effect, a process window is expanded, and the yield is improved. The risk of generating defects in the semiconductor device is reduced, and the yield of the semiconductor device is improved. The semiconductor device includes a semiconductor substrate, and a transistor disposed on the semiconductor substrate. In the transistor, gate side walls are at least arranged on the two sides of a gate stack structure in the length direction. In the thickness direction of the semiconductor substrate, the surfaces of different areas in the side faces, away from the gate stack structure, of the gate side walls are roughly aligned, and the thickness of partial areas of the gate side walls is larger than that of other areas of the gate side walls. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

The embodiment of the invention provides a semiconductor device and a forming method thereof. A method of forming a semiconductor device includes forming a first transistor and a second transistor on a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of the first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on a backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. A backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source / drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source / drain region.

A method for forming a flash memory includes forming an isolation layer to surround a plurality of active regions, forming a plurality of gate stacks across the active regions and the isolation layer, implanting a dopant into an upper portion of the isolation layer to form a doped isolation layer, partially recessing the doped isolation layer, and forming a dielectric material over the plurality of gate stacks, the plurality of active regions, and the doped isolation layer.

A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

Integrated circuit structures having front-side-cut backside source or drain contacts are described. In an example, an integrated circuit structure includes a first gate stack over a first plurality of horizontally stacked nanowires or fin, and a second gate stack over a second plurality of horizontally stacked nanowires or fin. A first epitaxial source or drain structure is at an end of the first plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a backside contact structure thereon. A second epitaxial source or drain structure is at an end of the second plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is laterally between and in contact with the backside dielectric structure and the backside contact structure.

A semiconductor device includes a substrate; a channel layer over the substrate; a gate stack and a gate spacer pattern over the channel layer; an interlayer insulating layer covering the gate stack and the gate spacer pattern; and a contact pattern vertically passing through the interlayer insulating layer to be connected to the substrate. the contact pattern includes a contact plug; and a contact barrier layer surrounding a side surface of the contact plug. The contact barrier layer includes a protrusion portion protruding toward the channel layer in a horizontal direction.

An integrated circuit device including a plurality of gate stacks disposed on a substrate and including a first gate stack and a second gate stack, a spacer disposed on sidewalls of each of the plurality of gate stacks, a plurality of source / drain areas disposed in an upper portion of the substrate and at sides of the plurality of gate stacks, an active area disposed in the upper portion of the substrate and between adjacent source / drain areas of the plurality of source / drain areas, a channel semiconductor layer disposed between the active area and the second gate stack among the plurality of gate stacks.

A semiconductor device includes several gate stacks over a substrate, a first insulating layer over the gate stacks and a second insulating layer. The gate stacks extend in the first direction and are separated from each other in the second direction. There is an air gap between two adjacent gate stacks. The first insulating layer is disposed over the gate stacks and the air gaps. The first insulating layer exposes an end portion of each of the gate stacks. The second insulating layer is disposed on the first insulating layer and further covers the end portions of the gate stacks that are uncovered by the first insulating layer.

A method of the present disclosure includes forming a fin-shaped structure protruding from a substrate, depositing an isolation feature on sidewalls of the fin-shaped structure, forming a dummy gate stack over a portion of the fin-shaped structure, removing a portion of the dummy gate stack to form a trench exposing the portion of the fin-shaped structure, recessing the portion of the fin-shaped structure to extend the trench downward below a top surface of the isolation feature, depositing a first dielectric layer in the trench, recessing the first dielectric layer, such that a topmost portion of the first dielectric layer is below the top surface of the isolation feature, after the recessing of the first dielectric layer, depositing a second dielectric layer in the trench, the first and second dielectric layers including different material compositions, and replacing an unremoved portion of the dummy gate stack with a metal gate structure.

Described herein are nanoribbon transistors with bilayer cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a first, inner layer adjacent to the gate stack and a second, outer layer adjacent to the source or drain. The inner layer may be a low-k dielectric material, while the outer layer may be a high-k dielectric material.

In an embodiment, a semiconductor device may include a plurality of first nanostructures. The plurality of first nanostructures extend between first source / drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. The plurality of second nanostructures extend between second source / drain regions. The device may furthermore include a first gate stack around the plurality of first nanostructures. The device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may moreover include a vertical interconnect structure extending through the first and second gate stacks. The device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.

A semiconductor device may include a first gate stack, a second gate stack, and a bridge. The first gate stack may include a first channel layer and a plurality of first gate electrodes provided respectively on an upper portion of the first channel layer and a lower portion of the first channel layer. The second gate stack may include a second channel layer and a plurality of second gate electrodes provided respectively on an upper portion of the second channel layer and a lower portion of the second channel layer. The bridge may connect the first gate stack and the second gate stack to each other.

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source / drain region in the first recess and in the second recess, the source / drain region adjacent the gate stack, wherein the source / drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

Integrated circuit structures having direct backside source or drain contacts implemented by silicon germanium etch stops are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the epitaxial source or drain structure over and electrically coupled to the corresponding conductive back contact, the conductive back contact extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

The invention discloses a soft measurement method and device based on a gating stack type auto-encoder, which are used for dynamically controlling the feature extraction capability of the auto-encoder through a gating mechanism from the perspective of optimal prediction estimation quality data, thereby improving the generalization capability and prediction precision of a soft measurement model. The soft measurement method disclosed by the invention is characterized in that a gate control stack type auto-encoder is used for extracting the characteristics of optimal prediction quality data through a gate control mechanism. The invention also discloses a plurality of improved schemes related to the structure of the gated stack type auto-encoder, relates to a newly added residual estimation unit, an improved conversion mode of the encoding unit and the gated unit and the like, and aims to utilize more and more comprehensive information to learn and represent each weight in the gated quantity, so that the soft measurement precision is improved. In addition, the invention further discloses a soft measurement device which comprises a central control module, a data acquisition module, a display module and a storage medium so as to execute the implementation process of the soft measurement method disclosed by the invention.

Provided herein is a semiconductor memory device. The semiconductor memory device includes a gate stacked body enclosing a plurality of channel pillars and a plurality of support structures extending through a section of the gate stacked body near an edge of the gate stacked body.

This document describes an electro-optic photonic memory device comprising a micro-ring resonator, and at least one ferroelectric field effect transistor (FeFET) that is disposed along a partial circumference of a raised ring waveguide of the micro-ring resonator. The FeFET comprises a ferroelectric gate stack and a heterojunction channel layer.

The invention relates to a ferroelectric memory device and a manufacturing method of the ferroelectric memory device. The ferroelectric memory device includes: a dielectric layer including a plurality of ferroelectric regions alternately arranged with a plurality of non-ferroelectric regions in a first direction, the dielectric layer having a tubular structure; a channel layer extending in a first direction on an inner wall of the dielectric layer; and a gate stack structure including a plurality of conductive layers surrounding the plurality of ferroelectric regions of the dielectric layer, and wherein the plurality of conductive layers are spaced apart in the first direction.

A method includes forming a first gate stack including forming a first interfacial layer over a first semiconductor region, wherein the first interfacial layer has a first thickness; and forming a first high-k dielectric layer over the first interfacial layer, wherein the high-k dielectric layer has a second thickness. The method further includes forming a second gate stack including forming a second interfacial layer over a second semiconductor region, wherein the second interfacial layer has a third thickness; and forming a second high-k dielectric layer over the second interfacial layer, wherein the second high-k dielectric layer has a fourth thickness. The thicknesses, dopants, and doping concentrations of the first interfacial layer and the second interfacial layer may be different from each other. The thicknesses, dopants, and doping concentrations of the first high-k dielectric layer and the second high-k dielectric layer may be different from each other.

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive layers, which are alternately stacked in a third direction; a channel plug formed in a cell region, the channel plug penetrating the gate stack structure in the third direction; and at least one support structure formed in a contact region, the channel plug penetrating the gate stack structure in the third direction. The support structure includes a plurality of support structure layers that are sequentially stacked in the third direction, and the plurality of support structure layers are sequentially disposed such that each of the plurality of support structure layers extends in different directions along a plane defined by a first direction and a second direction, the first direction, the second direction, and the third direction being orthogonal to each other.

A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, and a second transistor in the second region. The first transistor includes a first gate structure having an interfacial layer, a first high-k region over the interfacial layer, and a conductive layer over the first high-k region. The second transistor includes a second gate structure having the interfacial layer, a second high-k region over the interfacial layer, and the conductive layer over the second high-k region. The first high-k region is thicker than the second high-k region. The first transistor includes a first channel under the first gate structure. The first channel has first and second semiconductor materials alternately stacked. The first transistor includes a first source / drain (S / D) feature interfacing with both the first and second semiconductor materials in the first channel of the first transistor.