1407 results about "Gate stack" patented technology

Provided are a memory device and a method of manufacturing the same. The memory device includes a peripheral stack including a plurality of circuits, a lower cell array stack including a gate stack including a plurality of gate lines, a gate line contact passing through at least a part of the gate stack and electrically connected to a gate line selected from among the plurality of gate lines, a plurality of through-vias passing through the gate stack and connected to corresponding ones of the plurality of circuits of the peripheral circuit stack, and a wiring structure connecting one of the plurality of through-vias to the gate line contact.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

Integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.

One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source / drain (S / D) feature, a second S / D feature, a channel region interposed between the first and second S / D features, and a gate stack engaging the channel region. The semiconductor device includes a first S / D contact landing on a top surface of the first S / D feature, a second S / D contact landing on a top surface of the second S / D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S / D feature. The dielectric plug spans a width equal to or smaller than a width of the first S / D feature.

A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

The invention provides a method for forming a strained silicon layer and a semiconductor structure, which comprises the steps of covering a semiconductor layer and a gate stack structure to form an etching stop layer, and the semiconductor layer comprises a first device region and a second device region which are separated from each other; forming an auxiliary side wall surrounding the side wall of the gate stack structure on the etching stop layer; forming a patterned hard mask layer; taking the patterned hard mask layer as an etching mask, and performing selective etching on the second device region through a wet etching process to form a sigma trench; and growing a strained silicon layer in the sigma groove. According to the invention, on the premise of not sacrificing the consistency of the critical dimensions of the sigma trench, the etching load effect caused by dry etching in the forming process of the sigma trench is avoided.

Embodiments relate to a transistor having a substrate and a gate formed in or on a surface of the substrate. The gate can include a piezoelectric material. The transistor has a drain and a source formed in or on a surface of the gate. The transistor has a channel formed adjacent to the gate and located between the drain and the source. The channel can include a semiconductor / semi-metallic material. The transistor can have a source contact formed at the source and configured to anchor the semiconductor / semi-metallic channel material to the piezoelectric material. The transistor can have a drain contact formed at the drain and configured to anchor the semiconductor / semi-metallic channel material to the piezoelectric material. The transistor operates on the principle of voltage induced strain transduction via a piezoelectric gate stack leading to a modification of the interface between the metal contact and the semiconducting / semi-metallic channel material.

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

A method includes forming a first source / drain region and a second source / drain region in a semiconductor fin; depositing a first dielectric layer over the first source / drain region and the second source / drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

The invention provides a method for forming an embedded source-drain region. The method comprises the following steps of: covering a semiconductor layer and a gate stack structure to form a sacrificial layer; covering the side wall of the gate stack structure with a sacrificial layer to form an auxiliary side wall; and covering the first device region with a patterned mask layer, etching the second device region by taking the auxiliary side wall and the sacrificial layer as masks to form a sigma trench extending to enter the lower part of the gate stack structure, and simultaneously thinning the sacrificial layer covering the top surface of the gate stack structure of the second device region. According to the forming method, the etching loss of the gate stack structure of the corresponding device region can be reduced, the height difference of the isolation side walls between the PMOS region and the NMOS region is reduced or eliminated, the influence of different etching loads on the subsequent process is avoided, and the process stability is improved on the premise that the process cost and the process complexity are not improved.

A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.

A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

A method includes forming a first complementary Field-Effect Transistor (CFET) and a second CFET. The first CFET includes a first lower transistor, and a first upper transistor overlapping the first lower transistor. The second CFET includes a second lower transistor, and a second upper transistor overlapping the second lower transistor. The method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching a first gate stack between the first upper transistor and the second upper transistor, and etching a second gate stack between the first lower transistor and the second lower transistor. The first opening is filled with a dielectric material to form a dielectric region. The method further includes performing a second etching process to etch a middle portion of the dielectric region and to form a second opening, and filling the second opening with a conductive material to form a through-via.

Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

A semiconductor fabrication method includes: providing a separating wall and a plurality of liners including a first liner and a second liner between a first fin and a second fin having an epitaxial stack and a sacrificial gate stack over channel regions of the second fin; recessing a sacrificial epitaxial layer of the epitaxial stack to form a cavity; recessing the first line thereby expanding the cavity; recessing the second liner thereby expanding the cavity; forming inner spacer material in the first and second cavities; forming source / drain features; and replacing the sacrificial epitaxial layer and the sacrificial gate stack with a metal gate layer; wherein the metal gate layer has a first critical dimension (CD) measured between the inner spacer material, and wherein the first liner after recessing has a second CD measured between the inner spacer material that is approximately equal to the first CD.

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a first region and a second region, where a Flash memory cell gate stack is formed in the first region, a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation.

An integrated circuit structure includes a device layer including a plurality of devices. The plurality of devices includes (i) a plurality of source and drain regions, (ii) a plurality of gate stacks, and (iii) a plurality of gate spacers, each gate spacer separating a corresponding source or drain region from a corresponding gate stack, the gate spacers comprising a first dielectric material. A first source or drain contact is coupled to a frontside of a first source or drain region of the plurality of source or drain regions. A second dielectric material is coupled to a backside of the first source or drain region. A second source or drain contact is coupled to a backside of a second source or drain region of the plurality of source or drain regions. In an example, the first dielectric material and the second dielectric material comprise the same elemental constituents.

A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

Dipole engineering techniques are disclosed herein that may be implemented when fabricating gate stacks, such as a gate stack of a transistor. An exemplary method for forming a gate stack of a transistor includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives aluminum from the p-dipole dopant source layer into the high-k dielectric layer, and after removing the p-dipole dopant source layer, forming at least one electrically conductive gate layer over the high-k dielectric layer. The p-dipole dopant source layer includes an aluminum layer. The p-dipole dopant source layer may further include an aluminum oxide layer and / or an aluminum nitride layer.

A semiconductor device includes: a substrate, a gate stacking structure that includes a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on the substrate, a channel layer that extends in a first direction and into the gate stacking structure, where the channel layer is electrically connected to the substrate, a channel insulating layer that at least partially surrounds the channel layer, and a plurality of dielectric layers that are between the channel insulating layer and the plurality of gate electrodes, extend along a circumference of the channel layer, and are spaced apart from each other in the first direction, where each of the plurality of dielectric layers includes: a ferroelectric pattern that at least partially surrounds the channel insulating layer, and an anti-ferroelectric pattern that at least partially surrounds the ferroelectric pattern.

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for increasing the thickness of at least partial region of a gate side wall along the thickness direction of a semiconductor substrate, so that the region with larger thickness in the gate side wall has a stronger protection effect, a process window is expanded, and the yield is improved. The risk of generating defects in the semiconductor device is reduced, and the yield of the semiconductor device is improved. The semiconductor device includes a semiconductor substrate, and a transistor disposed on the semiconductor substrate. In the transistor, gate side walls are at least arranged on the two sides of a gate stack structure in the length direction. In the thickness direction of the semiconductor substrate, the surfaces of different areas in the side faces, away from the gate stack structure, of the gate side walls are roughly aligned, and the thickness of partial areas of the gate side walls is larger than that of other areas of the gate side walls. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

The embodiment of the invention provides a semiconductor device and a forming method thereof. A method of forming a semiconductor device includes forming a first transistor and a second transistor on a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of the first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on a backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. A backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source / drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source / drain region.

A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

A method for forming a flash memory includes forming an isolation layer to surround a plurality of active regions, forming a plurality of gate stacks across the active regions and the isolation layer, implanting a dopant into an upper portion of the isolation layer to form a doped isolation layer, partially recessing the doped isolation layer, and forming a dielectric material over the plurality of gate stacks, the plurality of active regions, and the doped isolation layer.