692 results about "Gate stack" patented technology

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.

An integrated circuit device including a plurality of gate stacks disposed on a substrate and including a first gate stack and a second gate stack, a spacer disposed on sidewalls of each of the plurality of gate stacks, a plurality of source / drain areas disposed in an upper portion of the substrate and at sides of the plurality of gate stacks, an active area disposed in the upper portion of the substrate and between adjacent source / drain areas of the plurality of source / drain areas, a channel semiconductor layer disposed between the active area and the second gate stack among the plurality of gate stacks.

A semiconductor device includes several gate stacks over a substrate, a first insulating layer over the gate stacks and a second insulating layer. The gate stacks extend in the first direction and are separated from each other in the second direction. There is an air gap between two adjacent gate stacks. The first insulating layer is disposed over the gate stacks and the air gaps. The first insulating layer exposes an end portion of each of the gate stacks. The second insulating layer is disposed on the first insulating layer and further covers the end portions of the gate stacks that are uncovered by the first insulating layer.

A method of the present disclosure includes forming a fin-shaped structure protruding from a substrate, depositing an isolation feature on sidewalls of the fin-shaped structure, forming a dummy gate stack over a portion of the fin-shaped structure, removing a portion of the dummy gate stack to form a trench exposing the portion of the fin-shaped structure, recessing the portion of the fin-shaped structure to extend the trench downward below a top surface of the isolation feature, depositing a first dielectric layer in the trench, recessing the first dielectric layer, such that a topmost portion of the first dielectric layer is below the top surface of the isolation feature, after the recessing of the first dielectric layer, depositing a second dielectric layer in the trench, the first and second dielectric layers including different material compositions, and replacing an unremoved portion of the dummy gate stack with a metal gate structure.

A semiconductor device may include a first gate stack, a second gate stack, and a bridge. The first gate stack may include a first channel layer and a plurality of first gate electrodes provided respectively on an upper portion of the first channel layer and a lower portion of the first channel layer. The second gate stack may include a second channel layer and a plurality of second gate electrodes provided respectively on an upper portion of the second channel layer and a lower portion of the second channel layer. The bridge may connect the first gate stack and the second gate stack to each other.

The invention discloses a soft measurement method and device based on a gating stack type auto-encoder, which are used for dynamically controlling the feature extraction capability of the auto-encoder through a gating mechanism from the perspective of optimal prediction estimation quality data, thereby improving the generalization capability and prediction precision of a soft measurement model. The soft measurement method disclosed by the invention is characterized in that a gate control stack type auto-encoder is used for extracting the characteristics of optimal prediction quality data through a gate control mechanism. The invention also discloses a plurality of improved schemes related to the structure of the gated stack type auto-encoder, relates to a newly added residual estimation unit, an improved conversion mode of the encoding unit and the gated unit and the like, and aims to utilize more and more comprehensive information to learn and represent each weight in the gated quantity, so that the soft measurement precision is improved. In addition, the invention further discloses a soft measurement device which comprises a central control module, a data acquisition module, a display module and a storage medium so as to execute the implementation process of the soft measurement method disclosed by the invention.

This document describes an electro-optic photonic memory device comprising a micro-ring resonator, and at least one ferroelectric field effect transistor (FeFET) that is disposed along a partial circumference of a raised ring waveguide of the micro-ring resonator. The FeFET comprises a ferroelectric gate stack and a heterojunction channel layer.

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive layers, which are alternately stacked in a third direction; a channel plug formed in a cell region, the channel plug penetrating the gate stack structure in the third direction; and at least one support structure formed in a contact region, the channel plug penetrating the gate stack structure in the third direction. The support structure includes a plurality of support structure layers that are sequentially stacked in the third direction, and the plurality of support structure layers are sequentially disposed such that each of the plurality of support structure layers extends in different directions along a plane defined by a first direction and a second direction, the first direction, the second direction, and the third direction being orthogonal to each other.

A method for forming a semiconductor device including forming a stack of alternating channel layers and sacrificial layers over a substrate, forming a gate structure over a portion of the stack to define a channel region, etching the stack in a region adjacent to the gate structure to form a source / drain recess, forming an epitaxial bottom layer along a bottom surface and opposing sidewalls of the source / drain recess, wherein the epitaxial bottom layer contacts the channel layers and a dielectric spacer adjacent to the gate structure. The method also includes depositing an etch stop layer over the epitaxial bottom layer, the etch stop layer having a germanium concentration higher than the epitaxial bottom layer, filling the remaining portion of the source / drain recess with a sacrificial semiconductor layer, removing and replacing the gate structure with a replacement gate stack, selectively removing the sacrificial semiconductor layer to expose the etch stop layer, reacting the etch stop layer to form a silicide layer, and forming a source / drain contact to fill the source / drain recess, wherein the source / drain contact is a bar-shaped plug extending vertically between adjacent channel regions, the source / drain contact is enclosed on a bottom and at least two opposing sides by the silicide layer and the epitaxial bottom layer, and the silicide layer comprises an upper portion in contact with the source / drain contact and a lower portion in contact with the epitaxial bottom layer.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300°° C. to about 500°° C.). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high- k / interfacial interface ±0.5 nm.

The n / p MOS gate stack includes a semiconductor substrate having an nMOS region and a pMOS region, an nMOS stack including a first interface layer, a first high dielectric layer formed on the first interface layer, a first n-metal layer formed on the first high dielectric layer, and a first upper electrode formed on the first n-metal layer, which are formed in the nMOS region, and a pMOS stack including a second interface layer, a second high dielectric layer formed on the second interface layer, a second p-metal layer formed on the second high dielectric layer, a second n-metal layer formed on the second p-metal layer, and a second upper electrode formed on the second n-metal layer, which are formed in the pMOS region. The first high dielectric layer includes a first dipole material, and the second p-metal layer includes a second dipole material.

A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source / drain regions, a first channel region between the first and second source / drain regions, third and fourth source / drain regions, and a second channel region between the third and fourth source / drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source / drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer.

An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and / or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and / or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.

An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. Forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. Forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. Forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. Forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., WCl5) and a hydrogen-comprising precursor (e.g., H2).

Gate stack fabrication techniques are disclosed for capacitance equivalent thickness scaling. An exemplary method for forming a gate stack includes forming an interfacial layer, forming a high-k dielectric layer over the interfacial layer, and forming an electrically conductive gate layer over the high-k dielectric layer. Forming the high-k dielectric layer includes forming a group 4 element-containing dielectric layer (e.g., an HfO2 layer and / or a ZrO2 layer) and forming a rare earth element-containing dielectric layer. In some embodiments, the rare earth element-containing dielectric layer includes yttrium and oxygen, nitrogen, carbon, or a combination thereof. The electrically conductive gate layer is formed over the rare earth element-containing dielectric layer (i.e., the rare earth element-containing dielectric layer is not removed and remains in the gate stack). The rare earth element-containing dielectric layer can be formed before, after, or between forming sublayers of group 4 element-containing dielectric layer.

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

The embodiment of the invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region; forming a high dielectric constant dielectric layer covering the NMOS device region and the PMOS device region above the substrate; forming a gate stack structure above the high dielectric constant dielectric layer, wherein the gate stack structure is located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to reserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region; and after isolation side walls are formed on the side walls of the gate stack structure to define boundaries of sigma trenches, forming the sigma trenches between the isolation side walls of the gate stack structure in the PMOS device region by using an etching process by taking the patterned high-dielectric-constant dielectric layer as a mask. According to the embodiment of the invention, the height difference between the pseudo gate of the PMOS device region and the pseudo gate of the NMOS device region is eliminated.

Gate stacks for stacked device structures, such as stacked transistors, and methods of fabrication thereof are disclosed. An exemplary method includes forming a semiconductor layer stack over a substrate. The semiconductor layer stack includes a first semiconductor layer disposed over a second semiconductor layer. The method further includes forming a first type metal gate layer around the second semiconductor layer. The method further includes, after forming an aluminum-containing isolation layer over the first type metal gate layer, forming a second type metal gate layer around the first semiconductor layer and over the aluminum-containing isolation layer. In some embodiments, the method further includes removing a native metal oxide layer from over the first type metal gate layer before forming the aluminum-containing isolation layer. In some embodiments, removing the native metal oxide layer from over the first type metal gate layer includes performing a chlorine-based gas treatment.

The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.

Threshold voltage (Vt) tuning layers may be sensitive to etching by reactants used to deposit overlying gate material, such as metal nitride. Methods for depositing Vt tuning layers are provided. In some embodiments Vt tuning layers may comprise a Vt tuning material in a neutral matrix. In some embodiments, processes for reducing or eliminating the etching of Vt tuning layers by halide reactants are described. In some embodiments a Vt tuning layer, such as a metal oxide layer, is treated by a nitridation process following deposition and prior to subsequent deposition of a metal nitride capping layer. In some embodiments an etch-protective layer, such as a NbO layer, is deposited over a Vt tuning layer prior to deposition of an overlying metal nitride layer.

Multigate devices having bottom insulation and methods of fabrication thereof are disclosed herein. An exemplary bottom channel insulation structure includes a first insulation layer disposed over a substrate (e.g., an extension thereof) and a second insulation layer disposed over the first insulation layer. The first insulation layer has a first composition and a first length. The second insulation layer has a second composition that is different than the first composition and a second length that is greater than the first length. The first insulation layer is a bottom sacrificial layer of a set of sacrificial layers that are formed and subsequently replaced with a gate stack during fabrication of a multigate device. The bottom sacrificial layer is a dummy sacrificial layer because is not replaced with the gate stack, such that additional insulation is provided between the gate stack and the substrate and / or between source / drains.

The application discloses a transistor and a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors, and aims to solve the problem of poor compatibility between a ring-gate transistor and another transistor with a thicker gate dielectric layer and / or gate, and to reduce the integration difficulty of the two transistors. The manufacturing method of the transistor comprises the following steps: providing a semiconductor substrate; forming an active structure and an isolation layer on the semiconductor substrate; the active structure comprises a source region, a drain region, and at least two channel layers located between the source region and the drain region; the at least two channel layers are in contact with the source region and the drain region respectively; the adjacent two channel layers have a first gap; the isolation layer comprises at least a first isolation layer; the first isolation layer at least fills the first gap; the at least two channel layers and the isolation layer form a first fin structure; and a gate stack structure is formed across the first fin structure.

Provided is a semiconductor device. The semiconductor device includes: a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulation layer, and first and second dielectric isolation layers. The insulation layer is arranged between a source / drain region of the first gate-all-around transistor and a source / drain region of the second gate-all-around transistor. The first dielectric isolation layers and the second dielectric isolation layers are alternately stacked between a channel region of the first gate-all-around transistor and a channel region of the second gate-all-around transistor. A gate stack structure of the first gate-all-around transistor and / or a gate stack structure of the second gate-all-around transistor is located at a periphery of alternately stacked first and second dielectric isolation layers. Film layers located at bottom and top layers in alternately stacked first and second dielectric isolation layers are both first dielectric isolation layer.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

The application provides a method for reducing epitaxial resistance, and provides a semiconductor structure, which at least comprises: a source-drain region and a gate stack of an NMOS region; a source-drain region and a gate stack of a PMOS region; a first protective layer covering the source-drain region and the gate; the first protective layer on the PMOS region is opened by using photoetching and etching to form a first sidewall on the sidewall of the gate stack; a first epitaxial layer containing ion doping and a first cap layer on the first epitaxial layer are formed on the source-drain region of the PMOS region; the source-drain region of the PMOS region is subjected to rapid thermal annealing treatment, so that the doping ions in the first epitaxial layer diffuse to the first epitaxial layer at the bottom of the sidewall; the remaining first protective layer is removed, and then a second protective layer covering the NMOS region and the PMOS region is formed. The application reduces the channel resistance of the PMOS source-drain region to the gate edge, and improves the Idsat (saturation current) and Ioff (off-state current) performance of the device.

The method includes forming a first multilayer stack and a second multilayer stack. The first multilayer stack includes a first plurality of sacrificial layers and a first plurality of semiconductor nanostructures disposed alternately. The second multilayer stack includes a second plurality of sacrificial layers and a second plurality of semiconductor nanostructures disposed alternately. The first plurality of sacrificial layers and the second plurality of sacrificial layers are replaced with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively. The third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes. The method further includes removing the third plurality of sacrificial layers to form a first recess; forming a first gate stack in the first recess; removing the fourth plurality of sacrificial layers to form a second groove; and forming a second gate stack in the second recess. The embodiment of the invention also relates to a method for forming the semiconductor device.

Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is vertically disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. An area of the gate stack projected on a top surface of the substrate is within an area of the bottom dielectric layer projected on the top surface of the substrate.

One method of the present disclosure comprises: forming a stack having channel layers nested with sacrificial layers, structuring the stack to form a fin-shaped structure, forming a dummy-gate stack over a first region of the fin-shaped structure, selectively removing the sacrificial layers to expose the channel layers as channel elements, depositing dielectric dummy layers in spaces between the channel elements, forming a hard mask layer over the dummy-gate stack, structuring the hard mask layer to form an opening directly above the first region of the fin-shaped structure, performing an etching process through the opening to simultaneously remove the channel elements and the dielectric dummy layers in the fin-shaped structure, such that a second trench is formed through the dummy-gate stack, and depositing an insulating structure in the second trench.The insulation structure divides the dummy gate stack into two segments.

An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source / drain region in the first fin and adjacent the first gate spacer. The first source / drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.