1582 results about "Fin field effect transistor" patented technology

A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.

A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation

A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

Field effect transistors (FETs) and methods of fabricating FETs that include a channel layer on sidewalls of a structure on a semiconductor substrate and having at least a portion of the channel layer strained in a direction that the sidewalls of the structure extend from the semiconductor substrate are provided. The transistor may be a FinFET, the structure on the semiconductor substrate that includes a fin structure and the sidewalls may be sidewalls of the fin structure. The channel layer may be a Si epitaxial layer and may be on an inner fin structure that includes alternating layers of SiGe and Si. The channel layer may include strained and unstrained portions. The strained and unstrained portions may be sidewalls of the channel layer.

Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used.

A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.

A method forming a tri-gate fin field effect transistor includes forming an oxide layer over a silicon-on-insulator wafer comprising a silicon layer, and etching the silicon and oxide layers using a rectangular mask to form a mesa. The method further includes etching a portion of the mesa using a second mask to form a fin, forming a gate dielectric layer over the fin, and forming a tri-gate over the fin and the gate dielectric layer.

A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Disclosed are methods, systems and devices, including a device having a fin field-effect transistor with a first terminal, a second terminal, and two gates. In some embodiments, the device includes a local data line connected to the first terminal, at least a portion of a capacitor plate connected to the second terminal, and a global data line connected to the local data line by the capacitor plate.

Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures.