140 results about "Fin field effect transistor" patented technology

Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCl, Cl2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source / drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

The present disclosure relates to a method for processing a fin field effect transistor device, in particular a fork device. The method comprises: providing a substrate (21); forming a trench (25) in the substrate (21), wherein the trench (25) extends along a first direction; filling the trench (25) with a filling material (11); partially recessing the substrate (21) to form a fin structure (27), wherein the fin structure (27) comprises the filled trench (25), a first section of the substrate (21) at a first side of the filled trench (25), and a second section of the substrate (21) at a second side of the filled trench (25); forming a gate structure on and around the fin structure (27).

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source / drain (S / D) region adjacent to the gate structure. The S / D region can include first and second side surfaces separated from each other. The S / D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer / residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes.

Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCI, CI2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source / drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one of sidewalls of each of the semiconductor fins, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor fins, thereby reducing the floating body effect in the memory cell.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

A method of manufacturing an integrated circuit (IC) device includes constructing a first row of fin field-effect transistors (FinFETs) by forming a first total number of one of n-type fins or p-type fins, constructing a second row of FinFETs adjacent to the first row of FinFETs by forming a second total number of the one of the n-type fins or the p-type fins, and constructing a third row of FinFETs adjacent to the second row of FinFETs by forming the first total number of the other of the n-type fins or the p-type fins, wherein the second total number of fins is one greater or one fewer than the first total number of fins.

This application relates to integrating a FinFET and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source and drain structures of the FinFET are respectively formed on the two pressure source portions of the first fin structure. A source metal material, a drain metal material, and a first metal material are formed to be electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

The application provides a preparation method of SDB of fin field effect transistor, which comprises the following steps: forming parallel fins on the semiconductor substrate, the surface of the fins is provided with a hard mask layer, and a first silicon oxide layer covering the fins and the hard mask layer is formed on the semiconductor substrate; grinding the first silicon oxide layer to expose the surface of the hard mask layer; forming a photoresist layer on the surface of the first silicon oxide layer, and patterning the photoresist layer to define an SDB area; taking the patterned photoresist layer as a mask to etch the hard mask layer and the fins, forming an SDB groove, and removing the photoresist layer; depositing a second silicon oxide layer in the hard mask layer, the first silicon oxide layer and the SDB groove; and grinding the second silicon oxide layer to expose the surface of the hard mask layer and the first silicon oxide layer. The first silicon oxide layer is firstly subjected to a chemical mechanical grinding process for planarization, and then an etching process is performed to form the SDB groove, so that the depth difference caused by the load effect can be reduced.

Embodiments of the present disclosure relate to dual-width fin field effect transistors. A dual-width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabricating such a dual-width FinFET includes laterally recessing a strained fin in source and drain regions using a wet chemical etching process, thereby preserving high strain in the fin while simultaneously trimming the width of the fin in the source and drain regions to less than 5 nm. The resulting FinFET features a wider portion of the fin in a channel region under the gate and a narrower portion of the fin in the source and drain regions. The narrower fin has the advantage that it can be more easily doped during epitaxial growth of raised source and drain regions.

Executable processing methods can produce semiconductor structures that can include high-k dielectric materials. A method can include forming a silicon layer over a semiconductor substrate. The semiconductor substrate can include silicon germanium. The method can include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate to form a sacrificial oxide. The method can include removing the sacrificial oxide. The method can include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The method can include forming a high-k dielectric material overlying the oxygen-containing material.

A method of independently forming source / drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source / drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source / drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source / drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source / drain region, the second inner spacer layer comprising a second material different from the first material.

The application provides a fin field effect transistor and a preparation method thereof. A gate dielectric layer of the fin field effect transistor comprises an aluminum oxide layer and a hafnium oxynitride layer covering the aluminum oxide layer. The aluminum oxide layer can form a good interface with a semiconductor substrate, thereby providing a good interface basis for the hafnium oxynitride layer, preventing crystalline epitaxy of the hafnium oxynitride layer, and reducing interface state density between the gate dielectric layer and the semiconductor substrate. The aluminum oxide layer and the hafnium oxynitride layer can cooperate to reduce loss in a carrier movement process, adjust a Fermi level of the gate dielectric layer, thereby reducing leakage current between the gate dielectric layer and the semiconductor substrate, and improving reliability of the device.

The present disclosure provides a semiconductor device, a preparation method of the semiconductor device, and an electronic device. The semiconductor device comprises a gate and a semiconductor fin extending along a first direction, the semiconductor fin comprising a functional part having a channel region, the gate being configured to control on-off of the channel region. The functional part comprises a silicon material, and the abundance of Si-28 isotope in the silicon material of the functional part is greater than or equal to 95.01%. The semiconductor device can improve the heat conduction performance and electronic performance of the channel region of the fin field effect transistor.

Some implementation described herein include a semiconductor device including a transistor structure and methods of manufacturing. The transistor structure, a tunneling fin field effect transistor structure, includes different combinations of doped semiconductor regions that form a source region, a drain region, and a channel region of the transistor structure. The different combinations of doped semiconductor regions include different types of dopants, different concentrations of dopants, and / or dopant gradients that change differences in band gap energy levels across one or more junctions of the transistor structure to increase a threshold voltage and / or decrease a leakage in the transistor structure.

A semiconductor device includes a stacked FinFET transistor in a first region and a gate-all-around (GAA) transistor in a second region. The stacked FinFET transistor includes a stack of first and second semiconductor layers disposed between two first epitaxial features. The first and second semiconductors are alternately stacked. The stacked FinFET transistor also includes a first gate dielectric layer disposed over top and sidewalls of the stack, and a first gate electrode layer disposed over the first gate dielectric layer. The GAA transistor includes two second epitaxial features, a stack of third semiconductor layers disposed between the two second epitaxial features, the third semiconductor layers and the first semiconductor layers including a same semiconductor material, a second gate dielectric layer wrapping around at least one of the third semiconductor layers, and a second gate electrode over the second gate dielectric layer.

Method for the formation of Fin field-effect transistors, which includes: Etching a semiconductor substrate (20) to form a first trench (26) and a second trench (26), wherein a residual section of the semiconductor substrate between the first trench and the second trench is left as a semiconductor region, and wherein the semiconductor region is a semiconductor base (130) and comprising semiconductor strips (132) arranged above and connected to the semiconductor base; Forming a doped dielectric layer(36) on side walls of the semiconductor region and over a top surface of the semiconductor region, wherein the doped dielectric layer contains a dopant; Filling a dielectric material (50) into the first and second trenches and above the doped dielectric layer (36) to form insulating regions (54), wherein after filling the dielectric material (50) into the first and second trenches, the dielectric material is arranged in the first trench (26) and the second trench (26) above the doped dielectric layer (36); and Performing a tempering process to diffuse the dopant in the doped dielectric layer (36) into the totality of the semiconductor strips (132) and a surface layer of the semiconductor base (130), thereby forming a diffused semiconductor region (52).

Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

This application provides a finned field-effect transistor device and its fabrication method, relating to the field of semiconductor technology. The finned field-effect transistor device includes: a first substrate, a device layer, and a capping layer stacked sequentially; the device layer includes a plurality of field-effect transistors; the field-effect transistors include: a fin and a source, a first spacer layer, a gate, a second spacer layer, and a drain sequentially disposed along the extension direction of the fin, the source and drain being respectively disposed at both ends of the fin and respectively connected to the fin; the sides of the fin, source, gate, and drain covered by the capping layer are flush with each other.

A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

Some implementations described herein provide techniques and apparatuses for forming insulator layers in or on a semiconductor substrate prior to forming epitaxial layers within source / drain regions of a fin field-effect transistor. The epitaxial layers may be formed over the insulator layers to reduce electron tunneling between the source / drain regions of the fin field-effect transistor. In this way, a likelihood of leakage into the semiconductor substrate and / or between the source / drain regions of the fin field-effect transistor is reduced.

The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source / drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source / drain region around the gate structure; forming an opening in the ILD layer to expose the source / drain region; forming a silicide region and a barrier layer successively in the openings over the source / drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.