269 results about "Fin field effect transistor" patented technology

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.

FinFET multi-diode thyristor switches for protecting high data rate communication system interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and / or reduces total on-state resistance.

The invention provides a method for operating at least one CMOS transistor at a low temperature, the at least one CMOS transistor produced using at least one process selected from a planar bulk CMOS process, a fin field effect transistor (FinFET) process, and a combination thereof, the method comprising setting the at least one CMOS transistor in a low-temperature drive mode comprising determining for the at least one CMOS transistor its threshold voltage as a function of its operating temperature range and for an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature in the operating temperature range for the at least one CMOS transistor, in particular a desired operating temperature below 218K, more in particular at a cryogenic temperature, determining a resulting forward bulk biasing (FBB) voltage, and applying the resulting forward bulk biasing voltage to the at least one CMOS transistor.

The present disclosure relates to semiconductor structures and, more particularly, to asymmetric junctionless fin field effect transistor (FINFET) structures and methods of manufacture. The structure includes: a nanowire fin comprising a first width adjacent to a source region and a second width adjacent to a drain region, the first width and the second width being different dimensions; and a gate structure over the nanowire fin, the gate structure spanning over the first width and the second width and being between the source region and the drain region.

A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer. The FinFET transistor comprising: a fin semiconductor structure comprising an elongate protruding core portion, the fin semiconductor structure being arranged on the lattice-mismatched semiconductor epilayer, a first and a second nanostructured electrode radially enclosing respectively a source end and a drain end of the protruding core portion, and a nanostructured gate electrode radially enclosing a central portion of the protruding core portion, the central portion being a portion of the protruding core portion between the source end and the drain end.

Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.

Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCl, Cl2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source / drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

A semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source / drain region in the first recess and in the second recess, the source / drain region adjacent the gate stack, wherein the source / drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and / or between the gate oxide layer and the at least one fin structure.

A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the recessed portion of the drift layer and along sides of the fin-shaped portion of the drift layer. A body layer and a source layer formed over a portion of the doped-well layer over the recessed portion of the drift layer. An insulating layer over the doped-well layer. A gate electrode over the insulating layer.

A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.

A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source / drain recess in a source / drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source / drain tip. A depth of the source / drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source / drain recess to the target depth. The source / drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source / drain recess is spaced a distance from a gate footing that can minimize DIBL. The source / drain recess is filled with an epitaxial semiconductor material.

The present disclosure relates to a method for processing a fin field effect transistor device, in particular a fork device. The method comprises: providing a substrate (21); forming a trench (25) in the substrate (21), wherein the trench (25) extends along a first direction; filling the trench (25) with a filling material (11); partially recessing the substrate (21) to form a fin structure (27), wherein the fin structure (27) comprises the filled trench (25), a first section of the substrate (21) at a first side of the filled trench (25), and a second section of the substrate (21) at a second side of the filled trench (25); forming a gate structure on and around the fin structure (27).

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Embodiments of the present invention disclose forming an epitaxial structure in a fin field-effect transistor. In one embodiment, a method of forming source / drain members in a FinFET device includes: providing a fin formed over a substrate and a gate structure formed over the fin; forming a groove adjacent to the gate structure in the fin; forming a first epitaxial layer in the groove; forming a second epitaxial layer over the first epitaxial layer; and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, and one or both of the first epitaxial layer and the third epitaxial layer contain a second element different from the first element. One or both of the first epitaxial layer and the third epitaxial layer may be formed by a plasma deposition process.

Embodiments provide bipolar junction transistors (BJTs) which are formed from GAA or FinFET transistors and methods of forming the BJTs. The BJTs include dielectric isolation structures formed between gates of the GAA or FinFET transistors. The dielectric isolation structures reduce spacing between transistors of neighboring terminals of the BJTs. The dielectric isolation structures allow the BJTs to use the nominal gate spacing (Lg) as logic device, thereby, compatible with the GAA or FinFET processes.

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and / or prevent polishing issues, etch back issues, and / or other types of semiconductor processing issues.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source / drain (S / D) region adjacent to the gate structure. The S / D region can include first and second side surfaces separated from each other. The S / D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer / residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes.

A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCI, CI2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source / drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

An integrated circuit (IC) includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The IC further includes n-type source / drain (S / D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S / D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S / D contacts physically contacting each of the p-type S / D epitaxial features and the second portion of each of the first and the second hybrid fins.

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one of sidewalls of each of the semiconductor fins, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor fins, thereby reducing the floating body effect in the memory cell.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

A method of manufacturing an integrated circuit (IC) device includes constructing a first row of fin field-effect transistors (FinFETs) by forming a first total number of one of n-type fins or p-type fins, constructing a second row of FinFETs adjacent to the first row of FinFETs by forming a second total number of the one of the n-type fins or the p-type fins, and constructing a third row of FinFETs adjacent to the second row of FinFETs by forming the first total number of the other of the n-type fins or the p-type fins, wherein the second total number of fins is one greater or one fewer than the first total number of fins.