67 results about "Fin field effect transistor" patented technology

Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCl, Cl2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source / drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

The present disclosure relates to a method for processing a fin field effect transistor device, in particular a fork device. The method comprises: providing a substrate (21); forming a trench (25) in the substrate (21), wherein the trench (25) extends along a first direction; filling the trench (25) with a filling material (11); partially recessing the substrate (21) to form a fin structure (27), wherein the fin structure (27) comprises the filled trench (25), a first section of the substrate (21) at a first side of the filled trench (25), and a second section of the substrate (21) at a second side of the filled trench (25); forming a gate structure on and around the fin structure (27).

Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCI, CI2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source / drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one of sidewalls of each of the semiconductor fins, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor fins, thereby reducing the floating body effect in the memory cell.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

This application relates to integrating a FinFET and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source and drain structures of the FinFET are respectively formed on the two pressure source portions of the first fin structure. A source metal material, a drain metal material, and a first metal material are formed to be electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

The application provides a preparation method of SDB of fin field effect transistor, which comprises the following steps: forming parallel fins on the semiconductor substrate, the surface of the fins is provided with a hard mask layer, and a first silicon oxide layer covering the fins and the hard mask layer is formed on the semiconductor substrate; grinding the first silicon oxide layer to expose the surface of the hard mask layer; forming a photoresist layer on the surface of the first silicon oxide layer, and patterning the photoresist layer to define an SDB area; taking the patterned photoresist layer as a mask to etch the hard mask layer and the fins, forming an SDB groove, and removing the photoresist layer; depositing a second silicon oxide layer in the hard mask layer, the first silicon oxide layer and the SDB groove; and grinding the second silicon oxide layer to expose the surface of the hard mask layer and the first silicon oxide layer. The first silicon oxide layer is firstly subjected to a chemical mechanical grinding process for planarization, and then an etching process is performed to form the SDB groove, so that the depth difference caused by the load effect can be reduced.

Embodiments of the present disclosure relate to dual-width fin field effect transistors. A dual-width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabricating such a dual-width FinFET includes laterally recessing a strained fin in source and drain regions using a wet chemical etching process, thereby preserving high strain in the fin while simultaneously trimming the width of the fin in the source and drain regions to less than 5 nm. The resulting FinFET features a wider portion of the fin in a channel region under the gate and a narrower portion of the fin in the source and drain regions. The narrower fin has the advantage that it can be more easily doped during epitaxial growth of raised source and drain regions.

Executable processing methods can produce semiconductor structures that can include high-k dielectric materials. A method can include forming a silicon layer over a semiconductor substrate. The semiconductor substrate can include silicon germanium. The method can include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate to form a sacrificial oxide. The method can include removing the sacrificial oxide. The method can include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The method can include forming a high-k dielectric material overlying the oxygen-containing material.

A method of independently forming source / drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source / drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source / drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source / drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source / drain region, the second inner spacer layer comprising a second material different from the first material.

The present disclosure provides a semiconductor device, a preparation method of the semiconductor device, and an electronic device. The semiconductor device comprises a gate and a semiconductor fin extending along a first direction, the semiconductor fin comprising a functional part having a channel region, the gate being configured to control on-off of the channel region. The functional part comprises a silicon material, and the abundance of Si-28 isotope in the silicon material of the functional part is greater than or equal to 95.01%. The semiconductor device can improve the heat conduction performance and electronic performance of the channel region of the fin field effect transistor.

Method for the formation of Fin field-effect transistors, which includes: Etching a semiconductor substrate (20) to form a first trench (26) and a second trench (26), wherein a residual section of the semiconductor substrate between the first trench and the second trench is left as a semiconductor region, and wherein the semiconductor region is a semiconductor base (130) and comprising semiconductor strips (132) arranged above and connected to the semiconductor base; Forming a doped dielectric layer(36) on side walls of the semiconductor region and over a top surface of the semiconductor region, wherein the doped dielectric layer contains a dopant; Filling a dielectric material (50) into the first and second trenches and above the doped dielectric layer (36) to form insulating regions (54), wherein after filling the dielectric material (50) into the first and second trenches, the dielectric material is arranged in the first trench (26) and the second trench (26) above the doped dielectric layer (36); and Performing a tempering process to diffuse the dopant in the doped dielectric layer (36) into the totality of the semiconductor strips (132) and a surface layer of the semiconductor base (130), thereby forming a diffused semiconductor region (52).

This application provides a finned field-effect transistor device and its fabrication method, relating to the field of semiconductor technology. The finned field-effect transistor device includes: a first substrate, a device layer, and a capping layer stacked sequentially; the device layer includes a plurality of field-effect transistors; the field-effect transistors include: a fin and a source, a first spacer layer, a gate, a second spacer layer, and a drain sequentially disposed along the extension direction of the fin, the source and drain being respectively disposed at both ends of the fin and respectively connected to the fin; the sides of the fin, source, gate, and drain covered by the capping layer are flush with each other.

The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source / drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source / drain region around the gate structure; forming an opening in the ILD layer to expose the source / drain region; forming a silicide region and a barrier layer successively in the openings over the source / drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

The invention relates to a three-dimensional semiconductor device, a preparation method thereof and a thermal management scheme. The device includes a three-dimensional active structure and a functional thermal management body integrated with and thermally coupled to the structure. At least one thermal physical attribute of the thermal management body is configured to be in non-uniform continuous distribution in space so as to realize collaborative optimization of thermal and electrical properties of the three-dimensional active structure. The preparation method comprises the following steps: providing a three-dimensional active structure; based on the heat source, electric field or stress distribution of the structure, determining a target distribution function of thermophysical attributes through reverse design; and a material synthesis or structure assembly process is regulated and controlled according to the function, so that a thermal management body with corresponding non-uniform distribution attributes is formed and integration is completed. Through integrated heat management with designable attributes, the heat dissipation efficiency and the electrical performance of the device are effectively improved, meanwhile, the process is simplified, materials are saved, and the comprehensive cost is remarkably reduced. The method is suitable for surrounding gate transistors, fin field effect transistors, three-dimensional stacked memories and other chips.

A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of fins, each of the fins having a fin length and a fin width measured laterally with respect to the fin length and including a first fin tip disposed at a first end of the fin; a second fin tip disposed at a second end of the fin opposing the first end; a bridging structure connecting the first fin tip to an adjacent fin; a central region disposed between the first fin tip and the second fin tip and characterized by an electrical conductivity; and a source contact electrically coupled to the central region. The FinFET device also includes a gate region surrounding the fins.

A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate is composed of a first sub-metal gate cut line filled with a first stressor material, and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

The application discloses a recess etching method in a fin field effect transistor, comprising the following steps: providing a substrate, the surface of the substrate is provided with a plurality of gates and fin structures between the gates; etching the fin structures between the adjacent gates to form an initial recess, the inner wall surface of the initial recess is attached with by-products generated in the etching process; removing the by-products on the inner wall surface of the initial recess; etching the initial recess again to form a recess with a smooth inner wall surface. The application can reduce the roughness and defect state density of the recess surface in the recess etching of the fin structure of the Fin-FET, and form a recess with a smooth surface.

A semiconductor device includes a substrate, at least one finFET on a first area of the substrate, the at least one finFET including a first gate structure and first source / drain regions on opposite sides of the first gate structure, and a planar FET on a second area of the substrate, the planar FET including a second gate structure and second source / drain regions on opposite sides of the second gate structure, wherein the first gate structure includes a first gate insulating layer, a first metal gate, and first spacers, the second gate structure includes a second gate insulating layer, a second metal gate, and second spacers, wherein the upper surfaces of the fin and the substrate are at a same height, and wherein the second gate insulating layer includes a first oxide layer in a recess of the substrate and a second oxide layer on the first oxide layer.

A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate extending through the STI region. The FinFET further includes a second fin structure on the substrate extending through the STI region. The FinFET also includes a metal gate on the STI region, the first fin structure, and the second fin structure. The metal gate is comprised of a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

Embodiments of the present disclosure advantageously provide semiconductor components, particularly fin field effect transistors (FinFETs), and methods of making such components with improved effective capacitance (Ceff). The FinFET includes a gate structure in which an air gap is provided by recessing a high dielectric constant material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high dielectric constant dielectric layer and improving the effective capacitance (Ceff) of the component.

Procedure with the following steps: Creating a first semiconductor fin (24') that protrudes from a substrate (20); Manufacturing a gate stack (80) over the first semiconductor fin (24'), wherein manufacturing the gate stack comprises the following: Deposition of a dielectric gate layer (54, 56) over the first semiconductor fin (24'), Deposition of a first seed layer (72) over the dielectric gate layer, Deposition of a second seed layer (74) over the first seed layer (72), wherein the second seed layer has a different structure than the first seed layer, and Deposition of a conductive layer (76) over the second seed layer (74), wherein the first seed layer (72), the second seed layer and the conductive layer have the same conductive material, wherein the first seed layer (72) is the same material as the second seed layer (74); and Creating source and drain areas (42) adjacent to the gate stack.

The application provides a semiconductor device manufacturing method and a semiconductor device. The manufacturing method includes the following steps: processing a fin structure on a substrate layer; processing an oxide layer surrounding the fin structure outside the fin structure; making the fin structure protrude to the surface of the oxide layer; processing a dummy polysilicon gate between the fin structures on the surface of the oxide layer; forming an interlayer dielectric layer between adjacent dummy polysilicon gates; removing the dummy polysilicon gate to expose the oxide layer; injecting ion dopants into the oxide layer to etch the oxide layer downward to a certain depth; and depositing a metal gate on the surface of the etched oxide layer. The manufacturing method can be used to manufacture semiconductor devices, especially fin field effect transistors.

The invention provides a fin field effect transistor and a forming method thereof. A semiconductor structure is formed; the semiconductor structure comprises a plurality of fins located on one side of the substrate, a protection layer and a photoresist layer; the plurality of fins comprise dummy fins, and the photoresist layer is provided with a groove; measuring the groove to obtain a first size and a center offset; determining a first correction amount and a second correction amount according to the first size, the center offset and a second size of the target area; the first correction amount and the second correction amount are correction amounts in the positive direction and the negative direction respectively in the arrangement direction; and according to the first correction amount and the second correction amount, performing ion beam etching processing on the groove to obtain a target groove. Therefore, the position deviation of the groove relative to the target area is pre-determined, the groove is expanded by utilizing ion beam etching, and the size and the position of the groove are corrected to enable the groove to be positioned right above the pseudo fin, so that the pseudo fin to be removed can be accurately etched, damage to other fins is avoided, and the performance of a device is improved.

One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing titanium nitride (TiN) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as finFETs, GAAs, and the like, without creating a seam. The methods include selective deposition processes using blocking compounds in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.

A fin field-effect transistor device with hybrid conduction mechanism, including a fin field-effect transistor, a second source region, and a second drain region; the fin field-effect transistor includes a substrate, a fin channel region, a first source region, and a first drain region; the height of the second source region is not lower than the height of the substrate between the first source region and the first drain region; the first source region the first drain region and the second drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, the second source region is doped with second ions. This scheme can realize hybrid conduction of fin channel diffusion drift current and bottom channel band-to-band tunneling current, thus obtaining better ultra-steep switching characteristics.