428 results about "Logic gate" patented technology

The invention belongs to the field of quantum computing, and particularly relates to a distortion correction optimization method and device for a quantum measurement and control link, and the method comprises the steps: applying a frequency control signal for loading a target pre-distortion waveform on a to-be-corrected quantum measurement and control Z link; setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit; obtaining the fidelity of the quantum state output by the selected quantum bit; in response to the fact that the fidelity does not reach the preset standard, updating the pre-distortion waveform, and returning to execute a frequency control signal for applying and loading the target pre-distortion waveform signal on the quantum measurement and control Z link to be corrected; and setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit until the fidelity reaches a preset standard. According to the invention, distortion correction can be rapidly and effectively carried out.

The invention discloses an OEO amplifier with a high-speed hard switching function and an optical transmission system, and relates to the technical field of optical amplifiers, the OEO amplifier comprises three magneto-optical switches, an optical splitter group, a photoelectric detector group, a real-time comparison circuit, a logic gate control circuit and a driving circuit; the photoelectric detector group collects optical signal power to generate an electric signal; the real-time comparison circuit performs voltage threshold judgment on the electric signal; the logic gate control circuit is connected with the output end of the real-time comparison circuit so as to synchronously control the switching states of the three magneto-optical switches according to a voltage threshold judgment result; the driving circuit is used for driving the magneto-optical switch to synchronously execute a switching action; when the OEO amplifier detects that optical signals in any direction are interrupted, all the magneto-optical switches finish synchronous switching within 100 microseconds, and the end-to-end optical signal switching time difference is smaller than 2 picoseconds. The method is suitable for a single-fiber bidirectional optical communication environment requiring high frequency, high precision and high stability.

The invention discloses a variable component sub-line compilation optimization method and a related device, and belongs to the technical field of quantum computing, and the method comprises the following steps: if a variable component sub-line is not compiled for the first time and a mapping relation is unchanged, calling quantum hardware resources to execute the compiled variable component sub-line so as to update logic gate parameters in the variable component sub-line, the mapping relation is used for representing the corresponding relation between the logic bits in the variable component sub-lines and the physical bits in the quantum hardware resources. According to the method, the mapping relation result is stored during the first compiling, and a mechanism for judging whether the compiling is the first compiling is introduced into the compiling process, so that the tedious remapping operation is avoided, the time and computing resources required by the compiling process are remarkably reduced, the parameter updating can be quickly responded, and the execution efficiency of the variable component sub-line is improved.

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

The invention relates to the technical field of data processing systems, and discloses a conference information intelligent data processing system based on multi-modal data fusion, and the system comprises a transaction template generation unit which calls a model from a preset rule base to generate a structured data container with an attribute field; the dual-channel feature extraction unit is used for distributing the voice to service data and a control instruction channel, extracting the service data to an independent cache region and monitoring a control keyword; the state control unit is used for unlocking the container only when the confirmation instruction is received, verifying data and writing a field to generate a transaction submission instruction; according to the system and the method, physical isolation of data flow and control flow is realized through a dual-channel architecture, a control instruction is used as a unique logic gating, non-decisive negotiation noise is filtered from the source, and atomicity and compliance of conversion from unstructured conference data to structured management transactions are ensured.

The invention discloses a floating-point number format conversion device and method, a storage medium and a program product, and relates to the technical field of floating-point number format conversion. The device comprises a preprocessing unit and a conversion mapping unit; the preprocessing unit is used for receiving input data in a first floating point format and performing bit width compression processing on at least part of digits influencing rounding operation in the input data to generate a corresponding index value, and the bit width of the index value is smaller than the mantissa bit width of the input data; the conversion mapping unit is coupled to the preprocessing unit, a plurality of mapping relations between index value ranges and numerical value representations in a second floating point format are stored in the conversion mapping unit, and the conversion mapping unit is used for searching the corresponding numerical value representations in the second floating point format according to the index values to serve as output data. The invention aims to reduce the number of logic gates and the circuit complexity required by floating-point number format conversion, so that the area of a related chip is reduced, the power consumption is reduced, and the operation delay is shortened.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

A deep neural network circuit with multiple layers formed of multi-terminal logic gates is provided. In one aspect, the neural network circuit includes a plurality of logic gates arranged into a plurality of layers and a plurality of logical connectors arranged between each pair of adjacent layers. Each of the logical connectors connects the output of a first logic gate to the input of a second logic gate and each of the logical connectors has one of a plurality of different logical connector states. The neural network circuit is configured to be trained to implement a function by finding a set of the logical connector states for the logical connectors such that the neural network circuit implements the function.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

A multiply-accumulate unit comprises a first input configured to receive a first operand encoded using a two-bit encoding scheme in which a ternary value is represented by two bits, wherein identical bits indicate a non-computable value and different bits indicate a computable value. The unit further comprises a second input for receiving a second operand, a zero detection circuit with a logic gate that compares the two bits and generates a skip signal when they are identical, an arithmetic circuit for performing accumulation based on both operands, an accumulator register for storing the result, and a gating circuit that selectively enables writing to the accumulator register based on the skip signal, preventing writing when the first operand is non-computable.

The application discloses a kind of based on ensemble rare earth ions double quantum bit controlled gate construction method, it is related to quantum control technical field, it includes to double quantum bit frequency site selection, and respectively as control bit, target bit;Utilize the blocking effect generated by the dipole-dipole interaction between double quantum bits to construct controlled gate, including: to control bit apply light pulse driving control bit is from ground state transition to excited state;To target bit apply single quantum gate to drive its evolution, and apply compensation pulse;To control bit apply light pulse driving control bit from excited state de-excitation to ground state.The application utilizes the interaction of the light pulse and quantum system medium that can be optimized to produce arbitrary geometric quantum logic gate on target quantum bit, and simultaneously by using the blocking effect caused by dipole-dipole interaction, the evolution of target bit quantum bit can be constrained by control bit.

This application discloses a floating-point number format conversion apparatus and method, storage medium, and program product, relating to the field of floating-point number format conversion technology. The apparatus includes a preprocessing unit and a conversion mapping unit. The preprocessing unit receives input data in a first floating-point format and performs bit-width compression processing on at least a portion of the bits in the input data that affect rounding operations to generate corresponding index values, wherein the bit width of the index values ​​is smaller than the mantissa bit width of the input data. The conversion mapping unit is coupled to the preprocessing unit and stores multiple mapping relationships between index value ranges and numerical representations in a second floating-point format, used to look up the corresponding numerical representation in the second floating-point format as output data based on the index values. This application aims to reduce the number of logic gates and circuit complexity required for floating-point number format conversion, thereby reducing the chip area, power consumption, and operation latency.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

The application discloses an osteoporosis risk grading prediction method based on clinical prior logic gating, acquires multi-modal clinical data of a patient to obtain a standardized feature vector group, constructs and trains an osteoporosis risk grading prediction neural network model, including a double-flow feature coding module, a logic gating fusion module and a cascaded classification prediction module, inputs the standardized feature vector group after splicing processing to the trained neural network model, and outputs an osteoporosis risk grading prediction result. The application converts the diagnosis logic in the clinical guideline into an attention gating mechanism in the neural network by designing a double-flow architecture, and combines a screening-grading cascaded strategy, so that the existing structured data (demography, test single, medical history) in the hospital information system can be directly used to realize low-cost, high-precision and clinically interpretable osteoporosis risk grading without additional image examination.

The present application provides an uncooled infrared detector readout circuit and an uncooled infrared detector. The readout circuit comprises an uncooled infrared focal plane array (10), a pixel gating module (20), a logic control module (70), and a readout circuit module (40). The uncooled infrared focal plane array (10) comprises a plurality of infrared sensitive pixels (101) arranged in an array; the pixel gating module (20) is connected to the infrared sensitive pixels (101); the logic control module (70) and the pixel gating module (20) are connected to some infrared sensitive pixels by means of a logic gate circuit (80), and the logic control module (70) is configured to be capable of controlling none of the infrared sensitive pixels connected to the logic control module (70) to be gated; and the readout circuit module (40) is capable of performing signal readout on the gated infrared sensitive pixels.

The invention relates to a method and a device for preventing undesired triggering of short circuit or overcurrent protection. Methods, apparatus, systems, and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over-current protection. An example apparatus (500) includes an output terminal (108); a voltage detection device (506) coupled to the voltage detection input terminal and the output terminal (108) and comprising a voltage detection output (520) coupled to the first input terminal of the logic gate (508); a pulse expander (510) coupled between the logic gate (508) output (526) and the select node (528); a multiplexer (522) coupled to the select node (528) and configured to be coupled to the first protection circuit (512), the second protection circuit (514), and the driver (540); and a switch (530) coupled between the input terminal (524) and the output terminal (108) and including a switch gate terminal coupled to the driver (540).

An apparatus includes a first D flip-flop including a first data output, a first negative edge-triggered clock input, and a first reset input, and a second D flip-flop including a second data output, a second negative edge-triggered clock input, and a second reset input. The apparatus includes a logic gate having an output and first and second inputs, the first input of the logic gate coupled to the first data output, and the second input of the logic gate coupled to the second data output, in which the output of the logic gate is configured to be a first clock output of the apparatus. A delay circuit of the apparatus includes an output and input, the output of the delay circuit coupled to the first and second reset inputs, and the input of the delay circuit coupled to the output of the logic gate.

The invention relates to an implementation method for applying linear subcomponents of a ZUC algorithm to multiple scenes. The method comprises the following steps: constructing a linear transformation matrix expression from an input bit sequence to an output bit sequence of a linear subcomponent according to the definition of the linear subcomponent in the ZUC algorithm; and carrying out structure division on the linear transformation matrix expression, and decomposing the original large-scale matrix operation into at least two independent small-scale matrix operations. And according to each small-scale matrix design, a logic gate level implementation scheme based on in-situ XOR operation is designed, and a bit operation sequence is generated. And mapping the logic gate-level implementation scheme into a plurality of physical circuit modules with a hierarchical connection relationship according to the data dependency relationship among the bit operation sequences, so that all the physical circuit modules jointly form a component structure suitable for multiple scenes. By adopting the method, the reliability and applicability of the communication system or equipment for executing the ZUC algorithm can be enhanced.

Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson transmission lines (JTLs) or logic gates having strengthened or weakened bias taps as compared to bias taps of JTLs or logic gates in the operational RQL circuitry. Sampler JTLs or logic gates with weakened bias taps to AC clock resonators can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. Staging relative strengths of the bias taps of the samplers in an ensemble of samplers allows for outputs of wrapper circuitry to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range.

The application relates to a single photon avalanche diode front-end circuit for multi-mode detection, which integrates a quenching, delay control and self-resetting module composed of basic MOS tubes, inverters and logic gates. Three control signals are output by a controller to configure modes: in a synchronous gating mode, the related MOS tubes are sequentially controlled to be turned on and turned off in a gating mode; in an asynchronous free-running mode, the related control levels are fixed, and the reset delay is linearly controlled by adjusting the third control signal. The application realizes dual-mode detection by using a single circuit structure, shares the core quenching path, has the advantages of small area, low power consumption and wide adjustable range of dead time, and is suitable for large-scale SPAD array integration.

The invention discloses a quantum circuit optimization method and device and a medium, and the method comprises the steps: firstly determining a quantum logic gate in a to-be-optimized quantum circuit, and then converting the quantum logic gate into a target quantum logic gate which can be executed by an ion trap quantum chip, according to the method, a target quantum circuit which is equivalent to a to-be-optimized quantum circuit and comprises a target quantum logic gate is generated, the target quantum logic gate comprises an MS gate and an RPhi gate, a to-be-optimized common quantum circuit is compiled into the target quantum circuit which can be directly executed by an ion trap quantum chip by utilizing a quantum logic gate conversion and combination rule, and the target quantum logic gate is converted into the target quantum circuit which can be directly executed by the ion trap quantum chip. The number of quantum logic gates in the target quantum circuit is reduced, the depth of the optimized target quantum circuit is smaller, and a basis is provided for calculation simulation of a common quantum circuit on an ion trap quantum chip.

A circuit may comprise a first multiplexer, a second multiplexer, a combination of logic gates, a third multiplexer, a first low-pas filter, and a second low-pass filter. The first multiplexer can be configured to receive and select a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. Respective phases of the first to fourth clock signals are related to each other. The second multiplexer can be configured to receive and select the first to fourth clock signals. The combination of logic gates may comprise a first logic gate and a second logic gate. The combination of logic gates can be coupled to the second multiplexer and can be configured to receive the second plurality of the first to fourth clock signals. The third multiplexer can be configured to receive and select the first to fourth outputs.

The invention discloses a source-type and drain-type switching value protection circuit and system. The source-type and drain-type switching value protection circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube Q4, a resistor R1 and a PMOS tube Q2 which are connected in series, a resistor R13 and a resistor R12; a voltage drop control unit; the output end of the comparator U10B is connected between the resistor R2 and the resistor R9 through the resistor R3, and the grid electrode of the PMOS tube Q4 is connected between the resistor R2 and the resistor R9; the grid electrode of the PMOS transistor Q2 is connected with the collector electrode of the NPN type triode Q6, and the base electrode of the triode Q6 is connected with the output end of the controllable logic gate U1A; the input end of the controllable logic gate U1A is used for receiving a first voltage signal, and the enable end of the controllable logic gate U1A is used for receiving an enable signal output by the output end of the comparator U8B; wherein the positive electrode of the comparator U8B is connected with the reference voltage Vref1, and the other end of the comparator U8B is connected between the resistor R13 and the resistor R12, so that the reliability of the switching value output channel is improved.

The application relates to an integrated circuit analysis method and device, computer equipment and a storage medium. The method comprises the following steps: acquiring a gate-level netlist corresponding to a digital integrated circuit included in a device to be measured, the gate-level netlist being used for describing a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path; acquiring path information of each path according to the gate-level netlist; calculating a delay increment of each path according to the path information and a preset device degradation model; calculating a failure time of each path according to the delay increment and a failure boundary condition, and taking a path corresponding to a minimum failure time as a critical failure path of the digital integrated circuit. Through the method, a critical failure path causing reliability degradation in an integrated circuit can be analyzed based on circuit load and timing requirements, so that the path is reinforced at an early design stage, and the reliability of the integrated circuit is improved.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

The invention discloses a nuclear chemical engineering facility safety analysis method and system and electronic equipment, and belongs to the technical field of nuclear chemical plant safety analysis. The analysis method comprises the steps of obtaining an originating event list of the nuclear chemical engineering facility; according to the originating event list and the event sequence logic, respectively constructing an event tree model corresponding to each originating event; a fault tree model of a key fault branch in each event tree model is constructed, and the fault tree model comprises basic events connected with logic gates; calculating a basic event probability based on correlation analysis, human factor reliability analysis and an equipment failure database; and according to each event tree model, the fault tree model and the basic event probability, calculating a safety analysis result corresponding to each originating event. According to the method, the problems that a security analysis method based on a deterministic theory in the prior art is too conservative and low in accuracy can be solved.

The decimal quantization logic gate is a hardware logic operation design based on quantization logic, and the main design idea of the decimal quantization logic gate is that a linear multi-valued logic operation is used as a logic operation part to execute logic operations such as AND (small), OR (large) and NOT (complement); the multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like, and a multi-valued logic operation and multi-valued quantization'quantization logic 'circuit is formed by combining the structures of multi-valued quantization and logic operation together, and a multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like. The logic circuit always executes'quantization 'and'logic operation', so that the logic circuit is called'quantization logic '. The design of all previous'multi-valued logic gate 'and'two-valued logic gate' circuits is as follows: 'logical operation '(AND, OR, NOT) is firstly carried out, and then'quantization' (threshold detection) is carried out to set'fault-tolerant intervals'. Therefore, the quantization logic is the most original thought of logic hardware design.

The invention discloses a hardware acceleration system and method supporting a pulse-gated recurrent neural network, and relates to the technical field of neural network hardware acceleration, and the system comprises a PC terminal and an accelerator. The accelerator comprises a UART (Universal Asynchronous Receiver / Transmitter) module, a data composer, a storage module, a controller module, a calculation module and a gating calculation core, the PC terminal is connected with the UART module; the gating calculation core is connected with the data composer; and the controller module and the storage module are respectively connected with the UART module, the data composer, the calculation module and the gating calculation core. Based on the above scheme, different coding modes can be selected at a PC terminal to adapt to different data types, and a pulse neuron activation function and a logic gate are utilized to perform calculation heterogeneous design in a calculation module and a gating calculation core, so that a high-performance configurable hardware acceleration calculation architecture for the pulse gating recurrent neural network is realized.

Systems and procedures can perform sequential automatic test pattern generation (on parallel memory units). In one example, an array of logic gates (330-335) can output enable signals to cause multiple memory units (360, 361) to be enabled in parallel. The test pattern generation and test control logic (210) can perform forward path checking, backward path checking, and any other suitable check on the enabled memory units (360, 361). The systems and procedures can then move on to another group of memory units, enabling and testing them in parallel.

An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) ST CLK # based on PCLK assertion (0→1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.