708 results about "Logic gate" patented technology

A buck converter including a high-side switch, a low-side switch and a bootstrap (BOOT), under-voltage lockout (UVLO) circuit. The BOOT UVLO circuit includes a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event. The BOOT UVLO detection element is configured to output an UVLO signal (UVLO_Z), in case of the BOOT UVLO event. The BOOT UVLO circuit further includes a logic gate configured to receive the UVLO_Z and a high-side ON, (HSON) signal, the HSON signal is for controlling a switching of the high-side switch. The logic gate is configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby immediately switch OFF the high-side switch when the HSON signal is ON.

The invention belongs to the field of quantum computing, and particularly relates to a distortion correction optimization method and device for a quantum measurement and control link, and the method comprises the steps: applying a frequency control signal for loading a target pre-distortion waveform on a to-be-corrected quantum measurement and control Z link; setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit; obtaining the fidelity of the quantum state output by the selected quantum bit; in response to the fact that the fidelity does not reach the preset standard, updating the pre-distortion waveform, and returning to execute a frequency control signal for applying and loading the target pre-distortion waveform signal on the quantum measurement and control Z link to be corrected; and setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit until the fidelity reaches a preset standard. According to the invention, distortion correction can be rapidly and effectively carried out.

The invention discloses an implementation method of a quantum logic gate and a quantum computer system. The method comprises the following steps: preparing a quantum bit to a preset initial quantum state; according to the Hamiltonian corresponding to the quantum logic gate, respectively generating microwave signals corresponding to each segment in the Hamiltonian; the Hamiltonian of the quantum logic gate comprises at least two segments, and the at least two segments are used for enabling quantum bits to generate at least one polarity reversal in evolution; the generated microwave signals corresponding to all the segments are spliced; and applying a spliced microwave signal to the quantum bits in the initial quantum state, so that the quantum bits evolve from the initial quantum state to a target quantum state. According to the invention, the quantum bit can generate at least one polarity change in evolution, partial phase dispersion is offset by using the polarity characteristic of 1 / f noise, decoherence is inhibited, and the fidelity of the single-bit quantum logic gate is further improved.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

The invention discloses an intelligent fault tree generation method and system based on joint simulation and dynamic causal reasoning, relates to the technical field of fault trees, and solves the problems that the manual construction efficiency of a complex system fault tree is low, the hidden failure path omission ratio is high, and a model and operation and maintenance data are disjointed. The method comprises the following steps: constructing a multi-physics field coupled system joint simulation model; capturing a propagation path of the fault among the functional units in real time, and generating a fault propagation map; constructing a minimum cut set based on Monte Carlo simulation and Bayesian network reasoning, and automatically adapting an AND / OR logic gate to generate a fault tree; and dynamically updating the knowledge graph in combination with an online learning technology. The method has a good application prospect in the field of health management of equipment with high safety requirements.

The invention discloses an OEO amplifier with a high-speed hard switching function and an optical transmission system, and relates to the technical field of optical amplifiers, the OEO amplifier comprises three magneto-optical switches, an optical splitter group, a photoelectric detector group, a real-time comparison circuit, a logic gate control circuit and a driving circuit; the photoelectric detector group collects optical signal power to generate an electric signal; the real-time comparison circuit performs voltage threshold judgment on the electric signal; the logic gate control circuit is connected with the output end of the real-time comparison circuit so as to synchronously control the switching states of the three magneto-optical switches according to a voltage threshold judgment result; the driving circuit is used for driving the magneto-optical switch to synchronously execute a switching action; when the OEO amplifier detects that optical signals in any direction are interrupted, all the magneto-optical switches finish synchronous switching within 100 microseconds, and the end-to-end optical signal switching time difference is smaller than 2 picoseconds. The method is suitable for a single-fiber bidirectional optical communication environment requiring high frequency, high precision and high stability.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

The invention discloses a variable component sub-line compilation optimization method and a related device, and belongs to the technical field of quantum computing, and the method comprises the following steps: if a variable component sub-line is not compiled for the first time and a mapping relation is unchanged, calling quantum hardware resources to execute the compiled variable component sub-line so as to update logic gate parameters in the variable component sub-line, the mapping relation is used for representing the corresponding relation between the logic bits in the variable component sub-lines and the physical bits in the quantum hardware resources. According to the method, the mapping relation result is stored during the first compiling, and a mechanism for judging whether the compiling is the first compiling is introduced into the compiling process, so that the tedious remapping operation is avoided, the time and computing resources required by the compiling process are remarkably reduced, the parameter updating can be quickly responded, and the execution efficiency of the variable component sub-line is improved.

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

The invention relates to the technical field of data processing systems, and discloses a conference information intelligent data processing system based on multi-modal data fusion, and the system comprises a transaction template generation unit which calls a model from a preset rule base to generate a structured data container with an attribute field; the dual-channel feature extraction unit is used for distributing the voice to service data and a control instruction channel, extracting the service data to an independent cache region and monitoring a control keyword; the state control unit is used for unlocking the container only when the confirmation instruction is received, verifying data and writing a field to generate a transaction submission instruction; according to the system and the method, physical isolation of data flow and control flow is realized through a dual-channel architecture, a control instruction is used as a unique logic gating, non-decisive negotiation noise is filtered from the source, and atomicity and compliance of conversion from unstructured conference data to structured management transactions are ensured.

The invention relates to an ultraviolet photoelectric detector, a preparation method and application in a programmable logic gate. The apparatus includes: a support base; the ultraviolet band optical response unit comprises an optical substrate and an inorganic quantum dot photosensitive layer, and at least a PN junction is formed between the inorganic quantum dot photosensitive layer and the optical substrate; the charge transmission layer is located on the inorganic quantum dot photosensitive layer and at least forms atomic-scale heterogeneous contact with the inorganic quantum dot photosensitive layer, during photoelectric detection, target ultraviolet light irradiates on the charge transmission layer, and the charge transmission layer is electrically connected with the inorganic quantum dot photosensitive layer based on the detection light intensity state of the target ultraviolet light. The photo-generated current polarity of the ultraviolet photoelectric detector under the target ultraviolet light is regulated and controlled; the detection light intensity state at least comprises a comparison state between the light intensity of the target ultraviolet light and the detection critical light intensity. According to the invention, bipolar ultraviolet photoelectric detection under single-wavelength power modulation can be realized, and the reconfigurable polymorphic logic gate application can be effectively realized.

The utility model provides a half-bridge drive interlocking circuit, in which a logic circuit is provided with a logic gate; two input ends of the logic circuit respectively receive two control signals; the two control signals are in one-to-one correspondence with two switch tubes in the half-bridge circuit; when the two control signals are turn-on signals, the two output ends of the logic circuit output turn-off signals. A first output end of the logic circuit is connected with a control end of a first switching tube in the half-bridge circuit through a first driving circuit; a second output end of the logic circuit is connected with a control end of a second switching tube in the half-bridge circuit through a second driving circuit; namely, the logic circuit is built through the logic gate, the phenomenon of high-temperature attenuation caused by the adoption of an optical device is avoided, the logic circuit is not affected by the high-temperature environment, good performance stability can still be kept in the high-temperature environment, the signal transmission efficiency is high, and the driving accuracy and the reliability and safety of the system are improved.

The invention relates to a two-step time-to-digital converter and a method thereof, a phase-locked loop and an analog-to-digital converter. The method comprises the following steps of: performing N1-stage delay on a reference signal rs in sequence, and performing coarse quantization on the delayed signal of each stage relative to a feedback signal fb; when the two signals are different, after the time t1 is delayed, the first arriving signal is selected as a time starting signal Start and the fb is delayed for the time t1 and then serves as a time stopping signal Stop in the delayed period, and when the two signals are the same, the rs is selected as Start after the time t2 is delayed, and the fb is selected as Stop after the time t2 is delayed; performing fine quantization formation on the Start and the Stop; and decoding the code into n1-bit high-bit binary codes and decoding the code into n2-bit low-bit binary codes. The technical problem that the area and power consumption of an existing two-step TDC are increased due to the fact that the number of logic gates of a selector is greatly increased along with the increase of coarse quantization bits is solved.

The invention discloses a quantum bit mapping method, device and equipment, a medium and a computer program product, and the method comprises the steps: calculating initial quantum bit mapping according to the mutual relation between quantum bits on which each logic gate in a quantum circuit depends; the initial quantum bit mapping is initial mapping from logic quantum bits to physical quantum bits; generating a to-be-executed gate circuit set according to the execution dependency relationship among the logic gates in the quantum circuit; based on the initial quantum bit mapping, the execution cost of each to-be-executed gate circuit in the to-be-executed gate circuit set is calculated, and the to-be-executed gate circuit with the minimum execution cost is selected as a target execution gate circuit; and based on a preset heuristic cost function, calculating costs of different SWAP strategies of the target execution gate circuit, and determining optimal quantum bit mapping according to the SWAP strategy with the minimum cost. According to the invention, the insertion of the SWAP gate in the quantum circuit is significantly reduced, so that the efficiency and precision of quantum bit mapping are improved.

The invention discloses a floating-point number format conversion device and method, a storage medium and a program product, and relates to the technical field of floating-point number format conversion. The device comprises a preprocessing unit and a conversion mapping unit; the preprocessing unit is used for receiving input data in a first floating point format and performing bit width compression processing on at least part of digits influencing rounding operation in the input data to generate a corresponding index value, and the bit width of the index value is smaller than the mantissa bit width of the input data; the conversion mapping unit is coupled to the preprocessing unit, a plurality of mapping relations between index value ranges and numerical value representations in a second floating point format are stored in the conversion mapping unit, and the conversion mapping unit is used for searching the corresponding numerical value representations in the second floating point format according to the index values to serve as output data. The invention aims to reduce the number of logic gates and the circuit complexity required by floating-point number format conversion, so that the area of a related chip is reduced, the power consumption is reduced, and the operation delay is shortened.

In a general aspect, a multi-qubit quantum logic gate for a multi-qubit hardware-efficient stabilizer measurement is performed. In some implementations, a superconducting quantum processing unit includes a stabilizer check qubit device and two or more data qubit devices operably coupled to the stabilizer check qubit device through respective tunable-frequency coupler devices. A method includes applying a multi-qubit quantum logic gate on the stabilizer check qubit device and the two or more data qubit devices. Applying the multi-qubit quantum logic gate includes evolving the stabilizer check qubit device and the two or more data qubit devices under an interaction Hamiltonian with a plurality of terms. Each of the plurality of terms corresponding to an interaction between the stabilizer check qubit device and a respective one of the two or more data qubit devices, includes a phase combined with a Pauli operator applied to the stabilizer check qubit device and the Pauli operator applied to the respective one of the two or more data qubit devices.

Photonic controlled-phase gates that include a dipole emitter chirally coupled to a plurality of photonic qubit pairs in a waveguide are disclosed herein. Each photonic qubit pair includes a two-qubit state |xy, wherein the two-qubit state |xy comprises a combination of single-qubit states |0 and |1, and may be |00, |01, |10, and |11. The dipole emitter is configured to interact with the single-qubit state |0 to impose a π phase shift, and the dipole emitter interacts with states |00, |01, and |10 to impose the π phase shift.

A system for autonomous compliance with legal regulations in smart contracts; the system includes: a regulatory data collection unit comprising a network interface controller physically connected to an external communications port, a hardware-based public key infrastructure circuit configured to validate digital certificates of regulatory servers, and a direct memory access controller configured to transfer authenticated regulatory update packets from the network interface controller to a volatile buffer memory without processor intervention; a Compliance Code Conversion Unit with a hardware lexicon scanner implemented as a finite state machine and embedded in reconfigurable FPGA logic blocks, a microcontroller executing a hardware-based lexical analysis pipeline stored in firmware registers, and a translation cache memory configured to temporarily store tokenized compliance rules before writing them to a non-volatile instruction memory; a policy evaluation and enforcement unit comprising a transaction verification processor connected to a secure enclave memory, a hardware comparator circuit configured to compare transaction parameters with compliance thresholds stored in the secure enclave memory, and a logic gate circuit configured to generate execution gate signals that selectively allow, block, or modify smart contract execution signals transmitted to a blockchain execution processor; and an audit logging unit with a cryptographic hashing circuit configured to generate block hashes of enforcement records, a timestamp oscillator configured to generate temporal signatures of compliance enforcement actions, and a Merkle tree generation circuit configured to create tamper-proof hierarchical hash structures, with the enforcement records being passed to a decentralized storage interface for anchoring in the chain or distributed ledger.

A new inverting logic gate or a FET gate driver is disclosed. The logic gate mitigates the trade-off between power dissipation (or quiescent power) and slew rate of the typical RTL and DLL buffers by using an innovative circuit topology involving a pull-up bootstrapping transistor. The bootstrapping transistor may be an enhancement mode GaN field effect transistor (FET). This bootstrapping transistor may be driven by the complement of the input signal. Alternatively, the bootstrapping transistor may monitor the drain terminal of the pull-down transistor and conduct current accordingly. Other Boolean functions may also be achieved using this approach.

The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

The application discloses a vertical micro-mirror structure optical computing chip and a wafer-level intelligent manufacturing method thereof, and relates to the field of optical computing chips.The optical computing chip comprises a plurality of optical modulators and a plurality of quantum logic gates, and the optical modulators are provided with interference light paths based on vertical micro-mirrors, so that optical modulation is realized; the quantum logic gates construct stable light paths through the mirrors provided by the vertical micro-mirrors, realize interference by means of a beam splitter, and perform Hadamard transformation by a wave plate at the entrance or exit of a target light path, so that optical computing is realized; a deep-groove beam splitter or a deep-wall beam splitter is used as the beam splitter, the silicon walls in the deep-wall beam splitter are provided with a predetermined included angle perpendicular to the two side walls of the substrate, and the deep-groove beam splitter is manufactured in the following manner: a deep groove pattern is photoetched on the surface of a single-crystal silicon wafer; the deep groove with the predetermined angle is etched by deep etching and the side walls are smoothed; an optical thin film is deposited in the deep groove; the shape of the deep-groove beam splitter is photoetched and etched by deep etching, and the side walls are smoothed; and an optical antireflection film is grown on the vertical side walls.

Circuits and methods that enable a “break-before-make” process for an electronic switch that avoids the relatively large time delays of fixed time delay circuitry. Logic gates, rather than a time delay, are used to lock out an input switch through-path from turning ON before another input switch through-path is fully turned OFF. An embodiment includes a first and second monitor logic blocks, configured such that (1) a first through-path is turned OFF before a first shunt-path is allowed to turn ON and before a second shunt-path is allowed to turn OFF, and the second shunt-path is turned OFF before a second through-path is allowed to turn ON; and (2) the second through-path is turned OFF before the second shunt-path is allowed to turn ON and before the first shunt-path is allowed to turn OFF, and the first shunt-path is turned OFF before the first through-path is allowed to turn ON.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

A deep neural network circuit with multiple layers formed of multi-terminal logic gates is provided. In one aspect, the neural network circuit includes a plurality of logic gates arranged into a plurality of layers and a plurality of logical connectors arranged between each pair of adjacent layers. Each of the logical connectors connects the output of a first logic gate to the input of a second logic gate and each of the logical connectors has one of a plurality of different logical connector states. The neural network circuit is configured to be trained to implement a function by finding a set of the logical connector states for the logical connectors such that the neural network circuit implements the function.

The present application provides a memory with test function and a test method thereof. The memory includes a memory array having memory cells, input buffers divided into even groups and odd groups, and output buffers divided into even groups and odd groups; at least two data input pads providing test data to the memory cells via the even input buffers and the odd input buffers, respectively; first and second logic gates performing first logical operations on outputs of the even output buffers and the odd output buffers, respectively; a third logic gate performing a second logical operation on outputs of the first and second logic gates; and at least one data output pad coupled to an output of the third logic gate for providing test results of the memory cells.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

A multiply-accumulate unit comprises a first input configured to receive a first operand encoded using a two-bit encoding scheme in which a ternary value is represented by two bits, wherein identical bits indicate a non-computable value and different bits indicate a computable value. The unit further comprises a second input for receiving a second operand, a zero detection circuit with a logic gate that compares the two bits and generates a skip signal when they are identical, an arithmetic circuit for performing accumulation based on both operands, an accumulator register for storing the result, and a gating circuit that selectively enables writing to the accumulator register based on the skip signal, preventing writing when the first operand is non-computable.

The application discloses a kind of based on ensemble rare earth ions double quantum bit controlled gate construction method, it is related to quantum control technical field, it includes to double quantum bit frequency site selection, and respectively as control bit, target bit;Utilize the blocking effect generated by the dipole-dipole interaction between double quantum bits to construct controlled gate, including: to control bit apply light pulse driving control bit is from ground state transition to excited state;To target bit apply single quantum gate to drive its evolution, and apply compensation pulse;To control bit apply light pulse driving control bit from excited state de-excitation to ground state.The application utilizes the interaction of the light pulse and quantum system medium that can be optimized to produce arbitrary geometric quantum logic gate on target quantum bit, and simultaneously by using the blocking effect caused by dipole-dipole interaction, the evolution of target bit quantum bit can be constrained by control bit.

The present application relates to the technical field of field programmable gate array circuits, and discloses a method and system for optimizing FPGA technology mapping. The method first divides the input register transfer level circuit into several sub-circuits, and then transmits the user-specified original circuit input and output timing constraints to the input and output ends of each sub-circuit according to the "basic logic gate delay model", and performs technology mapping on each sub-circuit under this constraint. Then, the mapped sub-circuit is recalculated and its timing constraints are updated according to the "lookup table delay model", and technology mapping is performed again after adjustment. The two steps of updating the sub-circuit timing constraints and re-technology mapping are repeated until the timing constraints on all sub-circuits converge numerically. The present application can obtain an FPGA circuit with more optimized timing performance.