912 results about "Logic gate" patented technology

A buck converter including a high-side switch, a low-side switch and a bootstrap (BOOT), under-voltage lockout (UVLO) circuit. The BOOT UVLO circuit includes a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event. The BOOT UVLO detection element is configured to output an UVLO signal (UVLO_Z), in case of the BOOT UVLO event. The BOOT UVLO circuit further includes a logic gate configured to receive the UVLO_Z and a high-side ON, (HSON) signal, the HSON signal is for controlling a switching of the high-side switch. The logic gate is configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby immediately switch OFF the high-side switch when the HSON signal is ON.

The invention belongs to the field of quantum computing, and particularly relates to a distortion correction optimization method and device for a quantum measurement and control link, and the method comprises the steps: applying a frequency control signal for loading a target pre-distortion waveform on a to-be-corrected quantum measurement and control Z link; setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit; obtaining the fidelity of the quantum state output by the selected quantum bit; in response to the fact that the fidelity does not reach the preset standard, updating the pre-distortion waveform, and returning to execute a frequency control signal for applying and loading the target pre-distortion waveform signal on the quantum measurement and control Z link to be corrected; and setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit until the fidelity reaches a preset standard. According to the invention, distortion correction can be rapidly and effectively carried out.

The invention discloses an implementation method of a quantum logic gate and a quantum computer system. The method comprises the following steps: preparing a quantum bit to a preset initial quantum state; according to the Hamiltonian corresponding to the quantum logic gate, respectively generating microwave signals corresponding to each segment in the Hamiltonian; the Hamiltonian of the quantum logic gate comprises at least two segments, and the at least two segments are used for enabling quantum bits to generate at least one polarity reversal in evolution; the generated microwave signals corresponding to all the segments are spliced; and applying a spliced microwave signal to the quantum bits in the initial quantum state, so that the quantum bits evolve from the initial quantum state to a target quantum state. According to the invention, the quantum bit can generate at least one polarity change in evolution, partial phase dispersion is offset by using the polarity characteristic of 1 / f noise, decoherence is inhibited, and the fidelity of the single-bit quantum logic gate is further improved.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

The invention discloses an intelligent fault tree generation method and system based on joint simulation and dynamic causal reasoning, relates to the technical field of fault trees, and solves the problems that the manual construction efficiency of a complex system fault tree is low, the hidden failure path omission ratio is high, and a model and operation and maintenance data are disjointed. The method comprises the following steps: constructing a multi-physics field coupled system joint simulation model; capturing a propagation path of the fault among the functional units in real time, and generating a fault propagation map; constructing a minimum cut set based on Monte Carlo simulation and Bayesian network reasoning, and automatically adapting an AND / OR logic gate to generate a fault tree; and dynamically updating the knowledge graph in combination with an online learning technology. The method has a good application prospect in the field of health management of equipment with high safety requirements.

The invention discloses an OEO amplifier with a high-speed hard switching function and an optical transmission system, and relates to the technical field of optical amplifiers, the OEO amplifier comprises three magneto-optical switches, an optical splitter group, a photoelectric detector group, a real-time comparison circuit, a logic gate control circuit and a driving circuit; the photoelectric detector group collects optical signal power to generate an electric signal; the real-time comparison circuit performs voltage threshold judgment on the electric signal; the logic gate control circuit is connected with the output end of the real-time comparison circuit so as to synchronously control the switching states of the three magneto-optical switches according to a voltage threshold judgment result; the driving circuit is used for driving the magneto-optical switch to synchronously execute a switching action; when the OEO amplifier detects that optical signals in any direction are interrupted, all the magneto-optical switches finish synchronous switching within 100 microseconds, and the end-to-end optical signal switching time difference is smaller than 2 picoseconds. The method is suitable for a single-fiber bidirectional optical communication environment requiring high frequency, high precision and high stability.

Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

The invention discloses a true random number generator circuit based on 1T1R and a random number generation method thereof, belongs to the field of information security, and aims to solve the problem that in most true random number generator circuit designs based on volatile memristors, peripheral circuits generally comprise logic gates, triggers and clock signal generators, so that the reliability of the true random number generator circuit is greatly improved. The circuit comprises a memristor, a transistor and a T flip-flop, and the memristor, the transistor and the T flip-flop are connected with the memristor and the T flip-flop respectively. One end of the memristor is connected with an input voltage # imgabs0 #, and the other end of the memristor is connected in series to the drain electrode of the transistor through a first wire; the grid electrode of the transistor is connected to a fixed voltage # imgabs1 #, and the source electrode of the transistor is grounded; a second wire is led out from the first wire connected with the memristor and the transistor and is connected to the clock end of the T trigger, and the cross connection point of the first wire and the second wire is an output node # imgabs2.

The invention relates to a power device driving fault detection circuit and a use method thereof. The power device driving fault detection circuit comprises a control circuit, an inverter circuit, a first comparator, a second comparator and a detection circuit, the control circuit outputs a complementary signal to drive a power device in the inverter circuit, and the inverter circuit supplies power to post-stage equipment and provides a voltage signal for the comparator; the first comparator detects grid and source voltage of the upper bridge power device, the second comparator detects grid and source voltage of the lower bridge power device, and results are input into the detection circuit. The detection circuit uses a logic gate to determine whether the upper and lower bridge arm power devices are simultaneously conducted or not so as to realize dead zone detection. According to the system, hardware circuits and excessive controller pins do not need to be added, the detection process is safe, and large current cannot be generated.

The invention discloses a variable component sub-line compilation optimization method and a related device, and belongs to the technical field of quantum computing, and the method comprises the following steps: if a variable component sub-line is not compiled for the first time and a mapping relation is unchanged, calling quantum hardware resources to execute the compiled variable component sub-line so as to update logic gate parameters in the variable component sub-line, the mapping relation is used for representing the corresponding relation between the logic bits in the variable component sub-lines and the physical bits in the quantum hardware resources. According to the method, the mapping relation result is stored during the first compiling, and a mechanism for judging whether the compiling is the first compiling is introduced into the compiling process, so that the tedious remapping operation is avoided, the time and computing resources required by the compiling process are remarkably reduced, the parameter updating can be quickly responded, and the execution efficiency of the variable component sub-line is improved.

A memory output circuit for selectively propagating proximate memory output data in a memory array of superconducting memory cells includes multiple datum inputs adapted to operably receive corresponding memory state signals from physically adjacent bit lines in the memory array, and at least one logic gate configured to implement logical OR functionality. The logic gate includes multiple inputs, for receiving at least a subset of the datum inputs operatively coupled thereto, and an output for propagating at least one datum output signal. The memory output circuit further includes at least one delay element operatively coupled to a corresponding one of the datum inputs. The delay element is configured to generate an output signal operably connected to a corresponding one of the inputs of the logic gate, the output signal generated by the delay element being a temporal sequence of at least a subset of the memory state signals supplied thereto delayed by a prescribed delay value.

The invention discloses a transmission type liquid crystal terahertz spatial light modulator with a large switch ratio. The transmission type liquid crystal terahertz spatial light modulator structurally comprises an upper-layer quartz substrate, an upper-layer metal structure, a liquid crystal layer, a lower-layer metal structure and a lower-layer quartz substrate in sequence from top to bottom, the upper-layer metal structure is adhered to the back surface of the upper-layer quartz substrate and is a four-opening square ring reverse structure array, and the lower-layer metal structure is adhered to the top surface of the lower-layer quartz substrate; and the liquid crystal layer is filled between the upper-layer metal structure and the lower-layer metal structure to form a metal-medium-metal structure. The electro-optical effect of the liquid crystal is utilized, the FPGA is communicated with the electrodes corresponding to the metal structures, voltage is applied between the upper-layer metal structure and the lower-layer metal structure, the effective dielectric constant of the liquid crystal can be changed by adjusting the voltage, and therefore on-off of terahertz waves is achieved. And the upper computer controls the FPGA to output voltage through an instruction so as to realize programmable regulation and control of the device.

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

The invention relates to the technical field of data processing systems, and discloses a conference information intelligent data processing system based on multi-modal data fusion, and the system comprises a transaction template generation unit which calls a model from a preset rule base to generate a structured data container with an attribute field; the dual-channel feature extraction unit is used for distributing the voice to service data and a control instruction channel, extracting the service data to an independent cache region and monitoring a control keyword; the state control unit is used for unlocking the container only when the confirmation instruction is received, verifying data and writing a field to generate a transaction submission instruction; according to the system and the method, physical isolation of data flow and control flow is realized through a dual-channel architecture, a control instruction is used as a unique logic gating, non-decisive negotiation noise is filtered from the source, and atomicity and compliance of conversion from unstructured conference data to structured management transactions are ensured.

The invention relates to an ultraviolet photoelectric detector, a preparation method and application in a programmable logic gate. The apparatus includes: a support base; the ultraviolet band optical response unit comprises an optical substrate and an inorganic quantum dot photosensitive layer, and at least a PN junction is formed between the inorganic quantum dot photosensitive layer and the optical substrate; the charge transmission layer is located on the inorganic quantum dot photosensitive layer and at least forms atomic-scale heterogeneous contact with the inorganic quantum dot photosensitive layer, during photoelectric detection, target ultraviolet light irradiates on the charge transmission layer, and the charge transmission layer is electrically connected with the inorganic quantum dot photosensitive layer based on the detection light intensity state of the target ultraviolet light. The photo-generated current polarity of the ultraviolet photoelectric detector under the target ultraviolet light is regulated and controlled; the detection light intensity state at least comprises a comparison state between the light intensity of the target ultraviolet light and the detection critical light intensity. According to the invention, bipolar ultraviolet photoelectric detection under single-wavelength power modulation can be realized, and the reconfigurable polymorphic logic gate application can be effectively realized.

The invention provides a layout structure of a NORD flash memory, and the layout structure comprises a substrate which comprises an array region and an end region which are adjacent to each other; the multiple rows of word lines, the multiple rows of first control lines and the multiple rows of second control lines are located on the surface of the substrate in the array area at intervals, one side of each row of word lines is the first control line, and the other side of each row of word lines is the second control line; the logic grids are located on the surface of the substrate in the end region, the first control line and the second control line between every two adjacent word lines are communicated through one logic grid, and the multiple logic grids are arranged at intervals and located on the same straight line; the metal lines are located above the word lines, the first control lines and the second control lines, and each metal line is connected with one logic gate. According to the invention, the first control line and the second control line between every two adjacent word lines are communicated to one logic gate, so that the number of the logic gates is reduced.

The invention discloses a Si / SiC hybrid parallel device driving circuit with a variable switching time sequence. The Si / SiC hybrid parallel device driving circuit comprises a time sequence switching signal generating circuit, a time delay switch and time sequence switching circuit and a push-pull output circuit. A driving signal is sent by a main control chip, two different driving signals are respectively generated through calculation of a time delay circuit and a plurality of logic gates, and a conventional driving time sequence of normal switching on and off of a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor), delayed switching-on of a Si IGBT (Insulated Gate Bipolar Transistor) and switching-off in advance can be adapted. And meanwhile, a timing sequence switching signal generation circuit detects and compares the conduction current of the SiC MOSFET so as to generate a timing sequence switching signal. And when the conduction current of the SiC MOSFET is in different regions, switching the switching time sequence of the Si / SiC hybrid parallel device. According to the invention, within the whole operation range of the Si / SiC hybrid parallel device, the lowest switching loss and conduction loss are ensured, and the reliability of the SiC MOSFET is greatly improved.

The invention relates to an information-missing-oriented super-large-scale integrated circuit security design detection method, and belongs to the field of hardware Trojan horse detection. The method comprises the following steps: analyzing a gate-level netlist design file of the super-large-scale integrated circuit with missing information, creating directed graph representation, performing feature representation coding on logic gate nodes, and constructing circuit directed graph data; performing structural reasoning on the directed graph data by using a graph variation auto-encoder GraphVAE, complementing a circuit structure with information loss by using a decoder, and constructing complemented circuit directed graph data; performing logic gate type, fan-in and fan-out quantity, betweenness centrality and neighborhood type distribution calculation on the complemented data, and combining and splicing the complemented data into circuit gate characteristics; and constructing a graph neural network model GNN, further extracting deep-level features through graph convolution operation, and performing reasoning training by adopting a multi-layer perceptron to realize hardware Trojan classification. According to the method, the hardware Trojan of the gate-level netlist under the condition of information loss can be effectively detected.

One example aspect of the present disclosure is directed to a method for characterizing a multi-qubit logic gate operating on a pair of qubits. The method includes iteratively performing, via a multi-qubit quantum circuit, a set of serial operations on the pair of qubits. The multi-qubit quantum circuit includes the multi-qubit logic gate, a first single-qubit logic gate operating on the first qubit, and a second single-qubit logic gate operating on the second qubit. After iteratively performing the set of serial operations on the pair of qubits, a first quantum state of the first qubit and a second quantum state of the second qubit are measured. A first set of expectation values for the first qubit and a second set of expectation values for the second qubit are determined. A value for a first parameter of a set of parameters of the multi-qubit logic gate is determined.

Methods, systems and apparatus for simulating quantum circuits including multiple quantum logic gates. In one aspect, a method includes the actions of representing the multiple quantum logic gates as functions of one or more classical Boolean variables that define a undirected graphical model with each classical Boolean variable representing a vertex in the model and each function of respective classical Boolean variables representing a clique between vertices corresponding to the respective classical Boolean variables; representing the probability of obtaining a particular output bit string from the quantum circuit as a first sum of products of the functions; and calculating the probability of obtaining the particular output bit string from the quantum circuit by directly evaluating the sum of products of the functions. The calculated partition function is used to (i) calibrate, (ii) validate, or (iii) benchmark quantum computing hardware implementing a quantum circuit.

The utility model provides a half-bridge drive interlocking circuit, in which a logic circuit is provided with a logic gate; two input ends of the logic circuit respectively receive two control signals; the two control signals are in one-to-one correspondence with two switch tubes in the half-bridge circuit; when the two control signals are turn-on signals, the two output ends of the logic circuit output turn-off signals. A first output end of the logic circuit is connected with a control end of a first switching tube in the half-bridge circuit through a first driving circuit; a second output end of the logic circuit is connected with a control end of a second switching tube in the half-bridge circuit through a second driving circuit; namely, the logic circuit is built through the logic gate, the phenomenon of high-temperature attenuation caused by the adoption of an optical device is avoided, the logic circuit is not affected by the high-temperature environment, good performance stability can still be kept in the high-temperature environment, the signal transmission efficiency is high, and the driving accuracy and the reliability and safety of the system are improved.

The invention relates to a two-step time-to-digital converter and a method thereof, a phase-locked loop and an analog-to-digital converter. The method comprises the following steps of: performing N1-stage delay on a reference signal rs in sequence, and performing coarse quantization on the delayed signal of each stage relative to a feedback signal fb; when the two signals are different, after the time t1 is delayed, the first arriving signal is selected as a time starting signal Start and the fb is delayed for the time t1 and then serves as a time stopping signal Stop in the delayed period, and when the two signals are the same, the rs is selected as Start after the time t2 is delayed, and the fb is selected as Stop after the time t2 is delayed; performing fine quantization formation on the Start and the Stop; and decoding the code into n1-bit high-bit binary codes and decoding the code into n2-bit low-bit binary codes. The technical problem that the area and power consumption of an existing two-step TDC are increased due to the fact that the number of logic gates of a selector is greatly increased along with the increase of coarse quantization bits is solved.

The invention discloses a quantum bit mapping method, device and equipment, a medium and a computer program product, and the method comprises the steps: calculating initial quantum bit mapping according to the mutual relation between quantum bits on which each logic gate in a quantum circuit depends; the initial quantum bit mapping is initial mapping from logic quantum bits to physical quantum bits; generating a to-be-executed gate circuit set according to the execution dependency relationship among the logic gates in the quantum circuit; based on the initial quantum bit mapping, the execution cost of each to-be-executed gate circuit in the to-be-executed gate circuit set is calculated, and the to-be-executed gate circuit with the minimum execution cost is selected as a target execution gate circuit; and based on a preset heuristic cost function, calculating costs of different SWAP strategies of the target execution gate circuit, and determining optimal quantum bit mapping according to the SWAP strategy with the minimum cost. According to the invention, the insertion of the SWAP gate in the quantum circuit is significantly reduced, so that the efficiency and precision of quantum bit mapping are improved.

A method, apparatus and product comprising: obtaining a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits manipulated by a plurality of logical gates; and generating a physical representation of the quantum circuit, the physical representation is configured to allocate a set of physical qubits of a quantum computer to the plurality of logical qubits in order to implement error correction operations The generating includes selecting a first quantity of physical qubits from the set of physical qubits for a first separate section of the quantum circuit; selecting a second quantity of physical qubits from the set of physical qubits for a second separate section of the quantum circuit, and synthesizing the quantum circuit using the first and second quantities for the first and second separate sections.

The invention discloses a floating-point number format conversion device and method, a storage medium and a program product, and relates to the technical field of floating-point number format conversion. The device comprises a preprocessing unit and a conversion mapping unit; the preprocessing unit is used for receiving input data in a first floating point format and performing bit width compression processing on at least part of digits influencing rounding operation in the input data to generate a corresponding index value, and the bit width of the index value is smaller than the mantissa bit width of the input data; the conversion mapping unit is coupled to the preprocessing unit, a plurality of mapping relations between index value ranges and numerical value representations in a second floating point format are stored in the conversion mapping unit, and the conversion mapping unit is used for searching the corresponding numerical value representations in the second floating point format according to the index values to serve as output data. The invention aims to reduce the number of logic gates and the circuit complexity required by floating-point number format conversion, so that the area of a related chip is reduced, the power consumption is reduced, and the operation delay is shortened.

In a general aspect, a multi-qubit quantum logic gate for a multi-qubit hardware-efficient stabilizer measurement is performed. In some implementations, a superconducting quantum processing unit includes a stabilizer check qubit device and two or more data qubit devices operably coupled to the stabilizer check qubit device through respective tunable-frequency coupler devices. A method includes applying a multi-qubit quantum logic gate on the stabilizer check qubit device and the two or more data qubit devices. Applying the multi-qubit quantum logic gate includes evolving the stabilizer check qubit device and the two or more data qubit devices under an interaction Hamiltonian with a plurality of terms. Each of the plurality of terms corresponding to an interaction between the stabilizer check qubit device and a respective one of the two or more data qubit devices, includes a phase combined with a Pauli operator applied to the stabilizer check qubit device and the Pauli operator applied to the respective one of the two or more data qubit devices.

A single nucleotide polymorphism typing method based on a CRISPR / Cas12a logic gate realizes typing output of single nucleotide polymorphism through logic gate input of fluorescence signals of a CRISPR / Cas12a reaction system, namely ''existence'' and ''no'', ''strong'' and ''weak'', and is characterized in that the novel single nucleotide polymorphism typing method comprises two steps of target fragment amplification and CRISPR / Cas12a detection; wherein the target fragment amplification is characterized in that a PAM recognition sequence TTTN of CRISPR / Cas12a is introduced to a-15 site to a-11 site of a target site through the design of an amplification primer, and an amplification product can be detected by the CRISPR / Cas12a; according to the CRISPR / Cas12a detection, two crRNA1 and crRNA2 which can distinguish wild type and mutant type amplification products are used as guide chains of a CRISPR / Cas12a reaction system, a novel functionalized single-stranded DNA report probe is designed, and single nucleotide polymorphism typing is achieved through logic gates of'existence 'and'absence' and'strong 'and'weak' of fluorescence signals. The method solves the problem that a traditional CRISPR / Cas12a reaction system cannot realize single nucleotide polymorphism typing, can be used for scientific research analysis and clinical detection, and has a wide market prospect.