1138 results about "Logic gate" patented technology

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

Various systems and methods are presented regarding applying a non-Clifford logical CCZ gate in a 2D topological code, e.g., a 2D Abelian code. A Kirigami cut and fold process is applied to an initial 3D quantum error-correcting code composed of three copies of 3D surface codes to reduce (cut) a qubit lattice to a hollow cube such that the cube is formed of surfaces comprising qubits. The CCZ is applied to the hollow cube, with the cube subsequently flattened (folded) from the 3D arrangement to a 2D code arrangement. A lattice surgery process can be performed to map / transfer the 2D code arrangement to an ancilla Kirigami code(s), whereupon the 2D code arrangement can be returned to a 2D surface code for further application of a logical Clifford gate, if so desired.

The invention discloses a startup method, a shutdown method, a logic device, a server and a readable storage medium, the logic device is located in the server, the logic device is in communication connection with a field programmable gate array of the server, and after the server is powered on, the logic device is triggered to be reloaded by firmware; after firmware reloading is completed, a standby component of the server is powered on, and the state of the standby component is monitored; after it is monitored that the field programmable gate array is started, level information is transmitted to the field programmable gate array; and after the standby time sequence control is finished, performing power-on time sequence interaction with the field programmable gate array under the condition of receiving a power-on signal, and performing power-on processing on the processor. The method and the device have the technical effects that the startup action can be realized only by performing the standby time sequence and the power-on time sequence on the logic device and the field programmable logic gate array, and decoupling of the startup and shutdown of the server and the substrate management controller is realized, so that the startup and shutdown of the server are accelerated.

In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Disclosed are a mapping method for a quantum program and a quantum chip, a quantum computer, and a computer. The method comprises: obtaining topological structures of physical bits in a quantum chip, a logic gate set of an initial quantum program, and an initial mapping relationship between logic bits and the physical bits; determining an execution timing of the logic gate set of the initial quantum program bits; according to the topological structures of physical bits and the initial mapping relationship, adjusting the mapping relationships between the logic bits and the physical bits corresponding to each logic gate so as to obtain the final mapping relationship; and according to the final mapping relationship, constructing the to-be-mapped quantum program equivalent to the initial quantum program to minimize the number of SWAP quantum logic gates in the to-be-mapped quantum program.

The invention discloses a quantum computing fluid dynamics simulation method based on a lattice Boltzmann method, and the method combines the parallelism of quantum computing with the advantages of the lattice Boltzmann method. An efficient fluid dynamics solving framework is constructed through a collision operator in a non-equilibrium correction term linearization lattice Boltzmann equation which is obtained by deducing through a Chapman-Enskog theory and a Maxwell equilibrium state function, wherein the non-equilibrium correction term linearization lattice Boltzmann equation contains an adjustable relaxation parameter. The quantum state in the Hilbert space can be converted through a quantum logic gate due to the characteristics of quantum calculation, so that the problem of complex calculation in fluid mechanics is efficiently solved. According to the method, the actual problem is coded into the quantum state vector of the quantum bit, the vector is directly changed through quantum operation to solve the problem, the quantum bit state does not need to be iterated one by one, for example, in the matrix and vector multiplication process, operation can be completed only by using a quantum logic gate to act on the input quantum state, and therefore the calculation efficiency is remarkably improved.

The invention discloses an amplitude coding quantum circuit construction method and a related device, and the method comprises the steps: obtaining a data value group which comprises a plurality of data values; the method comprises the following steps: constructing a first quantum circuit comprising a first quantum bit and a second quantum bit, the first quantum circuit comprising a plurality of first quantum revolving doors sequentially acting on the first quantum bit and a logic gate combination of a variational encoder simultaneously acting on the first quantum bit and the second quantum bit, each first quantum revolving door is used for encoding a data value in an angle encoding mode to obtain an input quantum state under the condition that the first quantum bit is a ground state, and each variational encoder is used for compressing the input quantum state in the corresponding logic gate combination to a second quantum bit. Compared with the prior art, the variational encoder is adopted to simulate amplitude coding, the line depth is reduced, and therefore the problem that decoherence is likely to be caused by amplitude coding on a real quantum computer is solved.

The embodiment of the invention discloses a static time sequence analysis method and device based on layout features and electronic equipment. According to the scheme, the gate-level netlist of the circuit can be obtained, the time sequence diagram is established according to the gate-level netlist, the nodes and the directed edges in the time sequence diagram are filled with the first statistical characteristics respectively, the first layout characteristics of each connection network in the time sequence diagram are calculated, and the time sequence diagram is expanded according to the first layout characteristics; and constructing a static time sequence analysis prediction model based on the graph neural network and the convolutional neural network, and predicting the delay of a connecting line time sequence arc, the delay of a logic gate time sequence arc and the delay of a pin node in the expanded time sequence diagram, thereby determining a static time sequence analysis result. According to the method, the layout characteristics of the circuit are obtained by extracting and coding the nodes of the connection network, and the static time sequence analysis prediction model is modeled according to the layout characteristics, so that the prediction accuracy of the prediction model in the layout areas with different aspect ratios is improved.

The invention discloses an aggregate loading size identification and detection control system based on radar identification, and particularly relates to the field of constructional engineering, which comprises a multi-source sensing module, a feature extraction module, an index calculation module, a threshold judgment module, a logic decision module and a control execution module. Characteristic parameters such as phase difference and coordinate deviation are extracted through multi-modal processing, four kinds of comprehensive indexes such as volume uniformity and overload risk are generated, risk grading early warning is achieved through a three-level threshold system, a control instruction is generated in combination with a state machine model and a logic gate strategy, and the system is provided with an electro-hydraulic proportional valve and a redundant braking mechanism. The system supports multi-stage response from rate adjustment to emergency braking, has the characteristics of multi-dimensional dynamic monitoring, intelligent decision making and environment self-adaption, effectively improves the safety and automation level of bulk cargo loading operation, and is suitable for continuous operation requirements of complex industrial scenes.

A buck converter including a high-side switch, a low-side switch and a bootstrap (BOOT), under-voltage lockout (UVLO) circuit. The BOOT UVLO circuit includes a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event. The BOOT UVLO detection element is configured to output an UVLO signal (UVLO_Z), in case of the BOOT UVLO event. The BOOT UVLO circuit further includes a logic gate configured to receive the UVLO_Z and a high-side ON, (HSON) signal, the HSON signal is for controlling a switching of the high-side switch. The logic gate is configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby immediately switch OFF the high-side switch when the HSON signal is ON.

The invention belongs to the field of quantum computing, and particularly relates to a distortion correction optimization method and device for a quantum measurement and control link, and the method comprises the steps: applying a frequency control signal for loading a target pre-distortion waveform on a to-be-corrected quantum measurement and control Z link; setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit; obtaining the fidelity of the quantum state output by the selected quantum bit; in response to the fact that the fidelity does not reach the preset standard, updating the pre-distortion waveform, and returning to execute a frequency control signal for applying and loading the target pre-distortion waveform signal on the quantum measurement and control Z link to be corrected; and setting a first logic gate for quantum state operation on an XY control line of the selected quantum bit until the fidelity reaches a preset standard. According to the invention, distortion correction can be rapidly and effectively carried out.

The utility model discloses a storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistors. The storage and calculation integrated majority voting logic gate circuit comprises an input module, an operation module, a discharge module and an output module, the input module receives three voltage signals and transmits the three voltage signals to the operation module according to a time sequence; the operation module comprises a ferroelectric field effect transistor, formation and damage of a conducting channel of the ferroelectric field effect transistor are directionally changed according to voltage signals received by a grid electrode and a source electrode, a nonvolatile operation relation with an external voltage signal as input and on-off of an internal channel as output is established, a logic input variable form is unified, and majority voting logic operation is executed. The discharging module adjusts a voltage signal of the operation module in a reading stage to prevent misreading; the output module accurately reads a nonvolatile operation result as a voltage signal; the circuit has the advantages that the storable majority voting logic function can be realized with a small number of transistors, the logic input variable form is unified, and the operation cascading capability and the circuit expandability are improved.

The invention belongs to the technical field of optical fiber gas sensing, and discloses an optical fiber photoacoustic gas sensing system and method suitable for a low-pressure environment. The system comprises a programmable logic gate array circuit, a distributed feedback laser, a laser transmission optical fiber, an optical fiber photoacoustic sensing probe, a super-radiation light-emitting diode light source, an optical fiber circulator and a spectrograph. The air pressure is monitored according to the linear relation between the resonance frequency of the cantilever beam and the ambient air pressure, the characteristic that the acoustic sensitivity at the resonance position of the cantilever beam is enhanced under the low air pressure is utilized to make up for signal attenuation in the photoacoustic excitation process, and the sensitivity is corrected in combination with the air pressure measured by the cantilever beam. Therefore, high-precision and high-sensitivity detection of trace gas in a low-pressure environment is realized. The system only adopts a single cantilever beam and a single demodulator, has the functions of gas pressure and gas concentration detection, and can realize accurate detection of trace gas in a gas pressure change environment. And an all-fiber scheme is adopted, so that intrinsic safety is realized, and remote measurement and multi-point network group detection are easy.

The invention discloses an implementation method of a quantum logic gate and a quantum computer system. The method comprises the following steps: preparing a quantum bit to a preset initial quantum state; according to the Hamiltonian corresponding to the quantum logic gate, respectively generating microwave signals corresponding to each segment in the Hamiltonian; the Hamiltonian of the quantum logic gate comprises at least two segments, and the at least two segments are used for enabling quantum bits to generate at least one polarity reversal in evolution; the generated microwave signals corresponding to all the segments are spliced; and applying a spliced microwave signal to the quantum bits in the initial quantum state, so that the quantum bits evolve from the initial quantum state to a target quantum state. According to the invention, the quantum bit can generate at least one polarity change in evolution, partial phase dispersion is offset by using the polarity characteristic of 1 / f noise, decoherence is inhibited, and the fidelity of the single-bit quantum logic gate is further improved.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

The invention discloses a method for solving a task-platform optimization configuration problem based on QGA quantum enhancement, and the method comprises the steps: firstly, employing the true randomness and entanglement of quantum, achieving the coding of a corresponding relation between a task and a platform through a quantum state, and determining an optimal individual in a population through a fitness function; secondly, a quantum logic gate is used for achieving selection operation in the algorithm, and the rotation angle and direction of the quantum logic gate are determined through the fitness difference value between each chromosome and the optimal chromosome; then, a quantum logic gate X and a quantum logic gate SWAP are used for achieving mutation operation and crossover operation in the algorithm respectively; the method provided by the invention has high accuracy and timeliness, the number of algorithm iterations and the time complexity are greatly reduced, and the method can be effectively used for solving the task-platform optimization configuration problem in the military C2 organization.

The invention discloses a quantum logic gate, a quadratic function quantum state preparation method and a related device, and the quadratic function quantum state preparation method comprises the steps: determining a quantum bit for preparing a quadratic function quantum state; a target quantum circuit is constructed, the target quantum circuit is provided with first quantum logic gates and second quantum logic gates which act on the quantum bits, each action time sequence comprises one first quantum logic gate, and each first quantum logic gate acts on three quantum bits; the first quantum logic gate acts on the lowest quantum bit and the adjacent quantum bits; and operating the target quantum circuit to prepare a quadratic function quantum state. Compared with the prior art, according to the quadratic function quantum state preparation method provided by the invention, the depth of a circuit only needs an O (n) layer or an O (logn) layer, and the running time of a quantum computer can be effectively compressed.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

The invention discloses a short-path optical pulse based on a three-energy-level system, a generation method and application. Specific forms of Hamiltonian and Rabian frequency parameters thereof are constructed in a three-level quantum system, and the parameters are optimized to obtain a light pulse which enables an evolution path of a quantum state on a Bloch sphere to be shortest and is high in fidelity. According to the optical pulse obtained by the technical scheme, the quantum state can be changed into a target state from any initial state through a circular evolution path, and logic gate operation is executed. The evolution time of the gate can be effectively shortened through the circular evolution trajectory, and the quantum gate reduces the influence of environmental noise while keeping the robustness of the control error. According to the quantum logic gate, multi-parameter optimization is carried out on the optical pulse waveform, the quantum logic gate is suitable for a rare earth ion Pr < 3 + >: Y2SiO5 quantum bit system device and an inverted-V-shaped three-energy-level system, and the high-fidelity quantum logic gate is obtained.

The invention discloses an intelligent fault tree generation method and system based on joint simulation and dynamic causal reasoning, relates to the technical field of fault trees, and solves the problems that the manual construction efficiency of a complex system fault tree is low, the hidden failure path omission ratio is high, and a model and operation and maintenance data are disjointed. The method comprises the following steps: constructing a multi-physics field coupled system joint simulation model; capturing a propagation path of the fault among the functional units in real time, and generating a fault propagation map; constructing a minimum cut set based on Monte Carlo simulation and Bayesian network reasoning, and automatically adapting an AND / OR logic gate to generate a fault tree; and dynamically updating the knowledge graph in combination with an online learning technology. The method has a good application prospect in the field of health management of equipment with high safety requirements.

The invention discloses an OEO amplifier with a high-speed hard switching function and an optical transmission system, and relates to the technical field of optical amplifiers, the OEO amplifier comprises three magneto-optical switches, an optical splitter group, a photoelectric detector group, a real-time comparison circuit, a logic gate control circuit and a driving circuit; the photoelectric detector group collects optical signal power to generate an electric signal; the real-time comparison circuit performs voltage threshold judgment on the electric signal; the logic gate control circuit is connected with the output end of the real-time comparison circuit so as to synchronously control the switching states of the three magneto-optical switches according to a voltage threshold judgment result; the driving circuit is used for driving the magneto-optical switch to synchronously execute a switching action; when the OEO amplifier detects that optical signals in any direction are interrupted, all the magneto-optical switches finish synchronous switching within 100 microseconds, and the end-to-end optical signal switching time difference is smaller than 2 picoseconds. The method is suitable for a single-fiber bidirectional optical communication environment requiring high frequency, high precision and high stability.

The invention discloses a time service module and electronic equipment. The time service module comprises a programmable logic module, a main control module and a crystal oscillator module; the programmable logic module is connected with the crystal oscillator module, the crystal oscillator module outputs a clock frequency signal, and the programmable logic module outputs a first pulse signal according to the clock frequency signal; the programmable logic module comprises a source end logic gate unit, an output end logic gate unit and a counting unit, the source end logic gate unit is connected with a source pulse signal, the output end logic gate unit is connected with a first pulse signal, and the counting unit is connected with the source end logic gate unit and the output end logic gate unit; the counting unit outputs a first data signal according to the number of the switched-on logic gates in the source end logic gate unit and the number of the switched-on logic gates in the output end logic gate unit; the master control module calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal. The time service module provided by the invention has relatively high locking precision.

Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

The invention discloses a true random number generator circuit based on 1T1R and a random number generation method thereof, belongs to the field of information security, and aims to solve the problem that in most true random number generator circuit designs based on volatile memristors, peripheral circuits generally comprise logic gates, triggers and clock signal generators, so that the reliability of the true random number generator circuit is greatly improved. The circuit comprises a memristor, a transistor and a T flip-flop, and the memristor, the transistor and the T flip-flop are connected with the memristor and the T flip-flop respectively. One end of the memristor is connected with an input voltage # imgabs0 #, and the other end of the memristor is connected in series to the drain electrode of the transistor through a first wire; the grid electrode of the transistor is connected to a fixed voltage # imgabs1 #, and the source electrode of the transistor is grounded; a second wire is led out from the first wire connected with the memristor and the transistor and is connected to the clock end of the T trigger, and the cross connection point of the first wire and the second wire is an output node # imgabs2.

An IC device includes a first interconnect structure configured to distribute a power supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gating signal, and a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes a power switch coupled in series with a logic gate between the first and second interconnect structures, and the power switch includes a control terminal coupled to the third interconnect structure.

The invention relates to a power device driving fault detection circuit and a use method thereof. The power device driving fault detection circuit comprises a control circuit, an inverter circuit, a first comparator, a second comparator and a detection circuit, the control circuit outputs a complementary signal to drive a power device in the inverter circuit, and the inverter circuit supplies power to post-stage equipment and provides a voltage signal for the comparator; the first comparator detects grid and source voltage of the upper bridge power device, the second comparator detects grid and source voltage of the lower bridge power device, and results are input into the detection circuit. The detection circuit uses a logic gate to determine whether the upper and lower bridge arm power devices are simultaneously conducted or not so as to realize dead zone detection. According to the system, hardware circuits and excessive controller pins do not need to be added, the detection process is safe, and large current cannot be generated.

The invention discloses a variable component sub-line compilation optimization method and a related device, and belongs to the technical field of quantum computing, and the method comprises the following steps: if a variable component sub-line is not compiled for the first time and a mapping relation is unchanged, calling quantum hardware resources to execute the compiled variable component sub-line so as to update logic gate parameters in the variable component sub-line, the mapping relation is used for representing the corresponding relation between the logic bits in the variable component sub-lines and the physical bits in the quantum hardware resources. According to the method, the mapping relation result is stored during the first compiling, and a mechanism for judging whether the compiling is the first compiling is introduced into the compiling process, so that the tedious remapping operation is avoided, the time and computing resources required by the compiling process are remarkably reduced, the parameter updating can be quickly responded, and the execution efficiency of the variable component sub-line is improved.

A memory output circuit for selectively propagating proximate memory output data in a memory array of superconducting memory cells includes multiple datum inputs adapted to operably receive corresponding memory state signals from physically adjacent bit lines in the memory array, and at least one logic gate configured to implement logical OR functionality. The logic gate includes multiple inputs, for receiving at least a subset of the datum inputs operatively coupled thereto, and an output for propagating at least one datum output signal. The memory output circuit further includes at least one delay element operatively coupled to a corresponding one of the datum inputs. The delay element is configured to generate an output signal operably connected to a corresponding one of the inputs of the logic gate, the output signal generated by the delay element being a temporal sequence of at least a subset of the memory state signals supplied thereto delayed by a prescribed delay value.

The invention discloses a transmission type liquid crystal terahertz spatial light modulator with a large switch ratio. The transmission type liquid crystal terahertz spatial light modulator structurally comprises an upper-layer quartz substrate, an upper-layer metal structure, a liquid crystal layer, a lower-layer metal structure and a lower-layer quartz substrate in sequence from top to bottom, the upper-layer metal structure is adhered to the back surface of the upper-layer quartz substrate and is a four-opening square ring reverse structure array, and the lower-layer metal structure is adhered to the top surface of the lower-layer quartz substrate; and the liquid crystal layer is filled between the upper-layer metal structure and the lower-layer metal structure to form a metal-medium-metal structure. The electro-optical effect of the liquid crystal is utilized, the FPGA is communicated with the electrodes corresponding to the metal structures, voltage is applied between the upper-layer metal structure and the lower-layer metal structure, the effective dielectric constant of the liquid crystal can be changed by adjusting the voltage, and therefore on-off of terahertz waves is achieved. And the upper computer controls the FPGA to output voltage through an instruction so as to realize programmable regulation and control of the device.