443 results about "Logical operations" patented technology

The invention relates to the technical field of data exchange, in particular to a data exchange system of a nested tag structure, which comprises a data carrier adaptation module, a structure analysis module, a field mapping module, a logic driving module and a script generation module. According to the method, carrier identifiers are generated through comparison of MIME types, file header features are positioned through pattern matching, the recognition accuracy and adaptability are improved, a nesting relation is calculated through depth-first traversal of file paths, node sequences are generated through analysis in combination with a DOM tree, the label analysis efficiency is optimized, and a mapping table is generated through algorithm matching of field identifiers and database codes; the method comprises the following steps: dynamically constructing a field mapping relation, reducing manual configuration, constructing a decision matrix based on a mapping table, executing logical operation to generate a status bit and triggering a threshold write-in instruction, enhancing strategy dynamic adjustment capability, reducing semantic ambiguity through multi-algorithm collaboration and a dynamic decision mechanism, improving data exchange robustness, and supporting real-time state response. And the transmission timeliness of the industrial Internet of Things is ensured.

The invention discloses a processor, a chip product, computer equipment and a tensor processing method, and relates to the technical field of processors. A first tensor having a plurality of elements arranged according to a first arrangement order is stored in the first storage unit; the tensor storage engine is used for reading the plurality of elements from the first storage unit to the second storage unit according to a second arrangement sequence to obtain a rearranged tensor; the tensor calculation engine is used for executing logical operation on the rearranged tensor to obtain an operation result; the format conversion unit is used for converting the data format of each element in the operation result into a target data format to obtain an operation result after format conversion, and storing the operation result after format conversion into a third storage unit, the operation result after format conversion comprises the operation results of the multiple elements, and the third storage unit is used for storing the operation results after format conversion. A third arrangement sequence of the operation results of the plurality of elements in the third storage unit is the same as the first arrangement sequence. The development cost of the processor can be reduced.

The present disclosure relates to a data processing method, a processor, a chip, and an electronic device. The method comprises: on the basis of an obtained control instruction, a control logic unit sequentially reads, from a memory to a dot product unit array, loop tiling data of data to be processed; the dot product unit array performs multiply-accumulate operation on the loop tiling data of the data to be processed that is received each time, and determines a loop tiling result of the data to be processed that is received each time; and on the basis of a plurality of loop tiling results obtained from the dot product unit array, the control logic unit determines a logic operation result of the data to be processed. The embodiments of the present disclosure can convert, into the reading and logic operation of multiple pieces of loop tiling data of the data to be processed, the reading and logic operation of the data to be processed, so that data with larger size can be processed under the condition that the hardware resources of the processor are not changed, and the pressure on the storage bandwidth is reduced.

The invention discloses a processor, a chip product, computer equipment and a tensor calculation method, and relates to the technical field of processors. A first tensor is stored in a first storage unit of the processor; a plurality of scaling factors corresponding to the first tensor are stored in a second storage unit of the processor, the scaling factor set comprises a plurality of scaling factors, each scaling factor corresponds to one sub-block in the first tensor, each sub-block comprises at least one element in the first tensor, and each sub-block comprises at least one element in the first tensor; the scaling factor is used for adjusting the dynamic range of each element in the same sub-block; a tensor calculation engine of the processor is used for reading a first tensor from the first storage unit and reading a scaling factor set from the second storage unit; and for any sub-block in the first tensor, executing logical operation on elements in the sub-block according to the scale factor corresponding to the sub-block to obtain an operation result. According to the method and the device, the tensor calculation engine can realize accurate operation of the low-precision tensor through the scale factor of the sub-block granularity.

The invention discloses an all-optical logic operation system and operation method based on a metasurface device, and mainly solves the technical problems that an existing optical logic gate is high in system complexity, not visual enough in judgment result, high in recognition difficulty, poor in practicability and the like. The logic operation system comprises a polaroid, an object plane, a metasurface device and a detector which are arranged in sequence. The polarizer is used for adjusting the polarization direction of incident light; a plurality of transparent target areas with different shapes are arranged on the object plane and are used for placing corresponding target images; the centers of all the target areas are uniformly distributed on a circle with the center of the object plane as the circle center and d as the radius; incident light reaches the metasurface device after passing through the polaroid and a target image on the object plane, optical logic operation is carried out through the metasurface device, and then the incident light is output to the detector for imaging. The invention has the advantages of simple structure, quick function switching, miniaturization, high integration and the like.

The invention relates to the technical field of PLC control, in particular to a B / S architecture-based digital twin virtual debugging system and method for a transmission line. The system comprises a three-layer B / S (Browser / Server) architecture consisting of a PLC (Programmable Logic Controller) simulation layer, a business logic layer and a three-dimensional visualization layer, the PLC simulation layer is used for operating a PLC program to obtain a feedback signal of the controlled equipment, simulating the control logic of the PLC to the controlled equipment based on the feedback signal, and sending a control signal to the service logic layer; the business logic layer is used for acquiring the control signal and carrying out business logic operation based on the control signal and the feedback signal so as to calculate and simulate the movement of the controlled equipment and obtain real-time position data; and the three-dimensional visualization layer is used for displaying the operation state of the controlled equipment based on a pre-constructed virtual model of the controlled equipment and the real-time position data so as to display the operation result of the PLC program, generating a feedback signal based on a virtual sensor on the virtual model of the controlled equipment, and sending the feedback signal to the business logic layer.

The invention provides an intelligent door and window control method and system, and the method comprises the steps: S1, obtaining multi-source environment data; s2, inputting the multi-source environment data into a fuzzification module, and converting the multi-source environment data into a fuzzy variable through a preset ambiguity function; s3, dynamically generating an environment parameter weight vector according to the real-time scene parameters; s4, inputting the fuzzy variable and the environmental parameter weight vector into a fuzzy inference engine, executing logical operation of a fuzzy rule base, and outputting comprehensive evaluation values of window opening suitability, window closing urgency and shading demand; and S5, generating a final control instruction through a defuzzification strategy, and executing the final control instruction. According to the method, the problem of frequent invalid operation caused by fluctuation of the environmental parameters near the boundary value is solved, the environmental parameter weight vector is dynamically generated based on the time parameters, the user preset mode and the meteorological data confidence factor, adaptation to seasons, time periods, user states and other scenes is achieved, and decision logic can be flexibly adjusted according to actual requirements; and a contradictory decision under a traditional fixed rule is avoided.

The invention provides an arithmetic logic unit parallel processing system and method and electronic equipment, and relates to the field of chip architecture processing, and the arithmetic logic unit parallel processing system comprises an instruction transmitting unit, a write-back unit and a plurality of ALU groups containing a plurality of arithmetic logic units; wherein the instruction transmitting unit is respectively connected with the input end of each ALU group; the output end of each ALU group is connected with the write-back unit; the input end of each ALU group is respectively connected with the input ends of all the arithmetic logic units in the current ALU group; the output end of each ALU group is respectively connected with the output ends of all the arithmetic logic units in the current ALU group; according to the scheme, the reduction instruction and the vector arithmetic logic operation can be realized by using the same arithmetic logic operation component, the number and the area of the vector arithmetic logic operation component are reduced, and the utilization rate of the vector arithmetic logic operation component is improved.

A single-instruction multi-thread processor micro-architecture device oriented to neural network parallel scheduling comprises a front-end instruction fetching module, an instruction cache module, a decoding module, an arithmetic logic operation unit, a multiplication and division module, a memory access unit and a data cache module, and the micro-architecture device allocates a unique thread number for each thread. Threads are organized into thread groups, and in each period, the fair alternate arbiter selects an instruction from an instruction buffer of the thread group and sends the instruction to a subsequent decoding stage. The micro-architecture not only solves challenges faced by end-side equipment when processing high-performance calculation requirements such as neural network reasoning, but also provides an effective solution capable of reducing energy consumption and improving calculation efficiency through an innovative architecture design. The method is of great significance in promoting development of end-side AI application.

This electronic circuit implements calculation operations each providing a binary output, and comprises word lines; pairs of complementary bit lines; source lines; a set of memory cells organized according to a matrix including rows and columns, the memory cells of a same row being selectable by a word line, the memory cells of a same column being connected to a pair of complementary bit lines and to a source line; and a reading device implemented during each calculation operation. Each memory cell comprises two memristors and two switches.The reading device includes:a logic unit for each column, each being configured to perform a logic operation presenting a switching between a low value and a high value depending solely on the value of the input of the logic unit which is connected to a respective source line during said calculation operation,a module for converting a number of high or low values at the output of the logic units into an intermediate value dependent on said number of high / low values, the latter being an electrical value the variation of which over time depends on a time constant which is a function of said number of high / low values, anda comparison module for comparing the intermediate value with a reference value and for outputting a single-bit digital signal dependent on the comparison.

Examples are described for dynamically encrypting and / or decrypting a file formed of multiple blocks of ordered data. In one example, a method of dynamically encrypting a file to enable partial decryption of the file includes generating, using a secret key and one or more initialization vectors, a keystream for the multiple blocks of ordered data, encrypting the multiple blocks of ordered data of the file by performing a logical operation of the keystream with the multiple blocks of ordered data in a one-to-one correspondence, and building a file index of the file to identify location information of the multiple blocks of ordered data. The method may further include dynamically decrypting at least a portion of the file by decrypting at least one selected block of encrypted data of the file using a portion of the keystream, the portion of the keystream corresponding to the at least one selected block.

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

The invention relates to the technical field of static storage, and particularly discloses an anti-radiation SRAM (Static Random Access Memory) unit, array and storage and calculation integrated system, which realizes the balance of anti-radiation capability and engineering feasibility through the collaborative design of a circuit and the system. A polarity-reinforced RHCIM-16T unit structure is adopted as the core, and directional conductive constraint is introduced, so that complex multi-node flipping is simplified into a single'lock 0 'error, and the error rate is reduced from the source. On the basis, a lightweight single error correction code is combined to form an efficient fault-tolerant mechanism of circuit simplification and SEC coding. According to the scheme, through the design of splitting word lines and the like, logic operations such as AND and NOR are compatible, and stable execution of the storage and calculation integrated function in a radiation environment is ensured. Simulation and experiment results show that the robustness and the expandability of the memory array in the radiation environment can be remarkably enhanced while the relatively low area and the relatively low power consumption overhead are maintained.

The invention discloses a service application access method, device and system, a readable storage medium and a product, a target user sends an operation request to the rear end of a target service application through the front end of the target service application deployed on a cloud platform, and the operation request carries a first token, a second token and an operation instruction; the first token is a platform identity authentication token fed back to the target user by the cloud platform, and the second token is an application identity authentication token fed back to the target user by the target service application and carries user information synchronized by the cloud platform; the gateway of the cloud platform intercepts the operation request, and forwards the operation request to the rear end of the target service application after the first token is successfully authenticated; and the back end of the target service application executes a corresponding logic operation based on the operation instruction and the user information after successfully authenticating the second token.

According to the branch prediction method provided by the invention, the branch prediction result is obtained by indexing the historical branch prediction instructions in the branch prediction condition table, and the relevance between the historical branch prediction instructions can be well utilized, so that the success rate of branch prediction is greatly improved; meanwhile, the last four bits of the branch prediction instruction and values in the global historical register are subjected to logical operation, an operation value is obtained and then indexed, and the influence of the alias of the branch prediction instruction on branch prediction can be reduced; meanwhile, when the branch prediction result is skipping and the operation code of the branch prediction result is matched with the operation code of the indexed historical branch prediction instruction, the branch prediction result is trusted, so that the branch prediction accuracy is further improved; and moreover, the jump address is obtained by adopting a direct operation method, so that the area overhead and the delay caused by storing a large number of branch addresses by the BTB (Branch Target Buffer) can be saved.

Performing fused shift and logical operations in processor-based devices is disclosed herein. In some aspects, a processor device comprises an instruction processing circuit that includes a shift / logical circuit. The instruction processing circuit is configured to detect, in an instruction stream, one or more instructions to perform a shift operation and a subsequent logical operation. In response to detecting the one or more instructions, the instruction processing circuit is further configured to use the shift / logical circuit to perform the shift operation and the logical operation in a single processor clock cycle.

According to an embodiment of the present disclosure, a processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading data to be processed. The target operand specifies a target storage location in the memory for writing a processing result. The processor also includes an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result to a target storage location in the memory. In this way, the efficiency of vector calculations can be improved.

The invention provides a control device, and the device comprises a switch module which is used for setting in a three-second wiring mode, so as to carry out the electric energy transmission; the control module is used for collecting and receiving position state information of components in the switch module and performing logical operation according to preset locking logic; the output module is used for outputting an operation allowing signal according to the logic operation result. The position state information of the components in the switch module is collected and received through the control module, logic operation is carried out according to preset locking logic, the locking logic can be flexibly adjusted according to actual working conditions so as to meet different operation requirements, and abnormal conditions can be found and processed in time. The output module outputs an operation allowing signal according to a logical operation result, and ensures that opening and closing operations of components are allowed only under a safe condition, so that the automation and intelligence level of an electrical main wiring system is improved, the possibility of manual misoperation is reduced, various changes can be responded more quickly, and the operation efficiency is improved.

According to a preferred aspect of the invention, provided is an information processing apparatus including a processor and a storage device. A penalty coefficient setting unit is implemented by the processor and the storage device using a solution finding function for obtaining a solution of a combinatorial optimization problem using a cost function and a constraint condition. The penalty coefficient setting unit sets a penalty function and a penalty coefficient based on the constraint condition related to a logical operation imposed between two variables of the cost function and a value of a model coefficient of the cost function such that the solution of the combinatorial optimization problem satisfies the constraint condition, and searches for the solution of the combinatorial optimization problem based on the penalty function and the penalty coefficient.

According to the bit weight amplitude weight quantizer and the quantization discretization method, the maximum amplitude of input continuous simulation information is discretely divided into a plurality of amplitude paragraphs of a content interval GS, the amplitude paragraphs are associated with a carry system, the amplitude of the input continuous simulation information is discretely divided into a plurality of paragraphs through a number of carry systems, and the amplitude of the input continuous simulation information is divided into a plurality of paragraphs. If a decimal system exists, the amplitude of the continuous analog information is discretized into ten paragraphs, the discretized paragraphs are converted into thermometer coding information through a comparator, and then the thermometer coding information is converted into bit weight information through XOR and XNOR logical operation; the value of the bit weight in the bit weight information is generated by comparing the binary states 0 and 1 on the node, one state on the unique node is compared with different states on other nodes to indicate that the node has the weight, and the position number of the node with the weight is used for indicating the bit weight of all the nodes in the bracket.

The invention discloses a floating point arithmetic unit, a floating point processing device and method, a chip and electronic equipment, and the floating point arithmetic unit comprises a logic processing module which is used for carrying out the logic operation of a to-be-processed operand inputted into the floating point arithmetic unit, and obtaining an operation result; the delay control module is used for controlling the delay between the input logic processing module of the operands to be processed and the input floating point arithmetic unit; and / or controlling the delay between the operation result output by the logic processing module and the operation result output by the floating point operation unit. Therefore, the delay of the floating point operation can be effectively balanced, the operation efficiency is improved, and the overall performance of the floating point operation is improved.

The invention relates to the technical field of water conservancy project automation and industrial control, in particular to a water conservancy equipment collaborative operation system based on an industrial control system, which comprises a programmable input mapping and logic matching unit, a data processing unit and a data processing unit, the system carries out binary bit mode matching on the operation result and the feature data block in the memory; the logical operation and addressing unit is used for calculating control lag time and generating a structured digital control sequence data stack; the sequential control and instruction addressing unit is used for generating a cooperative control instruction set containing sequential logic; the output mapping and checking unit is used for reading real-time feedback, and if deviation exists, an interruption compensation program is triggered to correct an action curve of an executing mechanism; the storage rewriting and loop optimization unit is used for correcting transmission delay parameters of the model and realizing closed-loop optimization; according to the method, the problem of model distortion caused by physical property drift is solved, and stable full-life-cycle operation is ensured.

The present disclosure relates to the technical field of artificial intelligence algorithm hardware acceleration, and in particular to a Transformer accelerator architecture based on monolithic three-dimensional integration, comprising a silicon-based logic circuit, used for controlling a current flowing direction of Transformer for logic operation; an RRAM-CIM array, used for executing a linear transformation operation; and a CFET 2T0C-CIM array, used for executing a matrix multiplication operation.

The present application belongs to the field of data processing. Disclosed are a user data query method and apparatus, and a device and a storage medium. The method comprises: receiving a query request, wherein the query request comprises computation logic information; on the basis of a target bitmap identifier indicated by the computation logic information, determining a target bucket identifier in a target storage space, wherein the target storage space stores a bitmap identifier, a bucket identifier and bucket content, which have correspondences, the bitmap identifier is used for representing the classification of user data, and the bucket identifier and the bucket content are used for performing restoration to obtain the user data; and on the basis of a logic operation indicated by the computation logic information, processing bucket content, which corresponds to the target bucket identifier, in the target storage space, so as to obtain a query result and feed back same.

According to one aspect, the subject matter of the present description is a method for allocating logical qubits of a quantum algorithm to physical qubits of a quantum processor arranged according to a given architecture, the method including: establishing, from the architecture, a connectivity graph; the establishing, from the quantum algorithm, a graph of the logical operations; assigning a weight to each logical qubit; ranking the logical qubits according to the weight; allocating a first logical qubit chosen according to the weight, to a first physical qubit of the quantum register; iteratively allocating the logical qubits remaining to be allocated, including calculating a score; and reproducing the iterative allocation procedure until allocating the last logical qubit remaining to be allocated, thus resulting in obtaining a configuration for allocating logical qubits of the quantum algorithm to physical qubits of the quantum processor.

The invention relates to the technical field of computer information processing, space structure modeling and system modeling, in particular to an entanglement space calculation method suitable for complex structure relation modeling and state-driven logic operation and an implementation device of the entanglement space calculation method. Specifically, the entanglement space is an abstract data space containing nodes, constraints and channels, the nodes are state units, the constraints define logic relations among the nodes, the channels are state transmission paths, and a multi-level structure can be formed through nesting or coupling. The method comprises the steps of defining a basic unit, constructing an entanglement space, executing state mapping operation and unwrapping operation, and outputting a result. The device comprises a unit definition module, a space construction module, an operation execution module and an output module, and supports constraint conflict detection and state record tracing. According to the method, the problem that a traditional model is difficult to process complex nesting and multiple dependency relationships is solved, unified modeling and dynamic operation are achieved, the method is adaptive to multiple scenes, and the modeling and operation efficiency of a complex system is improved.

The invention provides a programmable logic controller, a control method, a storage medium and a program product. A user program is efficiently switched while operating a PLC. The PLC may include a processor to repeatedly execute a user program-based logical operation and a memory to store a value of a variable accessed according to the user program executed by the processor. An instruction to switch to a second user program that is an updated version of the first user program is issued while the processor is executing the first user program. Variable information is created for identifying a variable to be maintained and a variable to be changed by updating from a first user program to a second user program. An address storing a value of a variable to be maintained is maintained, and an address storing a value of a variable to be changed is allocated at a discontinuity of a logical operation in a case where the logical operation is stopped.

The application relates to the technical field of PLC control, in particular to a conveying line digital twin virtual debugging system and method based on a B / S architecture. The system comprises a three-layer B / S architecture composed of a PLC simulation layer, a business logic layer and a three-dimensional visualization layer. The PLC simulation layer is used for running a PLC program to obtain feedback signals of controlled equipment, simulating the control logic of the PLC on the controlled equipment based on the feedback signals, and sending control signals to the business logic layer. The business logic layer is used for obtaining the control signals and performing business logic operation based on the control signals and the feedback signals to calculate the movement of the simulated controlled equipment and obtain real-time position data. The three-dimensional visualization layer is used for displaying the running state of the controlled equipment based on a pre-constructed virtual model of the controlled equipment and the real-time position data to show the running result of the PLC program, and generating feedback signals based on virtual sensors on the virtual model of the controlled equipment and sending the feedback signals to the business logic layer.

Disclosed is a method for a logical operation performed by a quantum computing device (100, Figure 1), which may include: placing a data patch (320) in which information is stored and computed, and a first ancilla patch (340) which is consumed during a logical operation at a predetermined first interval; placing a first logical ancilla qubit (350) between the data patch and the first ancilla patch; placing a second logical ancilla qubit (360) to have a predetermined distance from one side of the first ancilla patch; and performing a joint measurement utilizing the data patch and the first ancilla patch.

The invention relates to the technical field of data encryption, in particular to an AES (Advanced Encryption Standard) box optimization method based on a GF ((22) 4) composite domain, which comprises the following steps of: firstly, proposing a multiplication inverse structure general formula based on the composite domain GF ((22) 4), and reducing the resource consumption of the GF (28) domain under the condition of not increasing logical operation; secondly, proposing a multiplication inverse structure of the composite domain GF ((22) 4) with an optimal structure, and optimizing a general formula of the multiplication inverse structure of the composite domain GF ((22) 4) based on a primitive polynomial, DDBT and DACSE to obtain a multiplication inverse structure with an optimal area delay; finally, an AES S box structure based on GF ((22) 4) is provided, and the area and delay of the AES S box structure are optimal.