198 results about "Logical operations" patented technology

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

The invention relates to the technical field of static storage, and particularly discloses an anti-radiation SRAM (Static Random Access Memory) unit, array and storage and calculation integrated system, which realizes the balance of anti-radiation capability and engineering feasibility through the collaborative design of a circuit and the system. A polarity-reinforced RHCIM-16T unit structure is adopted as the core, and directional conductive constraint is introduced, so that complex multi-node flipping is simplified into a single'lock 0 'error, and the error rate is reduced from the source. On the basis, a lightweight single error correction code is combined to form an efficient fault-tolerant mechanism of circuit simplification and SEC coding. According to the scheme, through the design of splitting word lines and the like, logic operations such as AND and NOR are compatible, and stable execution of the storage and calculation integrated function in a radiation environment is ensured. Simulation and experiment results show that the robustness and the expandability of the memory array in the radiation environment can be remarkably enhanced while the relatively low area and the relatively low power consumption overhead are maintained.

According to the bit weight amplitude weight quantizer and the quantization discretization method, the maximum amplitude of input continuous simulation information is discretely divided into a plurality of amplitude paragraphs of a content interval GS, the amplitude paragraphs are associated with a carry system, the amplitude of the input continuous simulation information is discretely divided into a plurality of paragraphs through a number of carry systems, and the amplitude of the input continuous simulation information is divided into a plurality of paragraphs. If a decimal system exists, the amplitude of the continuous analog information is discretized into ten paragraphs, the discretized paragraphs are converted into thermometer coding information through a comparator, and then the thermometer coding information is converted into bit weight information through XOR and XNOR logical operation; the value of the bit weight in the bit weight information is generated by comparing the binary states 0 and 1 on the node, one state on the unique node is compared with different states on other nodes to indicate that the node has the weight, and the position number of the node with the weight is used for indicating the bit weight of all the nodes in the bracket.

The invention discloses a floating point arithmetic unit, a floating point processing device and method, a chip and electronic equipment, and the floating point arithmetic unit comprises a logic processing module which is used for carrying out the logic operation of a to-be-processed operand inputted into the floating point arithmetic unit, and obtaining an operation result; the delay control module is used for controlling the delay between the input logic processing module of the operands to be processed and the input floating point arithmetic unit; and / or controlling the delay between the operation result output by the logic processing module and the operation result output by the floating point operation unit. Therefore, the delay of the floating point operation can be effectively balanced, the operation efficiency is improved, and the overall performance of the floating point operation is improved.

The invention relates to the technical field of water conservancy project automation and industrial control, in particular to a water conservancy equipment collaborative operation system based on an industrial control system, which comprises a programmable input mapping and logic matching unit, a data processing unit and a data processing unit, the system carries out binary bit mode matching on the operation result and the feature data block in the memory; the logical operation and addressing unit is used for calculating control lag time and generating a structured digital control sequence data stack; the sequential control and instruction addressing unit is used for generating a cooperative control instruction set containing sequential logic; the output mapping and checking unit is used for reading real-time feedback, and if deviation exists, an interruption compensation program is triggered to correct an action curve of an executing mechanism; the storage rewriting and loop optimization unit is used for correcting transmission delay parameters of the model and realizing closed-loop optimization; according to the method, the problem of model distortion caused by physical property drift is solved, and stable full-life-cycle operation is ensured.

According to one aspect, the subject matter of the present description is a method for allocating logical qubits of a quantum algorithm to physical qubits of a quantum processor arranged according to a given architecture, the method including: establishing, from the architecture, a connectivity graph; the establishing, from the quantum algorithm, a graph of the logical operations; assigning a weight to each logical qubit; ranking the logical qubits according to the weight; allocating a first logical qubit chosen according to the weight, to a first physical qubit of the quantum register; iteratively allocating the logical qubits remaining to be allocated, including calculating a score; and reproducing the iterative allocation procedure until allocating the last logical qubit remaining to be allocated, thus resulting in obtaining a configuration for allocating logical qubits of the quantum algorithm to physical qubits of the quantum processor.

The invention relates to the technical field of data encryption, in particular to an AES (Advanced Encryption Standard) box optimization method based on a GF ((22) 4) composite domain, which comprises the following steps of: firstly, proposing a multiplication inverse structure general formula based on the composite domain GF ((22) 4), and reducing the resource consumption of the GF (28) domain under the condition of not increasing logical operation; secondly, proposing a multiplication inverse structure of the composite domain GF ((22) 4) with an optimal structure, and optimizing a general formula of the multiplication inverse structure of the composite domain GF ((22) 4) based on a primitive polynomial, DDBT and DACSE to obtain a multiplication inverse structure with an optimal area delay; finally, an AES S box structure based on GF ((22) 4) is provided, and the area and delay of the AES S box structure are optimal.

The invention relates to a tone mapping method and device, electronic equipment and a storage medium. According to the method, a first logical operation unit, a second logical operation unit, a third logical operation unit and a lookup table of a field programmable logic gate array are matched with one another. Specifically, by inputting the Y channel median value into the lookup table, the Y channel value adjustment coefficient can be directly obtained, and exponential operation between the Y channel median value and the Y channel value adjustment coefficient does not need to be carried out. By inputting the ratio of the Y channel value of each pixel stretched to the full domain to the median value of the Y channel of each pixel stretched to the full domain into the lookup table, the compression value of the Y channel can be directly obtained, and exponential operation of the ratio and the compression value of the Y channel is not needed, so that the data processing efficiency is improved, and the operation resources are saved.

This application relates to the field of communication technology and discloses a hardware logic-based flow control circuit, chip, and flow control method. The flow control circuit is integrated inside the chip and is used to control multiple controlled modules. The flow control circuit includes: a bus interface for controlling multiple controlled modules or acquiring the status of multiple controlled modules; an instruction sequence execution controller for storing multiple sets of instruction sequences, each set of instruction sequences corresponding to a status index; the instruction sequence execution controller for executing the corresponding instruction sequence according to the input current status index, performing read / write operations or logical operations through the bus interface, and outputting an execution completion signal and a calculation result flag after all instructions in the corresponding instruction sequence have been executed; and a flow control state machine for outputting the current status index to the instruction sequence execution controller and receiving the execution completion signal and the calculation result flag, thereby controlling the flow while ensuring the robustness of the system.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

The invention discloses a task resource allocation method and device, equipment and a storage medium. The task resource allocation method comprises the steps that in response to a task processing request, resource pool matching is conducted according to labels carried by a task and matching rules of all resource pools, and the matching rules are set based on the labels and support logical operation among the multiple labels; and according to the task type and the algorithm requirement of the task, allocating resources in a resource pool matched with the task to process the task. In this way, simplified allocation of algorithm task resources can be achieved.

A method of performing logical qubit operations (17, 19, 25, 27, 29, 31) on an ensemble of logical qubits (1a-d), each logical qubit having a plurality of physical qubits (3), the method comprising: performing one or more rounds of single qubit logical operations (17, 19, 27, 29, 31) on each of a set of the logical qubits (1a-d); and performing a multi-qubit logical operation (25) using at least two of the set of logical qubits (1a-d), wherein the logical qubits (1a-d) involved in the multi-qubit logical operation (25) are synchronised prior to the multi-qubit logical operation (25) by one or more of: providing periods of physical idle time (21, 35, 37) between rounds of single qubit logical operations (17, 19, 27, 29, 31) performed on one or more of the logical qubits (1a-d) involved in the multi-qubit logical operation (25); and performing different numbers of rounds of single qubit logical operations (17, 19, 27, 29, 31) on the logical qubits (1a-15 d) involved in the multi-qubit logical operation (25) in a fixed period of time.

The invention relates to a multi-thread dynamic task scheduling circuit, a computing chip and a computing system, which are integrated in a parallel computing chip, and comprise a plurality of thread management units which are respectively used for storing context information of each task thread, reading an instruction stream from a memory through an internal instruction reading and transmitting unit, and decoding and transmitting the instruction stream; the arithmetic logic unit is used for executing arithmetic and logic operation instructions of the thread management unit so as to realize dynamic parameter derivation during operation; the task distribution unit is used for arbitrating the task configuration information transmitted by the plurality of thread management units and distributing the task configuration information to each processing unit in the chip; and the synchronization unit is used for synchronizing primitives through hardware so as to realize synchronization among the plurality of thread management units and synchronization between the thread management units and the processing unit. Each thread is programmable and adapts to complex scenes such as dynamic image sizes and dynamic calculation processes.

The decimal quantization logic gate is a hardware logic operation design based on quantization logic, and the main design idea of the decimal quantization logic gate is that a linear multi-valued logic operation is used as a logic operation part to execute logic operations such as AND (small), OR (large) and NOT (complement); the multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like, and a multi-valued logic operation and multi-valued quantization'quantization logic 'circuit is formed by combining the structures of multi-valued quantization and logic operation together, and a multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like. The logic circuit always executes'quantization 'and'logic operation', so that the logic circuit is called'quantization logic '. The design of all previous'multi-valued logic gate 'and'two-valued logic gate' circuits is as follows: 'logical operation '(AND, OR, NOT) is firstly carried out, and then'quantization' (threshold detection) is carried out to set'fault-tolerant intervals'. Therefore, the quantization logic is the most original thought of logic hardware design.

This invention belongs to the field of power grid fault diagnosis technology and discloses a power grid fault diagnosis method and system based on differential evolutionary logic operations. The method includes: collecting the action information of protection devices and circuit breakers in the power system; filtering out a set of candidate elements that have experienced faults based on preset association rules between faulty elements and protection / circuit breaker actions; establishing a 0-1 integer programming model based on the determined protection action information, circuit breaker action information, and candidate element set; and solving the 0-1 integer programming model using an improved differential evolutionary algorithm based on logic operations to determine the fault state of the candidate elements. This invention directly encodes individuals using binary, eliminating the need for floating-point to binary conversion. It also constructs a binary mutation operator and an improved crossover operator based on logic operations and employs adaptive parameter adjustment to balance the population diversity and search efficiency of the algorithm.

The application relates to the technical field of semiconductors, and provides a logic operation method and device based on a ferroelectric transistor and electronic equipment, the logic operation method based on the ferroelectric transistor comprises the following steps: obtaining an operation instruction to be executed, the operation instruction comprising input variables and the type of the logic operation to be executed; determining an assignment relationship between the input variables and logic variables of a target logic gate according to the working principle of the target logic gate and the type of the logic operation to be executed, wherein the target logic gate comprises at least one ferroelectric transistor; assigning the values of the input variables to the logic variables according to the assignment relationship; controlling the ferroelectric transistor to execute the logic operation according to the logic variables, and storing the result of the logic operation in situ by using the polarization state of the ferroelectric transistor. The method realizes the integration of storage and calculation based on the Boolean logic gate of the ferroelectric transistor, breaks through the limitations of the storage wall and the power consumption wall, and improves the flexibility of the Boolean logic gate of the ferroelectric transistor when performing the logic operation.

The application discloses a kind of complete non-volatile Boolean logic circuit based on 1T1R array and control method thereof, belong to microelectronic device technical field, for the logic value P and / or logic value Q of input is carried out logic operation;Wherein, the input resistance state of memristor M1 is determined by logic input Q, input voltage is fixed as-V0, the input voltage of memristor M2 is fixed as V1, the input voltage C on word line WL is determined by logic operation type and logic value Q, P;The input voltage D on source control end is determined by logic operation type, logic value P and voltage C, the resistance state of memristor M2 is as the output of calculation result;The application fully utilizes the switching characteristic of transistor in 1T1R structure on logic algorithm, by dynamically configuring the input voltage on word line WL and source control end, i.e., complete Boolean logic function can be realized in two steps, and non-volatile Boolean logic operation efficiency can be improved with less operation steps and fixed circuit topology.

The invention provides a neural network calculation acceleration method and system, and the method comprises the steps: extracting an amplitude bit of input vector data and an amplitude bit of weight vector data, and generating a zero tag through logic operation; the zero label represents whether the product of the input vector data and the weight vector data is zero or not; dynamically aggregating the non-zero products according to the zero label to form an aggregated product; and dynamically adjusting the calculation scale of the adder tree according to the number of non-zero products in the aggregated products, and only performing accumulation operation on the non-zero products. According to the method, invalid calculation can be effectively reduced, the calculation efficiency and the utilization efficiency of hardware resources are improved, and the method is suitable for accelerated calculation of various neural network models.

The application belongs to the field of databases and provides a code conversion method, device, equipment and medium based on statement pair equivalent replacement, which comprises the following steps: obtaining a to-be-converted statement including a first operator and a first logical statement in PLSQL code to be converted, the first operator being used for performing a logical NOT operation, and the logical operation result of the first logical statement being Null; obtaining a target logical operation result of the to-be-converted statement; removing the first operator and converting the first logical statement into a second logical statement with a logical operation result of the target logical operation result; and replacing the second logical statement with the to-be-converted statement to convert the obtained target PLSQL code into target Java code. According to the technical scheme of the embodiment, when the logical operation result of the first logical statement in the to-be-converted statement is Null, the to-be-converted statement can be replaced by the second logical statement in a pair-equivalent manner, so that the operation logic remains unchanged after being converted into a Java statement and the normal operation of the system is ensured.

The present invention provides a method for mitigating errors in quantum circuits, including error-corrected quantum logic operations, and a storage medium. [Solution] The method includes providing a set of quantum error relaxation protocols, each comprising at least two quantum error relaxation protocols. At least one error-corrected quantum logic operation is performed, and at least one syndrome associated with this error-corrected quantum logic operation is measured to obtain a syndrome measurement. The execution follows at least one selected quantum error relaxation protocol from the set, based on the syndrome measurement.

The invention discloses a logical operation method based on depth-first traversal and stack recursion, and belongs to the technical field of computer logical operation and data processing. The method aims at solving the problems that in the prior art, when a complex nested logic expression is processed, operator priority judgment is complex, short circuit evaluation is difficult to achieve, and code maintainability is poor. The core of the method is that firstly, a nested logic expression to be calculated is abstracted into a tree-shaped or nested array data structure; secondly, a depth-first traversal algorithm is adopted to conduct recursive scanning on the data structure, and in the traversal process, encountered logic operators and basic judgment conditions (calculation factors) or intermediate calculation results of sub-expressions are sequentially pressed into a main stack according to the traversal sequence; when traversal of one sub-expression is completed, an actuator module is automatically triggered; and the executor module pops up a logic operator of the current action range from the main stack.

The invention provides a performance monitoring method for an AI server, a medium and a computer program product. The method comprises the following steps: in a deep learning framework layer, in response to a received instruction for executing a logic operation, generating an associated ID for identifying the logic operation, analyzing the logic operation into a runtime API call, and submitting the runtime API call and the associated ID to a runtime layer; in the runtime layer, in response to the received runtime API call and the associated ID, generating a corresponding hardware task and a hardware task ID for identifying the hardware task, recording a mapping relationship between the associated ID and the hardware task ID, and submitting the hardware task and the hardware task ID to the hardware equipment layer; the hardware task is executed on the hardware equipment layer, hardware performance data associated with execution of the hardware task are recorded, and the hardware performance data are bound with the hardware task ID of the hardware task associated with the hardware performance data.

The application discloses a kind of smart contract vulnerability detection method and system based on meta operation.First, smart contract is converted into intermediate representation, and the basic matching operation on the intermediate representation is defined as meta operation, as the basic detection logic unit of contract code vulnerability detection;Second, the detection rule of contract vulnerability is expressed as the logical operation expression of a group of meta operation, and the vulnerability detection script file is formed.The detection code of all meta operations is implemented in the contract vulnerability detection system, and the analysis execution code of contract vulnerability detection rule;Finally, the system judges whether the smart contract to be measured exists certain vulnerability characteristics by parsing vulnerability detection script file and executing matching operation.The application is suitable for the detection of different versions of smart contract vulnerability, and the reuse of meta operation reduces a lot of repeated vulnerability detection code writing work, and improves the scalability of contract vulnerability detection tool.

The invention relates to a method and device for encoding multiple numerical values, equipment and a medium. Comprising the following steps: acquiring a plurality of initial numerical values which are the same in numerical value type; performing bit expansion processing on each initial numerical value in the plurality of initial numerical values according to a preset multiple to obtain a plurality of first intermediate numerical values; and executing logical operation on the plurality of first intermediate numerical values to obtain a target numerical value. It can be seen that in the method, a high-low bit combined storage mode is not adopted, bit expansion processing is carried out on each initial numerical value, and it is ensured that the binary length of each first intermediate numerical value can meet the requirement for follow-up integration of all initial numerical values. And fusing the plurality of first intermediate values into a complete target value through logical operation. The mechanism fundamentally avoids the scene that in a traditional scheme, a low-bit segment needs to be filled with a large number of zero values to meet the storage format, the technical problem that in the traditional scheme, data storage efficiency is low is effectively solved, and finally the expected storage saving target can be achieved.

The embodiment of the invention provides a method for performing logical operation based on a memory and the memory. Wherein the logic operation comprises AND logic operation or OR logic operation, and when the AND logic operation or the OR logic operation is executed, the method comprises the following steps: step S11, pre-charging a first bit line and a second bit line to a reference voltage; s12, performing charge sharing on the 3m first storage units and the first bit line, and performing charge sharing on the 3n second storage units and the second bit line at the same time, so as to form a first voltage difference on the first bit line and the second bit line; wherein m + n > = 2, m is a positive integer, and n is a non-negative integer; and step S13, amplifying the first voltage difference on the first bit line and the second bit line through a sense amplifier so as to obtain the AND logic operation or the target result of the logic operation on the first bit line or the second bit line.

This bidirectional logic element is provided with: a function / inverse function control unit; a forward input unit; a forward information transmission unit; a reverse input unit; a reverse information transmission unit; a bidirectional function operation unit that performs a forward logical operation and also performs a reverse operation; a forward function transfer unit; and an inverse function transfer unit. The arithmetic device and the arithmetic method use the bidirectional logic element.

The application discloses a kind of data processing method and related equipment related to computer technology field, specifically related to a kind of data processing method and related equipment, the method includes: obtaining query request;Parsing condition limiting information, determine at least two query conditions and the Boolean logic relation between at least two query conditions corresponding to condition limiting information;At least two query conditions each query condition corresponding to query code is generated;Query code is used to carry out object query in high-efficiency compressed bitmap data table, obtain the first high-efficiency compressed bitmap of object set satisfying the corresponding query condition;According to the Boolean logic relation between at least two query conditions, the query code corresponding to each query condition in at least two query conditions is combined, and combined code is obtained;Combined code is used to carry out logical operation on the first high-efficiency compressed bitmap according to the Boolean logic relation between at least two query conditions, and obtain target high-efficiency compressed bitmap, the present scheme realizes block query, improves query efficiency.

The present embodiments provide a method for introducing a magic state in a quantum computer and a quantum computer therefor, the method comprising the steps of: constructing a logical qubit by using an error correction code of a heavy hexagonal structure that connects two data qubits and one syndrome qubit from both sides by introducing two or more flag qubits between four data qubits and one syndrome qubit; and performing a logical operation on the logical qubit, wherein the error correction code performs a magic state injection process that maps a magic state implemented in physical qubits to a logical state.

This invention relates to the field of computer data processing and data visualization technology, specifically a personalized report configuration platform system, comprising: a data virtualization module: establishing physical data source mapping and constructing atomic data pools; an indicator graph construction module: generating atomic indicator dependency graphs, storing logical operation relationships rather than calculation results; a context-aware module: capturing environmental parameters such as tenant roles and time windows; a dynamic compilation engine: injecting environmental parameters into the graph and instantiating and parsing logical nodes to generate structured query instructions; and a rendering and compositing module: executing instructions to obtain result data and mapping it to view components. This invention achieves dynamic instantiation of logic defined once in multiple places, avoiding hard-coding development and improving the maintainability and response speed of the system.