2121 results about "Logical operations" patented technology

A system for detecting and responding to an attack comprises a filter module, a node, a management module, and a test node. The filter module allows questionable messages to proceed. The node receives the questionable messages and maintains logical operations associated with the questionable messages within a restricted region. The management module resets the service node upon a network attack. The test node replays the node questionable messages to identify a new attack. A method of protecting against a network attack logs questionable messages and directs the questionable messages to a node. The method maintains logical operations associated with the questionable messages within a restricted region and identifies a network attack upon the node, which triggers an intrusion response. The intrusion response resets the node, replays the questionable messages within a test node to identify a new attack message, and adds the new attack message to the known attack messages.

A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.

A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

A nonvolatile memory device includes a memory cell array configured to comprise memory cells coupled by bit lines and word lines, a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group, and an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.

A method and apparatus for providing a programmable logic datapath that may be used in a field programmable device. According to one aspect of the invention, a programmable logic datapath is provided that includes a plurality of logic elements to perform various (Boolean) logic operations. The programmable logic datapath further includes circuitry to selectively route and select operand bits between the plurality of logic elements (operand bits is used hereinafter to refer to input bits, logic operation result bits, etc., that may be generated within the logic datapath). In one embodiment, by providing control bits concurrently with operand bits to routing and selection (e.g., multiplexing) circuitry, the programmable logic datapath of the invention can provide dynamic programmability to perform a number of logic operations on inputs of various lengths on a cycle-by-cycle basis.

A hierarchical arbitration method in which requests are grouped, using a logical OR operation for example, and provided to higher levels of the hierarchy. Then, grant signals from higher levels of the hierarchy are either propagated down through each level of the hierarchy where they are used to modify, using a logical AND operation for example, grant signals. Alternatively, grant signals from all higher levels of the hierarchy may be provided to a leaf layer of the hierarchy where they are all used to modify, using a logical AND operation for example, grant signals.

Techniques for discovering and/or advertising services are described herein. A first bitmask is received from a remote device over a wireless network, the first bitmask having one or more bits that have a predetermined logical value. Each bit represents a particular service provided by the remote device. A logical operation is performed between the first bitmask and a second bitmask locally generated within a local device, where the second bitmask represents a service being searched by the local device. It is determined whether the remote device is potentially capable of providing the service being searched by the local device based on a result of the logical operation.

A system and method for efficiently implementing a local or distributed file system is disclosed. The system may include a distributed virtual file system (“dVFS”) that utilizes a persistent intent log (“PIL”) to record transactions to be applied to the file system. The PIL is preferably implemented in stable storage, so that a logical operation may be considered complete as soon as the log record has been made stable. This allows the dVFS to continue immediately, without waiting for the operation to be applied to a local or real file system. The dVFS may further incorporate replication to one or more remote file systems as an integral facility.

An apparatus, method, and system for synchronicity independent, resource delegating, power and instruction optimizing processor is provided where instructions are delegated between various processing resources of the processor. An Integer Processing Unit (IPU) of the processor delegates complicated mathematical instructions to a Mathematical Processing Unit (MPU) of the processor. Furthermore, the processor puts underutilized processing resources to sleep thereby increasing power usage efficiency. A cache of the processor is also capable of accepting delegated operations from the IPU. As such, the cache performs various logical operations on delegated requests allowing it to lock and share memory without requiring extra processing cycles by the entire processor. With the processor, execution instructions are optimized reducing the complexity of the processor, throughput is increased as delegation to multiple processing resources is scalable, and power usage efficacy is increased as underutilized and/or waiting processing resources may sleep when not active.

A Flash-based storage system, card, and/or module comprises a Flash controller configured to encrypt the data pages of a page stripe by shuffling the data pages, including loading each data page into a data shuffling buffer in a sequential order relative to other data pages in the page stripe, and thereafter unloading each data page in a non-sequential order relative to other data pages in the page stripe. The Flash controller is also configured to scramble the data pages of the page stripe by performing a bitwise logical operation on the data pages that are unloaded from the data shuffling buffer. A user key and one or more system keys are used to perform the shuffling and scrambling. The Flash controller is further configured to flush the user key by bypassing the system's backup power supply and performing an emergency system shutdown without backing up system data.

Systems and methods related to concealing mathematical and logical operations in software. Mathematical and logical operations are disguised by replacing them with logically equivalent expressions. Each equivalent expression has at least two expression constants whose values are based on scaling and bias constants assigned to variables in the original mathematical or logical operation. Each of the expression constants may also be based on additive or multiplicative inverses modulo n of the scaling and bias constants. By replacing the original operations with more complex but logically equivalent expressions containing variables that also involve more operations, the true nature of the original operations is disguised.

An object of the present invention is to provide an encryption/decryption system and encryption/decryption equipment which suppress the adverse effect of a load on arithmetic and logic operations to be performed by a computer, whose cipher system is hard to infer, which provide great security, and which eliminate the labor of managing keys or entering a key. A security key that encrypts or decrypts data using random numbers generated by a thermal noise random number generator is detachably attached to a personal computer. When attached to the personal computer, the security key autonomously encrypts or decrypts data to be handled by the personal computer. In other words, encryption/decryption equipment employing the thermal noise random number generator is detachably attached to a computer. The encryption/decryption equipment can be used as easily as keystrokes are made, and great security can be guaranteed.

An occlusion detection system and method include a decomposer configured to decompose an image into a set of hierarchical parts. A hierarchy of classifiers is employed to detect features in the image and the hierarchical parts. A logical operation is configured to logically combine a classification result from at least two of the classifiers to detect an occlusion state of the image.

The invention discloses an on-line detection device for open-circuit fault of power tubes of an inverter and a detection method thereof, relates to the field of on-line detection, and solves the problem of low detection speed existing in the conventional detection method and detection device. The detection device consists of three on-line detection circuits for the open-circuit fault of the power tubes; the circuit is used for detecting the open-circuit fault state of two power tubes in a bridge-arm circuit, and consists of a photocoupler circuit for detection, a logic circuit and a rising-edge delay circuit, wherein the rising-edge delay circuit receives a switch signal for time delay to acquire a time-delay switch signal, and sends the time-delay switch signal to the logic circuit; meanwhile, the photocoupler circuit for detection receives the switch signal controlled lower output signal, and transforms the output signal into a logic signal and sends the logic signal to the logic circuit; and logical operation is carried out to obtain the fault state, when the logical operation result is zero, the power unit correspondingly controlled by the switch signal is in a open-circuit fault state, otherwise, the power unit is normal. The invention is applicable to the open-circuit fault diagnosis of the single pipe or bridge arm of the inverter in various controlled motor drive systems and power-supply systems with current-open or close loop.

The invention discloses a distributed intelligent DNS (domain name server) library system which comprises a DNS configuration module, a domain name logical operation module, a detection module, a communication module and a plurality of intelligent DNS nodes. By the distributed intelligent DNS library system provided by the embodiment of the invention, through the mutual cooperation of modules, when the DNS of a user passes the local DNS server request to the intelligent DNS nodes, the intelligent DNS nodes return the user DNS request result, thus the user can nearby access a CDN (content distribution network) node with the best performance.