428 results about "Truth value" patented technology

An retention flash controller reads assigned-level bits from a bad block / erase count table or from a page status table that indicate when flash memory cells operate as Triple-Level-Cell (TLC), Multi-Level-Cell (MLC), or Single-Level-Cell (SLC). Pages that fail as TLC or MLC are downgraded for use as SLC pages by changing the assigned-level bits. The level bits adjust truth tables used by translation logic that receives inputs from voltage comparators reading a bit line. The range of voltages for each logic level may be adjusted by the truth tables or by programmable registers. The programming voltage or programming pulses may be adjusted to increase endurance and the number of permitted program-erase cycles while reducing retention times before a refresh is needed of the flash cells. Mixed configurations of flash memory have MLC blocks and MLC as SLC blocks, or other combinations.

A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits / cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

A database query optimizer processes an expression in a database query, and generates therefrom an operand list and a corresponding truth table that may be represented by a list of binary characters, where the operand list and corresponding truth table represent a disjunct normal form for the expression. Each expression is stored once it is processed into its operand list and corresponding list of binary characters. New queries are processed into component expressions, and each expression is checked to see if the expression was previously processed and stored as a processed expression. If so, the operand list and list of binary characters for the previously-stored expression may be used in processing the current expression. If there is no previously-stored expression that corresponds to the current expression, the previously-stored expressions are checked to see if any correspond to a complement of the current expression. If so, a new expression is easily constructed for the current expression by retrieving the list of binary characters that correspond to the complement expression, and inverting the bits in the list of binary characters. If there is no previously-stored expression that corresponds to the current expression or its complement, an operand list and corresponding list of binary characters are generated for the current expression. Logical operations between predicates in a query may be performed by performing mathematical operations on the lists of binary characters corresponding to each predicate expression. The end result is an operand list and corresponding list of binary characters that represents the entire expression in a query.

A method for performing DMA transfers with dynamic descriptor structure. A processor first creates a new chain of descriptors each including an end-of-chain (EOC) entry set to a false value except a dummy descriptor at the end of the new chain having the EOC entry set to a true value. The new descriptor chain can be appended to a previous descriptor chain, if any, by transferring parameters and a link pointer of the first descriptor within the new descriptor chain to a dummy descriptor of the previous descriptor chain. Then the processor changes the EOC entry of the dummy descriptor within the previous chain from the true value to the false value. Therefore, a DMA controller is able to transfer data in accordance with the new descriptor and also the previous one.

Methods, apparatuses, and computer program products for selected alert delivery in a distributed processing system are provided. Embodiments include receiving a plurality of events from one or more event producing components of the distributed processing system; creating, by an incident analyzer, in dependence upon the events a truth space representing events that make one or more conditional event processing rules true, the truth space including a set of truth points, each truth point including a set of events and a set of event locations; creating, by the incident analyzer, in dependence upon the truth space one or more alerts including assigning one of the locations of the truth space to one or more of the alerts; and sending, by the incident analyzer, the alerts to at least one component of the distributed processing system.