Embodiments of this application relate to the field of memories, and provide a
data input / output circuit and a memory. The
data input / output circuit includes a parallel-to-serial conversion circuit, configured to receive N pieces of data, and serially output the N pieces of data in a first time period; a read enable
signal generation circuit, configured to generate a read enable
signal, the read enable
signal being at an active level in the first time period; a resistance
control circuit, electrically connected to the read enable signal generation circuit, and configured to receive a termination resistance control code, an output drive resistance control code, and the read enable signal, and choose, based on the read enable signal, to output the termination resistance control code or output the output drive resistance control code; and an output drive circuit, electrically connected to the parallel-to-serial conversion circuit and the resistance
control circuit, and configured to receive the N pieces of data and a signal output by the resistance
control circuit, configure an output drive resistance value based on the signal output by the resistance control circuit and output the N pieces of data, or configure a termination resistance value, where N is a positive integer greater than 1.