117 results about "Transistor circuits" patented technology

A comparator includes an input circuit that receives a first input signal and a second input signal, a first sense amplifying circuit that generates a first output signal and a second output signal by amplifying a potential difference between the first input signal and the second input signal, a first clocking transistor circuit that connects the input circuit to the first sense amplifying circuit based on a first clock signal, a second sense amplifying circuit that generates a third output signal and a fourth output signal by amplifying the potential difference between the first input signal and the second input signal, and a second clocking transistor circuit that connects the input circuit to the second sense amplifying circuit based on a second clock signal.

The application discloses a DC-DC converter circuit based on over-temperature protection threshold adjustment, and an over-temperature detection module comprises: a first transistor circuit, the base of the transistor is connected with the reference voltage VBG output end of a band gap reference module, a positive temperature coefficient voltage proportional to absolute temperature is generated; a voltage dividing circuit input end is connected with the positive temperature coefficient voltage output end, the positive temperature coefficient voltage is divided to generate a detection voltage; a second transistor circuit, the base of the transistor is connected with the detection voltage output end, an over-temperature protection signal OTP is output to shut down the main circuit of the converter; an adjustment resistance circuit receives a digital adjustment signal; the digital adjustment signal changes the voltage dividing ratio of the positive temperature coefficient voltage divided to the detection voltage by controlling the equivalent resistance value of the adjustment resistance circuit; the change direction of the voltage dividing ratio is opposite to the change direction of the reference voltage VBG caused by adjustment. The application significantly improves the accuracy, consistency and overall reliability of the over-temperature protection threshold.

A kind of multi-channel high-voltage large current transistor array and its reliability test circuit belong to integrated circuit integration and testing technical field.Each column transistor circuit is composed of transistor array unit by composite transistor, freewheeling diode, base series resistance, current limiting resistance, pull-down resistance. Reliability test circuit includes single-chip microcomputer, single-chip microcomputer port indicator light, MOS drive circuit, transistor array device, transistor array device load system. Each interface of the single-chip microcomputer is connected with corresponding indicator light, corresponding MOS drive circuit unit, the output end of each unit of MOS drive circuit is connected with the base of corresponding array of transistor array device, the collector of corresponding array of transistor array device is connected with load system. It solves the problem that existing multi-channel transistor reliability test method cannot test signal interference between channels, thermal effect, potential failure risk under extreme working environment. It is widely used in transistor array product reliability test technical field.

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

The application relates to a GaN transistor driving circuit. It is used for a driven GaN transistor, and comprises upper and lower transistor circuits and upper and lower transistor control circuits. The upper and lower transistor circuits comprise upper and lower transistors, the upper and lower transistors are GaN transistors, the drain of the upper transistor is connected with a power voltage VCC, the gate is connected with a digital input VIN, the source is connected with the drain of the lower transistor, and is connected with the gate of the driven GaN transistor as the output of the GaN transistor driving circuit; the gate of the lower transistor is connected with the upper and lower transistor control circuits; the upper and lower transistor control circuits control the lower transistor by using a bus voltage VD, the power voltage VCC and the digital input VIN, so that the output of the GaN transistor driving circuit is in phase with the digital input VIN, the upper and lower transistor control circuits comprise transistors, the transistors are GaN transistors, and are turned on when the gate is applied with a voltage higher than a threshold voltage.

The invention relates to a memory device with pass transistor circuitry. A memory device has: a substrate having an H-shaped active region, the H-shaped active region includes a common active region extending in a first horizontal direction, and a first protruding active region, a second protruding active region, a third protruding active region, and a fourth protruding active region extending from an edge of the common active region in a second horizontal direction perpendicular to the first horizontal direction; a first pass transistor having a first gate electrode disposed over the first protruding active region; a second pass transistor having a second gate electrode disposed over the second protruding active region; a third pass transistor having a third gate electrode disposed over the third protruding active region; and a fourth pass transistor having a fourth gate electrode disposed over the fourth protruding active region.

A complementary field-effect transistor (CFET) circuit with a direct vertical connector and a method for manufacturing the same are disclosed. In one aspect, a semiconductor structure includes: a first field-effect transistor (FET) of a first charge carrier type, the first field-effect transistor (FET) including a first source / drain (S / D) region (412b) and a second source / drain (S / D) region (412a) and one or more channels (408b), the one or more channels being electrically connected to the first S / D region and the second S / D region through a first gate structure; a second FET of a second charge carrier type, the second FET being disposed above the first FET in the Z direction and including a third S / D region (414b) and a fourth S / D region (414a) and one or more channels (408a), the one or more channels being electrically connected to the third S / D region and the fourth S / D region through a second gate structure; and a vertical connector (420) extending in the Z direction from the top surface of the first S / D region (412b) to the bottom surface of the third S / D region (414b) and electrically coupling the first S / D region to the third S / D region.

The invention relates to the technical field of intelligent chips, and discloses a transistor circuit optimization method for improving the heat dissipation performance of an amplifier chip, and the method comprises the steps: carrying out the thermal resistance modeling of an input matching network, and obtaining the temperature rise distribution; a copper-graphene composite thermal conductivity enhancing structure is arranged on a grid wiring path; embedding an aluminum nitride high-thermal-conductivity dielectric layer below the grid electrode and connecting the deep silicon through hole to the substrate heat sink to construct a vertical low-thermal-resistance channel; a heat isolation groove filled with aerogel is arranged between the matching network and the active region to block transverse heat flow; a miniature temperature sensor and a bias control circuit are integrated, and gate voltage drift is dynamically compensated. According to the invention, the active heat dissipation structure matched with the thermal resistance of the input matching network is constructed in the grid region of the transistor, so that local hot spots caused by mismatching of the thermal resistance are eliminated fundamentally; a vertical heat dissipation channel formed by the high thermal conductivity dielectric layer and the deep silicon through hole significantly reduces a thermal resistance path from the grid electrode to the heat sink.

A bias compensation circuit includes a detection circuit comprising a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal; and a first diode circuit having a first terminal for receiving a second current and a second terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit and provides a second voltage level based on the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current based on the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias level based on the first reference current.

The present disclosure describes various aspects of implementing a low-dropout regulator in a gate-all-around process. In some aspects, a low-dropout (LDO) regulator circuit includes an amplifier and a power transistor with a source terminal coupled to a power rail. The LDO circuit may also include protection circuitry configured to prevent devices of the circuit from exceeding inter-terminal voltage ratings, which may protect the devices from damage when the LDO circuit is active or inactive. In some implementations, the protection circuitry includes a transistor coupled in series with the power transistor, voltage sources that provide signals or bias at intermediate voltages below a voltage of the power rail, and other transistors that operate based on or apply the intermediate voltages to the devices of the circuit. By so doing, the LDO circuit can be implemented in advanced fabrication processes (e.g., gate-all-around) in which devices may have reduced inter-terminal voltage ratings.

The invention discloses a rail-to-rail input bias current compensation circuit, which is characterized in that an input pair transistor module is formed by a PNP input differential pair and an NPN input differential pair which are connected in parallel, and can be switched to work or work simultaneously in a full common-mode voltage range to adapt to different input voltage conditions; secondly, the current sensing module samples the change of the bias current to generate a sensing current, so that the change of the bias current can be dynamically monitored and compensated; the current mirror module copies the sensing current, the input geminate transistor matching module serves as a matching transistor circuit of the input geminate transistor module, and after the sensing current is reduced, the sensing current is injected into the differential input end of the rail operational amplifier through the high-impedance current mirror module. The technical problems that in an existing PNP and NPN combined compensation method, the input bias current is large, the amplification factor difference of NPN and PNP tubes in a full-temperature region is large, and in a mirror image compensation method, only linear copying can be conducted on a direct-current working point, the nonlinear component of the input bias current Ib changing along with differential mode voltage Vdm cannot be tracked, and consequently nonlinear distortion is serious are solved.

A memory device including a substrate having a first active area and a second active area adjacent to each other in a first horizontal direction is disclosed. A first pass transistor is disposed on the substrate and has a first gate electrode crossing the first active area in the first horizontal direction, and a second pass transistor is disposed on the substrate and has a second gate electrode crossing the second active area in the first horizontal direction. The first active area has, in a planar view, a first recessed portion facing the second gate electrode on one side adjacent to the second active area.

An oscillating circuit with a withstand voltage mechanism. An inductor circuit is coupled to a pair of oscillating output terminals. A cross-coupled transistor circuit is coupled between the pair of oscillating output terminals and a first terminal. A capacitor circuit is coupled between the pair of oscillating output terminals. A first source degradation circuit includes: a first inductor, a first capacitor, a second capacitor, and a first source degradation transistor. The first inductor is electrically coupled between the first terminal and a first power supply voltage. The first capacitor is electrically coupled between the first terminal and a second terminal. The second capacitor is coupled between the first power supply voltage and a third terminal, wherein the third terminal is coupled to a second power supply voltage. The first source degradation transistor is coupled between the second terminal and the third terminal and is turned on by a first feed voltage.

The invention discloses a set of transistor structures and a transistor circuit. The transistor circuit includes a transistor and a voltage source. The transistor includes a semiconductor substrate, a gate structure, a channel region and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first end and a second end. The first conductive region is electrically coupled to the first end of the channel region, and the first conductive region includes a top surface and a bottom surface, where the bottom surface of the first conductive region is lower than the semiconductor surface of the semiconductor substrate. The voltage source is electrically coupled to the transistor through a bottom surface of the first conductive region. Compared with the prior art, the complexity of multi-layer interconnection in a new circuit architecture formed by a complementary metal oxide semiconductor circuit formed by the transistors can be reduced, and the speed performance and the anti-noise capability of the new circuit architecture can be improved, so that more and better heat dissipation paths can be created in the new circuit architecture.

This invention provides a photodetector including SPADs, which significantly reduces substrate fabrication costs compared to InGaAs, resulting in fewer residual pulses and suppressed DCR. The photodetector of this invention detects incident light from an object and includes: (i) a P-type silicon (Si) substrate; (ii) a P-type germanium (Ge) layer formed by epitaxial growth on a first surface of the P-type silicon (Si) substrate; (iii) a P-type thin-film silicon (Si) layer formed on the P-type germanium (Ge) layer; and (iv) the P-type thin-film silicon (Si) layer is divided into a first region and a second region by shallow trench isolation, wherein a plurality of single-photon detection diodes (SPADs) arranged in an array are formed in the first region, and a CMOS transistor circuit driving the SPADs is formed in the second region.

The invention relates to an ultra-low power consumption energy storage and management circuit special for a friction nanometer generator based on a transformer and a transistor circuit, and the circuit comprises a transformer grid-connected current increasing module which converts the high-voltage small current of TENG into low-voltage large current, and improves the power generation utilization rate; the transistor rectification module rectifies the low-voltage large current into direct current; the capacitor energy storage module is used for storing direct current; and the power supply management module monitors the capacitor voltage in real time, and when the capacitor voltage reaches a preset value, a discharge mode is switched to provide stable electric energy for electric appliances. Aiming at the problems of low energy conversion efficiency, insufficient automation and dependence on manual intervention of an energy storage circuit of a traditional friction nano generator (TENG), the circuit solves the problem of energy loss caused by high internal resistance of the TENG through current amplification by a transformer, charge and discharge control by a transistor and ultra-low power consumption design, realizes efficient energy storage and automatic management, and is suitable for large-scale popularization and application. The system is suitable for micro-energy scenes such as Internet of Things and wearable equipment, and has the characteristics of high charging speed, high energy utilization rate and system self-locking control.

A semiconductor memory device includes: a substrate including a first region and a second region, the first region includes a peripheral circuit and a first active region (FAR), and the second region includes memory cell blocks. The FAR includes a FAR first extension extending in a first direction, a FAR second extension extending in a second direction, and a FAR third extension extending in a third direction. The FAR first extension, the FAR second extension, and the FAR third extension form an angle greater than 90 degrees relative to one another. The device includes a first pass transistor circuit configured to transmit driving signals, and the first pass transistor circuit includes a FAR first gate structure on the FAR first extension, a FAR second gate structure on the FAR second extension, a FAR third gate structure on the FAR third extension, and a first shared source / drain.

To provide a planar antenna equipped with a temperature-controllable metal-insulator phase transition element using a thin-film transistor circuit.SOLUTION: A planar antenna 1 includes an antenna substrate 11 on which are arranged at least one patch antenna P, a signal line LS electromagnetically coupled to the patch antenna P, and a metal-insulator phase transition element V provided on the signal line LS, and a temperature control substrate including a thin-film transistor circuit, having at least one heating element H temperature-controlled using the thin-film transistor circuit as a drive circuit. The antenna substrate and the temperature control substrate are laminated together such that heat from the heating element H can be conducted to the metal-insulator phase transition element V.SELECTED DRAWING: Figure 2

The invention provides a neutral-point balance control method of a three-level inverter and the three-level inverter, and belongs to the technical field of inverters. Generating a first / second discontinuous pulse width modulation wave based on an externally input three-phase reference voltage; according to the current midpoint potential deviation state of the three-level inverter and the current space vector sector information of the three-phase reference voltage, weighting coefficients corresponding to the two discontinuous pulse width modulation waves are determined respectively; according to the weighting coefficient, performing weighted fusion on the two discontinuous pulse width modulation waves to obtain a target three-phase modulation wave; and generating a target driving signal based on a comparison result of a preset reference three-phase carrier wave and the target three-phase modulation wave, and sending the target driving signal to a switching tube circuit in the three-level inverter, so that the neutral-point potential of the three-level inverter is balanced. According to the invention, the neutral-point potential balance capability is improved while the switching loss is reduced, so that the system stability and the electric energy quality are improved.

The utility model belongs to the technical field of LED display screens, and provides a display module with a triode circuit design, the display module comprises a matching circuit design of a triode and a resistor, and negation of signals in the circuit is realized through matching of the triode and the resistor, so that negation design in an original circuit is replaced and compatible, and negation is realized. The triode circuit design is suitable for the circuit design which exceeds 16 scanning and uses 138 decoding in the display module circuit design; according to the utility model, through newly adding or changing the design of the negation circuit of the signal in the LED module circuit, the flexibility of material preparation selection and the reduction of the production cost in the production process are realized; by adopting the matching circuit design of the triodes and the resistors, negation of signals in the circuit is realized, so that the original negation design, such as a 74HC04 chip, is replaced, and the cost of raw materials is reduced; meanwhile, the design is suitable for the circuit design which exceeds 16 scanning and uses 138 decoding in the circuit design of the display module.

A reference current generating circuit including a reference voltage generating circuit and a current source circuit is provided. The reference voltage generating circuit generates a first reference voltage according to a first current. The reference voltage generating circuit includes a native transistor device, and the first current flows through the native transistor device. The current source circuit is coupled to the reference voltage generating circuit. The current source circuit generates a reference current according to the first reference voltage. The current source circuit includes a cascode transistor circuit, and the reference current flows through the cascode transistor circuit. The cascode transistor circuit includes a low-voltage transistor device and a high-voltage transistor device coupled in series.

A circuit board, a driving method thereof and a display device, the circuit board being used for driving a sensor in a display panel, the sensor comprising a plurality of transistors, the circuit board comprising: a plurality of switching pins electrically connected with first poles of the plurality of transistors; the first output pin of the microcontroller is electrically connected with the second electrodes of the plurality of transistors, and at least one first input pin of the microcontroller is electrically connected with the plurality of switching pins; the microcontroller is configured to provide a pulse width modulation signal for the plurality of transistors through the first output pin, and receive electrical signals at the plurality of switching pins through the at least one first input pin after delaying a preset duration from a rising edge of the pulse width modulation signal.

The invention relates to a stackable switched mode converter. A circuit includes a first transistor (106), a second transistor (108), a PWM circuit (114), a minimum turn-off timer (116), and a trigger circuit (112). The first transistor (106) has a first control terminal and the second transistor (108) has a second control terminal. The PWM circuit (114) has a first output coupled to the first control terminal, a second output coupled to the second control terminal, a first input, and a second input. The minimum turn-off timer (116) has a timer output coupled to a first input of the PWM circuit (114). The trigger circuit (112) has a trigger signal output, a trigger signal input, and a trigger signal receiving output coupled to the PWM circuit (114). The trigger circuit (112) includes a latch circuit.

A static random access memory (SRAM) bit-cell includes a cross-coupled latch circuit, a write driver circuit, a first transistor circuit, and a second transistor circuit. The cross-coupled latch circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors form a first inverter. The third and fourth transistors form a second inverter. The first inverter and the second inverter are cross-coupled. The write driver circuit is coupled to one reference voltage and a write bit line pair, and configured to write a data input into the cross-coupled latch circuit. The first transistor circuit is coupled to connection terminals of the first transistor and the third transistor. The second transistor circuit is coupled between the write driver circuit and another reference voltage, wherein both of the first transistor circuit and the second transistor are controlled by a word line.

An oscillator circuit having voltage-withstanding mechanism is provided. An inductor circuit is coupled to a pair of oscillating output terminals. A cross-coupled transistor circuit is coupled between the oscillating output terminals and a first terminal. A capacitor circuit is coupled between the oscillating output terminals. A first source degeneration circuit includes a first inductor, a first capacitor, a second capacitor and a first source degeneration circuit. The first inductor is coupled between the first terminal and a first power voltage. The first capacitor is coupled between the first terminal and a second terminal. The second capacitor is coupled between the first power voltage and a third terminal that is coupled to a second power voltage. The first source degeneration is coupled between the second terminal and the third terminal and is turned on based on a first feeding voltage.

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

According to some embodiments of the inventive concept, there is provided a non-volatile memory device comprising: a memory cell array; a pass transistor circuit electrically connected to the memory cell array; a block select line group including a plurality of block select lines, wherein the plurality of block select lines comprises a first block select line and a second block select line, each of which extends in a first direction on a first layer, and the block select line group is electrically connected to the pass transistor circuit; and a first metal line extending in a second direction on a second layer, wherein the second layer is on the first layer, wherein at least one block select line includes at least one twist pattern that changes a path of the at least one block select line in a hole of the first metal line.

A memory device having a pass transistor circuit includes a substrate on which a first active region and a second active region adjacent to each other in a first horizontal direction are disposed. The first transfer transistor is disposed on the substrate and has a first gate electrode across the first active region in a first horizontal direction, and the second transfer transistor is disposed on the substrate and has a second gate electrode across the second active region in the first horizontal direction. In plan view, the first active region has a first recessed portion facing the second gate electrode on a side adjacent to the second active region.

A computer-implemented method includes receiving a transistor circuit logic architecture and a desired switching profile at a controller. An incomplete machine learning feature is extracted from the transistor circuit logic architecture and from the desired switching profile. The incomplete machine learning feature lacks a set of input vectors. The incomplete machine learning feature is applied to a predictive machine learning model in an inference mode. The set of test input vectors is generated based at least in part on an output of the predictive machine learning model.

An electrostatic discharge protection circuit with stable discharging mechanism. A voltage input end generates a detection signal according to a voltage input end, and a first inverter outputs an inverted detection signal. A first P-type and N-type transistor circuit of a voltage lifting circuit is connected in series between the voltage input end and a ground end through a first end, and a second P-type and N-type transistor circuit is connected in series between the voltage input end and the ground end through a second end. Control ends of the first and second P-type transistors are electrically connected to the second end and the first end, respectively, and control ends of the first and second N-type transistors receive the inverted detection signal and the detection signal, respectively. A second inverter receives an inverted lifting detection signal from the second end and outputs a lifting detection signal. An electrostatic discharge transistor is controlled by the lifting detection signal to discharge the voltage input end when turned on.