28 results about "Transistor circuits" patented technology

A kind of multi-channel high-voltage large current transistor array and its reliability test circuit belong to integrated circuit integration and testing technical field.Each column transistor circuit is composed of transistor array unit by composite transistor, freewheeling diode, base series resistance, current limiting resistance, pull-down resistance. Reliability test circuit includes single-chip microcomputer, single-chip microcomputer port indicator light, MOS drive circuit, transistor array device, transistor array device load system. Each interface of the single-chip microcomputer is connected with corresponding indicator light, corresponding MOS drive circuit unit, the output end of each unit of MOS drive circuit is connected with the base of corresponding array of transistor array device, the collector of corresponding array of transistor array device is connected with load system. It solves the problem that existing multi-channel transistor reliability test method cannot test signal interference between channels, thermal effect, potential failure risk under extreme working environment. It is widely used in transistor array product reliability test technical field.

A complementary field-effect transistor (CFET) circuit with a direct vertical connector and a method for manufacturing the same are disclosed. In one aspect, a semiconductor structure includes: a first field-effect transistor (FET) of a first charge carrier type, the first field-effect transistor (FET) including a first source / drain (S / D) region (412b) and a second source / drain (S / D) region (412a) and one or more channels (408b), the one or more channels being electrically connected to the first S / D region and the second S / D region through a first gate structure; a second FET of a second charge carrier type, the second FET being disposed above the first FET in the Z direction and including a third S / D region (414b) and a fourth S / D region (414a) and one or more channels (408a), the one or more channels being electrically connected to the third S / D region and the fourth S / D region through a second gate structure; and a vertical connector (420) extending in the Z direction from the top surface of the first S / D region (412b) to the bottom surface of the third S / D region (414b) and electrically coupling the first S / D region to the third S / D region.

An oscillating circuit with a withstand voltage mechanism. An inductor circuit is coupled to a pair of oscillating output terminals. A cross-coupled transistor circuit is coupled between the pair of oscillating output terminals and a first terminal. A capacitor circuit is coupled between the pair of oscillating output terminals. A first source degradation circuit includes: a first inductor, a first capacitor, a second capacitor, and a first source degradation transistor. The first inductor is electrically coupled between the first terminal and a first power supply voltage. The first capacitor is electrically coupled between the first terminal and a second terminal. The second capacitor is coupled between the first power supply voltage and a third terminal, wherein the third terminal is coupled to a second power supply voltage. The first source degradation transistor is coupled between the second terminal and the third terminal and is turned on by a first feed voltage.

The invention discloses a set of transistor structures and a transistor circuit. The transistor circuit includes a transistor and a voltage source. The transistor includes a semiconductor substrate, a gate structure, a channel region and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first end and a second end. The first conductive region is electrically coupled to the first end of the channel region, and the first conductive region includes a top surface and a bottom surface, where the bottom surface of the first conductive region is lower than the semiconductor surface of the semiconductor substrate. The voltage source is electrically coupled to the transistor through a bottom surface of the first conductive region. Compared with the prior art, the complexity of multi-layer interconnection in a new circuit architecture formed by a complementary metal oxide semiconductor circuit formed by the transistors can be reduced, and the speed performance and the anti-noise capability of the new circuit architecture can be improved, so that more and better heat dissipation paths can be created in the new circuit architecture.

This invention provides a photodetector including SPADs, which significantly reduces substrate fabrication costs compared to InGaAs, resulting in fewer residual pulses and suppressed DCR. The photodetector of this invention detects incident light from an object and includes: (i) a P-type silicon (Si) substrate; (ii) a P-type germanium (Ge) layer formed by epitaxial growth on a first surface of the P-type silicon (Si) substrate; (iii) a P-type thin-film silicon (Si) layer formed on the P-type germanium (Ge) layer; and (iv) the P-type thin-film silicon (Si) layer is divided into a first region and a second region by shallow trench isolation, wherein a plurality of single-photon detection diodes (SPADs) arranged in an array are formed in the first region, and a CMOS transistor circuit driving the SPADs is formed in the second region.

An oscillator circuit having voltage-withstanding mechanism is provided. An inductor circuit is coupled to a pair of oscillating output terminals. A cross-coupled transistor circuit is coupled between the oscillating output terminals and a first terminal. A capacitor circuit is coupled between the oscillating output terminals. A first source degeneration circuit includes a first inductor, a first capacitor, a second capacitor and a first source degeneration circuit. The first inductor is coupled between the first terminal and a first power voltage. The first capacitor is coupled between the first terminal and a second terminal. The second capacitor is coupled between the first power voltage and a third terminal that is coupled to a second power voltage. The first source degeneration is coupled between the second terminal and the third terminal and is turned on based on a first feeding voltage.

A non-mobile indoor light-emitting diode (LED) emergency light in coordination with a long-range (LoRa) gateway includes an alternating-current (AC) control device, an emergency control device, a light source assembly, a battery, an auxiliary control board, and a power input interface, where a transistor circuit controlled by a pin of a chip of a microcontroller circuit is provided between an output terminal of the AC control device and an LED load; during emergency testing, the output terminal of the AC control device is disconnected from the LED load; the light source assembly includes a lampshade, an LED light source module, and a heat sink; the power input interface is formed by lamp caps at two ends, and is configured with the AC control device and the emergency control device; the lampshade and the heat sink are coordinated with the LED light source assembly.

This document describes devices, transistor structures, systems, and techniques for integrated circuits relating to gate-all-around field-effect transistor circuits, in which an n-type transistor is integrated with a p-type transistor such that each exhibits a voltage technique within its channel material. The nanowires of the p-type transistor are released during the growth of the source and drain material and surrounded by a flowable sacrificial oxide structure to exert compressive stresses on the channel material. The source and drain of the n-type transistor are grown in the presence of a grid-matched sacrificial material to place the channel material under tensile stress, and the nanowires are subsequently released. After removal of the flowable sacrificial oxide structure, gate structures are coupled to the n- and p-type transistors.

A circuit is provided in which, in response to an overcurrent condition, a switch is opened between an input node and a first gate node of a dual-gate transistor arrangement, while a connection is maintained between the input node and a second gate node.

This invention discloses an embedded liquid-cooled chip with a manifold structure and its fabrication method using laser direct writing. The chip includes an active chip and a manifold template. The active chip has an active device side and a channel side on its two sides, respectively. The active device side is equipped with transistor circuits that implement electrical functions, and the channel side surface is processed with liquid cooling channels. The manifold template is a single-board structure or a stacked board structure. This invention replaces the patterned photolithography method with a laser direct writing method for fabricating embedded liquid-cooled chips with manifold structures, solving the problems of low flexibility and high production cost of the patterned photolithography method in small-batch production of embedded liquid-cooled chips with manifold structures. This achieves low-cost and highly flexible fabrication of embedded liquid-cooled chips with manifold structures.

With this invention, electronic circuit components such as transistors, diodes, zener diodes and varicap diodes, which are conventionally manufactured with semiconductors, can be produced without semiconductors by means of a much simpler and cheaper technology, and by the same technology a compensation capacitor can be manufactured whose capacitance is automatically varied so as to follow changes in the load simultaneously. This principle may also be applied in other areas such as microwaves. In simple terms, the electric and magnetic fields of the main capacitor are blocked by a control voltage and varied between zero and maximum values, and as a result the capacitance of the main capacitor is changed. The fundamental principle here is the control of the electric and magnetic fields between the two conductive plates of a fixed-capacitance capacitor. For this purpose, a control voltage is applied between a third metallic plate, designed as a grid or similar structure so as not to block the electric and magnetic fields of the main capacitor and placed closer to one of the two plates, and the adjacent metallic plate, while a DC voltage (VDD) of suitable value for the circuit is applied across the terminals of the main capacitor. In a slightly different version, two grids are provided so that the structure can be used both as a diode and as a transistor. In both cases, the capacitance value of the main capacitor varies depending on the control voltage, i.e. Co = f(Vi). This means that, similar to classical transistors, the impedance of the circuit varies depending on the control voltage. In this structure, which exhibits behaviour similar to FET transistors, the output voltage is taken across the two outer plates of the capacitor with a design similar to a classical transistor circuit. In the production stage, the dielectric will be formed by coating very thin special plastic or other suitable materials with an appropriate metal of suitable thickness for the design and winding it in roll form. Likewise, dielectric layers may also be formed as very thin oxide or other non-conductive chemical compounds on the surfaces of the metallic 24 plates. That is, use will be made of conventional capacitor technologies such as ceramic, tantalum and electrolytic capacitors. In addition, different methods may be developed depending on the field of application. These designs will find application areas as semiconductor-free transistors, diodes, voltage-controlled variable capacitors, and many other uses, some of which have been explained in this project.

This application provides a linear voltage regulator circuit, chip, and electronic device, relating to the field of electronic circuit technology. The linear voltage regulator circuit includes a power supply terminal, a voltage input terminal, a voltage output terminal, a first resistor, a first Zener diode, a regulating transistor circuit, and an error sampling and adjustment circuit. During power-up at the power supply terminal, the regulating transistor circuit conducts both the power supply terminal and the voltage output terminal to supply power to the voltage output terminal. After power-up and entering the operating mode, it regulates and adjusts the voltage at the voltage output terminal. The first Zener diode reverse-biased during power-up at the power supply terminal to regulate the voltage at the voltage output terminal. After entering the operating mode, the error sampling and adjustment circuit amplifies the error voltage between the voltage output terminal and the voltage input terminal compared to the reference voltage at the reference terminal. Based on the error amplification result, it controls the regulating transistor circuit to regulate and adjust the voltage at the voltage output terminal. This application improves the response speed and voltage regulation effect of the linear voltage regulator circuit.

This application discloses a soft-start control circuit, method, device, and auxiliary lamp for a lamp module. The soft-start control circuit relates to the field of auxiliary lamp control technology. The soft-start control circuit includes: a switching transistor drive circuit; a switching transistor circuit including at least one switching transistor, with its input connected to the drive circuit and its output connected to the control terminal of the lamp module; and a main control module, whose output is connected to the drive circuit. The main control module receives the lamp module's on / off signal and outputs a control signal, causing the drive circuit to periodically control the switching transistor in the drive circuit to turn on and off according to the control signal until the duration of the main control module's output control signal reaches a target time. This application improves the reliability of lamp module control.

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

In some embodiments, the memory device includes a memory cell array including a plurality of memory blocks including a plurality of word lines, a pass transistor circuit including a plurality of pass transistors coupled to the plurality of word lines, a row decoder configured to provide a block selection voltage to first terminals and a driving voltage to second terminals of the plurality of pass transistors, a voltage generator configured to generate the block selection voltage and the driving voltage, and a control circuit configured to control the row decoder and the voltage generator, perform a leakage detection operation on a target memory block of the plurality of memory blocks, set a plurality of first detection word lines of the target memory block to a first voltage level, and set a plurality of second detection word lines of the target memory block to a second voltage level.

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

The capacitively-coupled static random access memory (SRAM-C) compute-in-memory (CIM) circuit includes at least one static random access memory (SRAM) configured to store a bit value, at least one capacitively-coupled (CC) circuit coupled to at least one SRAM, and an energy recovery logic (ERL) driver configured to recover signal energy by utilizing a ramped sinusoidal hot clock. The CC circuit includes a first and second capacitors, a first pair, a second pair, a third pair, a fourth pair of transistors. Each pair of transistors include a first and second transistors coupled to one another. the first capacitor is coupled to the first and second pairs of transistors and the second capacitor is coupled to the third and fourth pairs of transistors. The SRAM-C CIM circuit enhances efficiency and effectiveness of multiply-and-accumulate (MAC) operations of the SRAM-C CIM circuit.

This invention relates to the field of charger technology, specifically disclosing a smart charger for tricycles based on parallel current sharing technology of switching power supplies. The charger includes a charger body containing several power control boards. Each power control board includes an automatic current sharing circuit, an automatic voltage limiting circuit, a power module control circuit, and a switching power supply power transistor circuit. The automatic current sharing circuit and the automatic voltage limiting circuit are respectively connected to an external bus current signal and an external bus voltage signal. The power module control circuit drives the switching power supply power transistor circuit to output different charging voltages or charging currents based on the battery voltage. This invention solves the charging problem for batteries with different voltage levels and capacities through VCV and VCC control methods, enabling a single charger to meet the charging needs of different battery models. Furthermore, after connecting to the bus, multiple power sub-modules can operate in parallel, achieving high power output, high charging efficiency, and low cost.

This invention provides a novel MOS transistor circuit for RF interference suppression in TFT-LCD display chips, comprising a MOS transistor. The key feature is that an injection layer is disposed in the DPW layer of the MOS transistor, the injection layer being connected to IOVCC, and the DNW layer of the MOS transistor being left floating. The injection layer, DNW layer, and DPW layer form a newly added parasitic NPN transistor, wherein the DPW layer is connected to VSS. A TFT-LCD display chip and a corresponding control method are also provided. When the chip is subjected to RF signal interference, this technology can effectively reduce the conduction of parasitic transistors inside the chip and the injection of charge into the substrate without increasing chip area or production costs. Furthermore, it is applicable to different manufacturing processes.

An oscillating circuit with a withstand voltage mechanism includes: a first inductor circuit, a cross-coupled transistor circuit, a second inductor circuit, and a capacitor circuit. The first inductor circuit is electrically coupled to a pair of terminals. The cross-coupled transistor circuit is electrically coupled to the pair of terminals. The second inductor circuit is electrically coupled between the pair of terminals and a pair of oscillation output terminals. The capacitor circuit is electrically coupled between the pair of oscillation output terminals.

A supply control circuit and corresponding device are provided. An exemplary circuit is configured to supply a load at an output node and comprises driver circuitry including voltage boost capacitive circuitry configured to apply to the control terminals of driver transistor(s) a voltage-pumped replica of a comparison signal between a reference voltage and a voltage that is a function of the output voltage. Voltage refresh transistor circuitry coupled to the voltage boost capacitive circuitry is configured to transfer the voltage-pumped replica. The driver circuitry is controllably switchable between a first mode with a conductive or non-conductive current flow path and a second mode with the voltage refresh transistor circuitry activated and a non-conductive current flow path of the driver circuitry. The circuit comprises variable boosted voltage generation circuitry to increase the variable boosted voltage in response to a decrease of the supply voltage at the supply node.

A non-volatile memory device includes a memory cell array, a pass transistor circuit that is electrically connected to the memory cell array, a block select line group that includes a plurality of block select lines, including a first block select line and a second block select line, each of which extends in a first direction on a first layer, the block select line group being electrically connected to the pass transistor circuit, and a first metal line that extends in a second direction on a second layer, on the first layer, the first direction intersecting the second direction, with at least one block select line among the plurality of block select lines including at least one twist pattern that changes a path of the at least one block select line in a hole of the first metal line in a plan view.

The present application discloses a soft start control circuit, method, and apparatus for a lamp module, and a power assist lamp. The soft start control circuit comprises: a switch transistor drive circuit; a switch transistor circuit, comprising at least one switch transistor, an input end of the switch transistor circuit being connected to the switch transistor drive circuit, and an output end of the switch transistor circuit being connected to a control end of the lamp module; a main control module, an output end of the main control module being connected to the switch transistor drive circuit, and used to receive an on signal of the lamp module and output a control signal, so that the switch transistor drive circuit periodically controls on and off states of the switch transistor in the switch transistor circuit on the basis of the control signal, until a duration for which the main control module outputs the control signal reaches a target duration.

An object of the invention is to reduce reflux of an operating current of an electronic circuit provided with a plurality of transistor circuits. The electronic circuit includes a first power supply line, a second power supply line, a third power supply line, a first transistor circuit, and a second transistor circuit. A positive power supply voltage is applied to the first power supply line. A negative power supply voltage is applied to the second power supply line. An intermediate voltage between the positive power supply voltage and the negative power supply voltage is applied to the third power supply line. The first transistor circuit is connected between the first power supply line and the third power supply line. The second transistor circuit is connected between the second power supply line and the third power supply line.

This invention provides an adjustable output power supply circuit and an optical device. The adjustable output power supply circuit includes a switching circuit, a buck circuit, a first switching transistor circuit, and a second switching transistor circuit. The input terminal of the switching circuit is connected to the input power supply terminal, and the output terminal of the switching circuit is connected to the input terminals of the first switching transistor circuit and the buck circuit, respectively. The output terminal of the first switching transistor circuit is connected to a load circuit, and the output terminal of the buck circuit is connected to the input terminal of the second switching transistor circuit. The output terminal of the second switching transistor circuit is also connected to the load circuit. This invention enables automatic switching of power supply voltage for different application scenarios on the same hardware platform without the need for additional materials or changes to the BOM, significantly reducing costs and improving the convenience and practicality of engineering maintenance.

A memory device including a first semiconductor layer including a slim area, and a first cell area and a second cell area respectively arranged on both sides of the slim area in a first horizontal direction, and a second semiconductor layer, which vertically overlaps with the first semiconductor layer, and includes a pass transistor circuit connected to the first cell area and the second cell area through a word line, a block selection circuit for providing a block selection signal to the pass transistor circuit, and a voltage switch circuit for transmitting an operating voltage to the pass transistor circuit, wherein the voltage switch circuit may include a voltage switch region disposed in an under-slim region of the second semiconductor layer, wherein the under-slim region vertically overlaps with the slim area, and at least a part of the block selection circuit may be disposed in the under-slim region.