197 results about "Transistor circuits" patented technology

The invention provides a band-gap reference circuit for a low-voltage circuit, which comprises a clamping operational amplifier circuit for receiving an input voltage and outputting an amplified input voltage under the control of a bias voltage; the feedback adjustment circuit performs feedback adjustment on the amplified input voltage to obtain a feedback voltage; the current mirror circuit generates reference voltage and reference current according to the feedback voltage; the transistor circuit generates a positive / negative temperature coefficient current by using a reference voltage and generates an input voltage. The reference voltage output circuit generates and outputs a bandgap reference voltage using the reference current. The threshold voltage of a transistor in the circuit is reduced by using a substrate bias technology, the input node of the clamping operation amplification circuit is optimized, the minimum power supply voltage for working of the circuit is reduced, the loop is improved by using the feedback adjustment circuit, the power supply suppression capability is improved, and the stability of the output band-gap reference voltage is improved; the problems of how to improve the minimum power supply voltage of the band-gap reference circuit and how to optimize the power supply suppression effect are solved.

A comparator includes an input circuit that receives a first input signal and a second input signal, a first sense amplifying circuit that generates a first output signal and a second output signal by amplifying a potential difference between the first input signal and the second input signal, a first clocking transistor circuit that connects the input circuit to the first sense amplifying circuit based on a first clock signal, a second sense amplifying circuit that generates a third output signal and a fourth output signal by amplifying the potential difference between the first input signal and the second input signal, and a second clocking transistor circuit that connects the input circuit to the second sense amplifying circuit based on a second clock signal.

A battery package is provided. The battery package includes a battery, at least one terminal coupled to an antenna, a single wire interface configured to communicate with a processor and coupled to the at least one terminal, a battery authentication circuit arranged on the battery, a choke inductor coupled to the single wire interface, and a clamping transistor circuit including a clamping transistor and coupled to the choke inductor and configured to clamp a voltage applied to the single wire interface to an operating voltage of the battery authentication circuit.

The application discloses a DC-DC converter circuit based on over-temperature protection threshold adjustment, and an over-temperature detection module comprises: a first transistor circuit, the base of the transistor is connected with the reference voltage VBG output end of a band gap reference module, a positive temperature coefficient voltage proportional to absolute temperature is generated; a voltage dividing circuit input end is connected with the positive temperature coefficient voltage output end, the positive temperature coefficient voltage is divided to generate a detection voltage; a second transistor circuit, the base of the transistor is connected with the detection voltage output end, an over-temperature protection signal OTP is output to shut down the main circuit of the converter; an adjustment resistance circuit receives a digital adjustment signal; the digital adjustment signal changes the voltage dividing ratio of the positive temperature coefficient voltage divided to the detection voltage by controlling the equivalent resistance value of the adjustment resistance circuit; the change direction of the voltage dividing ratio is opposite to the change direction of the reference voltage VBG caused by adjustment. The application significantly improves the accuracy, consistency and overall reliability of the over-temperature protection threshold.

A kind of multi-channel high-voltage large current transistor array and its reliability test circuit belong to integrated circuit integration and testing technical field.Each column transistor circuit is composed of transistor array unit by composite transistor, freewheeling diode, base series resistance, current limiting resistance, pull-down resistance. Reliability test circuit includes single-chip microcomputer, single-chip microcomputer port indicator light, MOS drive circuit, transistor array device, transistor array device load system. Each interface of the single-chip microcomputer is connected with corresponding indicator light, corresponding MOS drive circuit unit, the output end of each unit of MOS drive circuit is connected with the base of corresponding array of transistor array device, the collector of corresponding array of transistor array device is connected with load system. It solves the problem that existing multi-channel transistor reliability test method cannot test signal interference between channels, thermal effect, potential failure risk under extreme working environment. It is widely used in transistor array product reliability test technical field.

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

The application relates to a GaN transistor driving circuit. It is used for a driven GaN transistor, and comprises upper and lower transistor circuits and upper and lower transistor control circuits. The upper and lower transistor circuits comprise upper and lower transistors, the upper and lower transistors are GaN transistors, the drain of the upper transistor is connected with a power voltage VCC, the gate is connected with a digital input VIN, the source is connected with the drain of the lower transistor, and is connected with the gate of the driven GaN transistor as the output of the GaN transistor driving circuit; the gate of the lower transistor is connected with the upper and lower transistor control circuits; the upper and lower transistor control circuits control the lower transistor by using a bus voltage VD, the power voltage VCC and the digital input VIN, so that the output of the GaN transistor driving circuit is in phase with the digital input VIN, the upper and lower transistor control circuits comprise transistors, the transistors are GaN transistors, and are turned on when the gate is applied with a voltage higher than a threshold voltage.

The invention relates to the technical field of power transistor output matching, in particular to a power transistor circuit and an integrated power transistor, the power transistor circuit comprises a power transistor body, a parallel resonance circuit and a second lead; the drain electrode of the power transistor body is electrically connected with the first end of the parallel resonance circuit, and the source electrode of the power transistor body is electrically connected with the second end of the parallel resonance circuit; when the drain electrode of the transistor body outputs a waveform, a standing wave is formed on a resonant circuit formed by a parasitic capacitor between the drain electrode and the source electrode of the transistor body and the parallel resonant circuit. Standing waves are generated through the resonance effect of the parallel resonance circuit, so that the efficiency of the power transistor is improved, and impedance matching is achieved.

The present invention discloses a slow start circuit for an audio switch, which includes a first transistor circuit, a second transistor circuit, a high-side level conversion circuit, a low-side level conversion circuit, and a main switch drive circuit. The low-side and high-side level conversion circuits are used to receive a slow start enable signal or a slow start disable signal sent by a digital circuit. When the high-side level conversion circuit and the low-side level conversion circuit receive the slow start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the slow start enable signal, receive a first current sent by a first current source through the first transistor circuit, and then drive the main switch drive circuit to receive a slow start current sent by a slow start current source to generate a main switch drive signal, and the slow start circuit enters the slow start mode. The slow start function proposed by the present invention realizes flexible adjustment of the slow start time length through an analog method, effectively eliminating the Pop sound when the earphone or the speaker is turned on.

The invention relates to a memory device with pass transistor circuitry. A memory device has: a substrate having an H-shaped active region, the H-shaped active region includes a common active region extending in a first horizontal direction, and a first protruding active region, a second protruding active region, a third protruding active region, and a fourth protruding active region extending from an edge of the common active region in a second horizontal direction perpendicular to the first horizontal direction; a first pass transistor having a first gate electrode disposed over the first protruding active region; a second pass transistor having a second gate electrode disposed over the second protruding active region; a third pass transistor having a third gate electrode disposed over the third protruding active region; and a fourth pass transistor having a fourth gate electrode disposed over the fourth protruding active region.

A complementary field-effect transistor (CFET) circuit with a direct vertical connector and a method for manufacturing the same are disclosed. In one aspect, a semiconductor structure includes: a first field-effect transistor (FET) of a first charge carrier type, the first field-effect transistor (FET) including a first source / drain (S / D) region (412b) and a second source / drain (S / D) region (412a) and one or more channels (408b), the one or more channels being electrically connected to the first S / D region and the second S / D region through a first gate structure; a second FET of a second charge carrier type, the second FET being disposed above the first FET in the Z direction and including a third S / D region (414b) and a fourth S / D region (414a) and one or more channels (408a), the one or more channels being electrically connected to the third S / D region and the fourth S / D region through a second gate structure; and a vertical connector (420) extending in the Z direction from the top surface of the first S / D region (412b) to the bottom surface of the third S / D region (414b) and electrically coupling the first S / D region to the third S / D region.

The invention relates to the technical field of intelligent chips, and discloses a transistor circuit optimization method for improving the heat dissipation performance of an amplifier chip, and the method comprises the steps: carrying out the thermal resistance modeling of an input matching network, and obtaining the temperature rise distribution; a copper-graphene composite thermal conductivity enhancing structure is arranged on a grid wiring path; embedding an aluminum nitride high-thermal-conductivity dielectric layer below the grid electrode and connecting the deep silicon through hole to the substrate heat sink to construct a vertical low-thermal-resistance channel; a heat isolation groove filled with aerogel is arranged between the matching network and the active region to block transverse heat flow; a miniature temperature sensor and a bias control circuit are integrated, and gate voltage drift is dynamically compensated. According to the invention, the active heat dissipation structure matched with the thermal resistance of the input matching network is constructed in the grid region of the transistor, so that local hot spots caused by mismatching of the thermal resistance are eliminated fundamentally; a vertical heat dissipation channel formed by the high thermal conductivity dielectric layer and the deep silicon through hole significantly reduces a thermal resistance path from the grid electrode to the heat sink.

A reference transistor forms part of a measurement circuit coupled to bias control circuitry that is configured to operate a primary transistor at a desired operating point by providing appropriate DC bias voltages to the control terminal of the primary transistor and one or more current terminals of the primary transistor based upon an output of the measurement circuit generated using the reference transistor. A dissipative circuit element is electrically coupled to the reference transistor and is configured to cause the reference transistor to exhibit negative gain at a drain terminal (or other output node) of the reference transistor with respect to alternating-current (AC) electrical signals which may be unintentionally coupled to the gate (or other input node) of the reference transistor.

A bias compensation circuit includes a detection circuit comprising a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal; and a first diode circuit having a first terminal for receiving a second current and a second terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit and provides a second voltage level based on the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current based on the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias level based on the first reference current.

The present invention discloses a bidirectional energy storage inverter, which relates to the technical field of power conversion. It includes an intelligent control module for receiving signals and module control; a charge and discharge control module for controlling the charge and discharge of an energy storage module; an inverter control module for selecting the path state connected to an inverter module and transmitting signals; an inverter module for performing inversion and rectification processing and controlling a power transistor circuit to access a full-bridge inverter circuit; a switching control module for controlling the connection between the inverter module and an AC module; an AC module for outputting and providing alternating current; and an output detection module for voltage detection. The bidirectional energy storage inverter of the present invention completes inversion and rectification processing through the inverter module, cooperates with the charge and discharge control module to control the energy storage and discharge of the energy storage module, controls the inverter control module to connect the power transistor circuit to the full-bridge inverter circuit according to the signals detected by the output detection module, and the switching control module controls the output path so as to maintain the operation of the inverter module.

According to one exemplary embodiment, a chip is described, comprising a plurality of cascode circuits, wherein each cascode circuit has at least one cascode having at least one respective cascode transistor, a voltage generation circuit which is set up to generate control voltages for controlling the cascode transistors of the cascode circuits, a respective transistor circuit for each cascode, which is connected between the voltage generation circuit and the cascode, has a respective source follower and is set up to generate a cascode transistor control voltage for the at least one cascode transistor of the cascode by means of the respective source follower from a respective control voltage of the control voltages generated by the voltage generation circuit.

The present disclosure describes various aspects of implementing a low-dropout regulator in a gate-all-around process. In some aspects, a low-dropout (LDO) regulator circuit includes an amplifier and a power transistor with a source terminal coupled to a power rail. The LDO circuit may also include protection circuitry configured to prevent devices of the circuit from exceeding inter-terminal voltage ratings, which may protect the devices from damage when the LDO circuit is active or inactive. In some implementations, the protection circuitry includes a transistor coupled in series with the power transistor, voltage sources that provide signals or bias at intermediate voltages below a voltage of the power rail, and other transistors that operate based on or apply the intermediate voltages to the devices of the circuit. By so doing, the LDO circuit can be implemented in advanced fabrication processes (e.g., gate-all-around) in which devices may have reduced inter-terminal voltage ratings.

The invention discloses a rail-to-rail input bias current compensation circuit, which is characterized in that an input pair transistor module is formed by a PNP input differential pair and an NPN input differential pair which are connected in parallel, and can be switched to work or work simultaneously in a full common-mode voltage range to adapt to different input voltage conditions; secondly, the current sensing module samples the change of the bias current to generate a sensing current, so that the change of the bias current can be dynamically monitored and compensated; the current mirror module copies the sensing current, the input geminate transistor matching module serves as a matching transistor circuit of the input geminate transistor module, and after the sensing current is reduced, the sensing current is injected into the differential input end of the rail operational amplifier through the high-impedance current mirror module. The technical problems that in an existing PNP and NPN combined compensation method, the input bias current is large, the amplification factor difference of NPN and PNP tubes in a full-temperature region is large, and in a mirror image compensation method, only linear copying can be conducted on a direct-current working point, the nonlinear component of the input bias current Ib changing along with differential mode voltage Vdm cannot be tracked, and consequently nonlinear distortion is serious are solved.

A memory device including a substrate having a first active area and a second active area adjacent to each other in a first horizontal direction is disclosed. A first pass transistor is disposed on the substrate and has a first gate electrode crossing the first active area in the first horizontal direction, and a second pass transistor is disposed on the substrate and has a second gate electrode crossing the second active area in the first horizontal direction. The first active area has, in a planar view, a first recessed portion facing the second gate electrode on one side adjacent to the second active area.

The present disclosure relates to an active directional structure for a test and / or measurement system, comprising: a generator port configured to receive a generator signal; a DUT port arranged for directly or indirectly connecting a DUT; a measurement port configured to output a measurement signal; and a reference port configured to output a reference signal. The active directional structure further comprises: a first converter which is configured to generate a test signal and the reference signal based on the generator signal; and a second converter which is configured to: generate the measurement signal based on the test signal, a reflected signal from the DUT and the reference signal; wherein the first converter and / or the second converter comprise a respective transistor circuit.

The invention relates to an active orientation structure (10) for a test and / or measurement system (60), comprising: a generator port (P1) configured to receive a generator signal; a DUT port (P2) arranged for directly or indirectly connecting a DUT; a measurement port (P3) configured to output a measurement signal; and a reference port (P4) configured to output a reference signal. The active orientation structure (10) further comprises: a first converter (11) configured to generate a test signal and the reference signal based on the generator signal; and a second converter (12) configured to generate the measurement signal based on the test signal, a reflected signal from the DUT, and the reference signal; wherein the first converter (11) and / or the second converter (12) comprise respective transistor circuits.

An oscillating circuit with a withstand voltage mechanism. An inductor circuit is coupled to a pair of oscillating output terminals. A cross-coupled transistor circuit is coupled between the pair of oscillating output terminals and a first terminal. A capacitor circuit is coupled between the pair of oscillating output terminals. A first source degradation circuit includes: a first inductor, a first capacitor, a second capacitor, and a first source degradation transistor. The first inductor is electrically coupled between the first terminal and a first power supply voltage. The first capacitor is electrically coupled between the first terminal and a second terminal. The second capacitor is coupled between the first power supply voltage and a third terminal, wherein the third terminal is coupled to a second power supply voltage. The first source degradation transistor is coupled between the second terminal and the third terminal and is turned on by a first feed voltage.

A self-protection circuitry is configured to receive a first power source. The self-protection circuitry includes a first transistor circuit, a first switch circuit, and a control circuit. The first transistor circuit includes a first input terminal, a first output terminal, and a first control terminal. The first output terminal is electrically connected to a ground terminal, and the first input terminal is configured to receive the first power source. The first switch circuit is electrically connected to the first control terminal and the first input terminal. The control circuit is electrically connected to the first switch circuit, and is configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit to be 10 conducted, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit to be cut off.

The invention discloses a set of transistor structures and a transistor circuit. The transistor circuit includes a transistor and a voltage source. The transistor includes a semiconductor substrate, a gate structure, a channel region and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first end and a second end. The first conductive region is electrically coupled to the first end of the channel region, and the first conductive region includes a top surface and a bottom surface, where the bottom surface of the first conductive region is lower than the semiconductor surface of the semiconductor substrate. The voltage source is electrically coupled to the transistor through a bottom surface of the first conductive region. Compared with the prior art, the complexity of multi-layer interconnection in a new circuit architecture formed by a complementary metal oxide semiconductor circuit formed by the transistors can be reduced, and the speed performance and the anti-noise capability of the new circuit architecture can be improved, so that more and better heat dissipation paths can be created in the new circuit architecture.

The present invention provides an array substrate and display panel. The array substrate comprises: a substrate; a thin-film transistor circuit layer disposed on the substrate and including thin-film transistors; a planarization layer disposed on the thin-film transistor circuit layer; and a first electrode disposed on the planarization layer and electrically connected to the thin-film transistors via vias penetrating the planarization layer. The first electrode comprises a stacked structure of a first film layer, a second film layer, and a third film layer, wherein the first film layer is disposed in contact with the planarization layer, and the second film layer is spaced apart from the planarization layer. Under high-temperature conditions, the first film layer is inert relative to the planarization layer. By adding a first film layer structure within the first electrode, the present invention prevents the first electrode from reacting with water vapor in the planarization layer during high-temperature processes, thereby preventing the generation of hydrogen ions. This, in turn, prevents the reduction of the active layer of the thin-film transistor by hydrogen ions, which typically causes negative drift in the thin-film transistor.

The utility model relates to a silicon-based CMOS and avalanche diode parallel integrated optical sensor. The optical sensor comprises a substrate; the epitaxial layer is positioned on the substrate; one or more single photon avalanche diodes (SPAD) located in the epitaxial layer, the SPAD comprising: a buried layer; the avalanche region is located on the buried layer; the diode doping region is located on the upper surface of the avalanche region; the SPAD electrode leading-out region is located on the buried layer and located on the single side, the two sides or the periphery of the avalanche region; the SPAD electrode contact region is positioned on the upper surface of the SPAD electrode extraction region; the silicon-based CMOS transistor circuits are located in the epitaxial layer, and the single photon avalanche diode and the CMOS transistor circuits are located on the same plane and are electrically connected. According to the optical sensor, the avalanche diode and the CMOS circuit are in the same plane, so that all functions of the sensor can be completed on one chip.

This invention provides a photodetector including SPADs, which significantly reduces substrate fabrication costs compared to InGaAs, resulting in fewer residual pulses and suppressed DCR. The photodetector of this invention detects incident light from an object and includes: (i) a P-type silicon (Si) substrate; (ii) a P-type germanium (Ge) layer formed by epitaxial growth on a first surface of the P-type silicon (Si) substrate; (iii) a P-type thin-film silicon (Si) layer formed on the P-type germanium (Ge) layer; and (iv) the P-type thin-film silicon (Si) layer is divided into a first region and a second region by shallow trench isolation, wherein a plurality of single-photon detection diodes (SPADs) arranged in an array are formed in the first region, and a CMOS transistor circuit driving the SPADs is formed in the second region.

The invention relates to an ultra-low power consumption energy storage and management circuit special for a friction nanometer generator based on a transformer and a transistor circuit, and the circuit comprises a transformer grid-connected current increasing module which converts the high-voltage small current of TENG into low-voltage large current, and improves the power generation utilization rate; the transistor rectification module rectifies the low-voltage large current into direct current; the capacitor energy storage module is used for storing direct current; and the power supply management module monitors the capacitor voltage in real time, and when the capacitor voltage reaches a preset value, a discharge mode is switched to provide stable electric energy for electric appliances. Aiming at the problems of low energy conversion efficiency, insufficient automation and dependence on manual intervention of an energy storage circuit of a traditional friction nano generator (TENG), the circuit solves the problem of energy loss caused by high internal resistance of the TENG through current amplification by a transformer, charge and discharge control by a transistor and ultra-low power consumption design, realizes efficient energy storage and automatic management, and is suitable for large-scale popularization and application. The system is suitable for micro-energy scenes such as Internet of Things and wearable equipment, and has the characteristics of high charging speed, high energy utilization rate and system self-locking control.

A semiconductor memory device includes: a substrate including a first region and a second region, the first region includes a peripheral circuit and a first active region (FAR), and the second region includes memory cell blocks. The FAR includes a FAR first extension extending in a first direction, a FAR second extension extending in a second direction, and a FAR third extension extending in a third direction. The FAR first extension, the FAR second extension, and the FAR third extension form an angle greater than 90 degrees relative to one another. The device includes a first pass transistor circuit configured to transmit driving signals, and the first pass transistor circuit includes a FAR first gate structure on the FAR first extension, a FAR second gate structure on the FAR second extension, a FAR third gate structure on the FAR third extension, and a first shared source / drain.

Provided are an underlying transistor circuit of a semiconductor memory and a preparation method for the same, which relate to the integrated circuit technologies. The circuit of the present disclosure includes a row line layer, a column line layer positioned above the row line layer, and an insulating isolation layer between the row line layer and the column line layer, with directions of the row lines and the column lines being perpendicular to each other. Holes penetrating the column line layer and the insulating isolation layer are provided at intersections of row lines and column lines; upper and lower segments of the hole are both filled with semiconductor materials; the semiconductor material in the upper segment of the hole has a doping type the same as that of the row line, while the semiconductor material in the lower segment of the hole has a doping type opposite to that of the row line, thus, a transistor is formed in each hole. The preparation process of the present disclosure is simple and cost-effective.